Main handout
Signed-off-by: Daniel Schwyn <daniel.schwyn@inf.ethz.ch>
This commit is contained in:
Daniel Schwyn
commit
6d444bf552
101
.clang-format
Normal file
101
.clang-format
Normal file
@ -0,0 +1,101 @@
|
||||
---
|
||||
Language: Cpp
|
||||
AccessModifierOffset: -4
|
||||
AlignAfterOpenBracket: Align
|
||||
AlignConsecutiveAssignments: false
|
||||
AlignConsecutiveDeclarations: false
|
||||
AlignEscapedNewlines: Right
|
||||
AlignOperands: true
|
||||
AlignTrailingComments: true
|
||||
AllowAllParametersOfDeclarationOnNextLine: false
|
||||
AllowShortBlocksOnASingleLine: false
|
||||
AllowShortCaseLabelsOnASingleLine: false
|
||||
AllowShortFunctionsOnASingleLine: Empty
|
||||
AllowShortIfStatementsOnASingleLine: false
|
||||
AllowShortLoopsOnASingleLine: false
|
||||
AlwaysBreakAfterDefinitionReturnType: None
|
||||
AlwaysBreakAfterReturnType: None
|
||||
AlwaysBreakBeforeMultilineStrings: false
|
||||
BasedOnStyle: WebKit
|
||||
BinPackArguments: true
|
||||
BinPackParameters: true
|
||||
BraceWrapping:
|
||||
AfterClass: false
|
||||
AfterControlStatement: false
|
||||
AfterEnum: false
|
||||
AfterFunction: true
|
||||
AfterNamespace: false
|
||||
AfterStruct: false
|
||||
AfterUnion: false
|
||||
AfterExternBlock: false
|
||||
BeforeCatch: false
|
||||
BeforeElse: false
|
||||
IndentBraces: false
|
||||
SplitEmptyFunction: false
|
||||
SplitEmptyRecord: false
|
||||
SplitEmptyNamespace: false
|
||||
BreakBeforeBinaryOperators: All
|
||||
BreakBeforeBraces: WebKit
|
||||
BreakBeforeTernaryOperators: true
|
||||
BreakAfterJavaFieldAnnotations: false
|
||||
BreakStringLiterals: true
|
||||
ColumnLimit: 90
|
||||
CommentPragmas: '^ IWYU pragma:'
|
||||
CompactNamespaces: false
|
||||
ContinuationIndentWidth: 4
|
||||
Cpp11BracedListStyle: false
|
||||
DerivePointerAlignment: false
|
||||
DisableFormat: false
|
||||
ExperimentalAutoDetectBinPacking: false
|
||||
FixNamespaceComments: false
|
||||
ForEachMacros:
|
||||
- foreach
|
||||
- Q_FOREACH
|
||||
- BOOST_FOREACH
|
||||
IncludeBlocks: Preserve
|
||||
IncludeCategories:
|
||||
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
|
||||
Priority: 2
|
||||
- Regex: '^(<|"(gtest|gmock|isl|json)/)'
|
||||
Priority: 3
|
||||
- Regex: '.*'
|
||||
Priority: 1
|
||||
IncludeIsMainRegex: '(Test)?$'
|
||||
IndentCaseLabels: false
|
||||
IndentPPDirectives: AfterHash
|
||||
IndentWidth: 4
|
||||
IndentWrappedFunctionNames: false
|
||||
JavaScriptQuotes: Leave
|
||||
JavaScriptWrapImports: true
|
||||
KeepEmptyLinesAtTheStartOfBlocks: false
|
||||
MacroBlockBegin: ''
|
||||
MacroBlockEnd: ''
|
||||
MaxEmptyLinesToKeep: 2
|
||||
NamespaceIndentation: Inner
|
||||
PenaltyBreakAssignment: 50
|
||||
PenaltyBreakBeforeFirstCallParameter: 19
|
||||
PenaltyBreakComment: 200
|
||||
PenaltyBreakFirstLessLess: 120
|
||||
PenaltyBreakString: 2
|
||||
PenaltyExcessCharacter: 30
|
||||
PenaltyReturnTypeOnItsOwnLine: 60
|
||||
PointerAlignment: Right
|
||||
ReflowComments: true
|
||||
SortIncludes: false
|
||||
SortUsingDeclarations: true
|
||||
SpaceAfterCStyleCast: false
|
||||
SpaceAfterTemplateKeyword: true
|
||||
SpaceBeforeAssignmentOperators: true
|
||||
SpaceBeforeParens: ControlStatements
|
||||
SpaceInEmptyParentheses: false
|
||||
SpacesBeforeTrailingComments: 2
|
||||
SpacesInAngles: false
|
||||
SpacesInContainerLiterals: true
|
||||
SpacesInCStyleCastParentheses: false
|
||||
SpacesInParentheses: false
|
||||
SpacesInSquareBrackets: false
|
||||
Standard: Cpp11
|
||||
TabWidth: 4
|
||||
UseTab: Never
|
||||
...
|
||||
|
||||
51
.gitignore
vendored
Normal file
51
.gitignore
vendored
Normal file
@ -0,0 +1,51 @@
|
||||
# vim swap files
|
||||
*~
|
||||
*.swp
|
||||
.*.swo
|
||||
.*.swp
|
||||
\#*
|
||||
.\#*
|
||||
.~*
|
||||
|
||||
# ctags
|
||||
tags
|
||||
|
||||
.settings
|
||||
/.dist-buildwrapper
|
||||
/build
|
||||
.cproject
|
||||
.project
|
||||
.vscode
|
||||
.arcconfig
|
||||
sftp-config.json
|
||||
.sync-config.cson
|
||||
|
||||
/.metadata/
|
||||
/toolchain/
|
||||
*.pyc
|
||||
|
||||
# Haskell and C intermediate files
|
||||
*.o
|
||||
*.hi
|
||||
*.hi-boot
|
||||
*.o-boot
|
||||
|
||||
# ctags
|
||||
.tags_sorted_by_file
|
||||
.tags
|
||||
|
||||
# Cscope
|
||||
cscope.out
|
||||
|
||||
# Builds
|
||||
build*/
|
||||
|
||||
# tup
|
||||
.tup
|
||||
bin/
|
||||
/Tuprules.lua
|
||||
/logs
|
||||
|
||||
# clang
|
||||
.clang_complete
|
||||
compile_commands.json
|
||||
50
AUTHORS
Normal file
50
AUTHORS
Normal file
@ -0,0 +1,50 @@
|
||||
The following people have contributed code to Barrelfish:
|
||||
|
||||
Reto Achermann <reto.achermann@inf.ethz.ch>
|
||||
Zachary Anderson <zachary.anderson@inf.ethz.ch>
|
||||
Paul Barham <Paul.Barham@microsoft.com>
|
||||
Andrew Baumann <andrewb@inf.ethz.ch>
|
||||
Richard Black <Richard.Black@microsoft.com>
|
||||
Justin Cappos <justin@cs.arizona.edu>
|
||||
Zaheer Chothia <zchothia@inf.ethz.ch>
|
||||
Andreas Dillier <dilliera@ethz.ch>
|
||||
Pierre-Evariste Dagand <pedagand@gmail.com>
|
||||
Oleg Godunok <ogodunok@gmail.com>
|
||||
Raphael Fuchs <fuchs.raphael@gmail.com>
|
||||
Simon Gerber <simon.gerber@inf.ethz.ch>
|
||||
David Gerhard <gerhardd@student.ethz.ch>
|
||||
Jana Giceva <gicevaj@inf.ethz.ch>
|
||||
Ankush Gupta <guptaan@student.ethz.ch>
|
||||
Claudio Föllmi <foellmic@student.ethz.ch>
|
||||
Tim Harris <tharris@microsoft.com>
|
||||
Samuel Hitz <samuel.hitz@gmail.com>
|
||||
Orion Hodson <ohodson@microsoft.com>
|
||||
Moritz Hoffmann <moritzho@inf.ethz.ch>
|
||||
Lukas Humbel <humbell@ethz.ch>
|
||||
Rebecca Isaacs <Rebecca.Isaacs@microsoft.com>
|
||||
Stefan Kästle <stefan.kaestle@inf.ethz.ch>
|
||||
Antoine Kaufmann <antoinek@student.ethz.ch>
|
||||
Yauhen Klimiankou <yauhenk@student.ethz.ch>
|
||||
Kornilios Kourtis <kkourt@inf.ethz.ch>
|
||||
Ihor Kuz <ihor.kuz@nicta.com.au>
|
||||
Reto Lindegger <lreto@ethz.ch>
|
||||
Zeus Gómez Marmolejo <zeus.gomez@bsc.es>
|
||||
Ross McIlroy <rmcilroy@microsoft.com>
|
||||
Dominik Menzi <dmenzi@student.ethz.ch>
|
||||
Wang Nan <wangnan0@huawei.com>
|
||||
Mark Nevill <mark@nevill.ch>
|
||||
Mateusz Olczak <mateusz@olczak.se>
|
||||
Simon Peter <speter@inf.ethz.ch>
|
||||
Amar Phanishayee <amarp+@cs.cmu.edu>
|
||||
Kaveh Razavi <razavik@student.ethz.ch>
|
||||
Jan S. Rellermeyer <rellermeyer@inf.ethz.ch>
|
||||
Timothy Roscoe <troscoe@inf.ethz.ch>
|
||||
Raffaele Sandrini <rasa@student.ethz.ch>
|
||||
Bram Scheidegger <brams@student.ethz.ch>
|
||||
Adrian Schüpbach <scadrian@inf.ethz.ch>
|
||||
Akhilesh Singhania <akhi@inf.ethz.ch>
|
||||
Pravin Shinde <shindep@student.ethz.ch>
|
||||
Manuel Stocker <mensi@vis.ethz.ch>
|
||||
Animesh Trivedi <atrivedi@student.ethz.ch>
|
||||
Sebastian Wicki <swicki@student.ethz.ch>
|
||||
Gerd Zellweger <mail@gerdzellweger.com>
|
||||
21
LICENSE
Normal file
21
LICENSE
Normal file
@ -0,0 +1,21 @@
|
||||
Copyright (c) 2007, 2008, 2009, 2010, 2011,2020,2021 ETH Zurich.
|
||||
Copyright (c) 2021 University of British Columbia.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
279
README.Barrelfish
Normal file
279
README.Barrelfish
Normal file
@ -0,0 +1,279 @@
|
||||
##########################################################################
|
||||
Copyright (c) 2009-2018, ETH Zurich.
|
||||
All rights reserved.
|
||||
|
||||
This file is distributed under the terms in the attached LICENSE file.
|
||||
If you do not find this file, copies can be found by writing to:
|
||||
ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
##########################################################################
|
||||
|
||||
Barrelfish Overview
|
||||
--------------------------------
|
||||
|
||||
Barrelfish currently runs on:
|
||||
|
||||
* x86 CPUs in AMD64 mode. The following are known to work:
|
||||
|
||||
- Intel Xeon Clovertown, Gainestown, Beckton, IvyBridge, Haswell (X5355,
|
||||
E5520, X7560, L5520, L7555, E5-2670v2, E3-1245v3)
|
||||
- AMD Opteron Italy, Santa Rosa, Barcelona, Shanghai, Istanbul, Magny Cours
|
||||
(275, 2220, 8350, 8374, 8380, 8431, 6174)
|
||||
- Intel Xeon Phi Knights Corner
|
||||
- QEMU simulator (2.2.10)
|
||||
|
||||
* ARM CPUs, specifically ARMv8 and ARMv7. The following platforms are known to work:
|
||||
|
||||
- ARMv7: The Texas Instruments OMAP4460 Pandaboard ES SoC
|
||||
(Barrelfish runs on both the A9 and the M3 cores)
|
||||
- ARMv7: The ARM VExpress EMM board as simulated by GEM5
|
||||
- ARMv8: Cavium ThunderX2
|
||||
- ARMv8: Applied Micro X-Gene
|
||||
- ARMv8: NXP i.MX 8 SoC on a Toradex iMX8X Colibri board
|
||||
- There is also limited support for the Netronome i8000 card, incorporating
|
||||
a single Intel iXP2800 processor
|
||||
|
||||
This README file provides instructions for the x86 architecture. For other
|
||||
architectures, please refer to the architecture-specific technical notes (e.g.,
|
||||
see TN 06 for the SCC, and TN 17 for ARM).
|
||||
|
||||
You can either generate the latest documentation from this source-code
|
||||
(instructions at end of this file), or visit the Barrelfish_ website
|
||||
to download them.
|
||||
|
||||
.. _Barrelfish: http://www.barrelfish.org/
|
||||
|
||||
Supported PC hardware
|
||||
--------------------------------
|
||||
|
||||
The biggest compatibility problems are likely to be in the PCI/ACPI code. We
|
||||
usually discover new quirks (or missing functionality in the ACPI glue code)
|
||||
on each new machine we test. The following systems are known to work:
|
||||
|
||||
* Intel x5000XVN
|
||||
* Tyan n6650W and S4985
|
||||
* Supermicro H8QM3-2
|
||||
* Dell PowerEdge R610 and R905
|
||||
* Sun Fire X2270 and X4440
|
||||
* Intel/Quanta QSSC-S4R
|
||||
* Lenovo X200 and X301 laptops
|
||||
* ASUS Eee PC 1015PEM netbooks
|
||||
|
||||
We have support for the following NICs:
|
||||
* The e1000n should work with most recent Intel gigabit ethernet
|
||||
controllers (see the list in devices/e1000.dev). We've mostly used the
|
||||
82572EI (PCI device ID 0x1082).
|
||||
* Intel i82599 (or X520) 10GbE
|
||||
* Solarflare sfn5122f 10GbE
|
||||
|
||||
You should also be able to boot Barrelfish on a recent version of QEMU (2.14);
|
||||
note that the e1000 device emulated by QEMU is not supported by our driver.
|
||||
|
||||
Required Tools
|
||||
--------------------------------
|
||||
|
||||
Our toolchain tracks Ubuntu LTS releases, and this is what we use to
|
||||
run our nightly tests. If you are running Ubuntu LTS (18.04.1 at time
|
||||
of writing), this means the following:
|
||||
|
||||
* GCC 7.4.0 for x86_64, ARMv7 and ARMv8
|
||||
- On Ubuntu LTS install packages:
|
||||
build-essential g++
|
||||
gcc-arm-linux-gnueabi g++-arm-linux-gnueabi
|
||||
gcc-aarch64-linux-gnu g++-aarch64-linux-gnu
|
||||
* GNU binutils (2.30 is supported)
|
||||
* GNU make
|
||||
* GHC v8.0.2 and Parsec 3.1
|
||||
- On Ubuntu LTS, install the following packages:
|
||||
cabal-install libghc-src-exts-dev libghc-ghc-paths-dev
|
||||
libghc-parsec3-dev libghc-random-dev libghc-ghc-mtl-dev
|
||||
libghc-async-dev libghc-aeson-pretty-dev libghc-aeson-dev
|
||||
libghc-missingh-dev
|
||||
- Then, run cabal update && cabal install bytestring-trie pretty-simple
|
||||
* FreeBSD's libelf:
|
||||
- On Ubuntu install the following packages:
|
||||
libelf-freebsd-dev freebsd-glue
|
||||
* Optional: LibUSB 1.0 (for the usbboot tool):
|
||||
- On Ubuntu install libusb-1.0-0-dev
|
||||
|
||||
* Optional: QEMU with e1000e EFI ROM:
|
||||
- On Ubuntu install qemu-system-x86 qemu-efi qemu-ipxe
|
||||
- Then cd /usr/lib/ipxe/qemu/ &&
|
||||
sudo wget https://github.com/qemu/qemu/raw/master/pc-bios/efi-e1000e.rom
|
||||
|
||||
* Optional ARMv8 support:
|
||||
- prefix all deb entries in /etc/apt/sources.list with [arch=amd64]
|
||||
- add "deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports bionic main universe"
|
||||
to sources.list
|
||||
- dpkg --add-architecture arm64 && apt update && apt install gnu-efi:arm64 libefiboot-dev
|
||||
|
||||
Building
|
||||
--------------------------------
|
||||
|
||||
1. Assuming you have already unpacked the sources, create a build directory ::
|
||||
|
||||
$ mkdir build && cd build
|
||||
|
||||
1. Run ``hake.sh``, giving it the path to the source directory and target
|
||||
architecture(s) ::
|
||||
|
||||
$ ../hake/hake.sh -s ../ -a x86_64
|
||||
|
||||
This will configure the build directory and use GHC to compile and then run
|
||||
hake, a tool used to generate the ``Makefile``.
|
||||
|
||||
3. Optionally, edit the configuration parameters in ``hake/Config.hs`` and
|
||||
run ``make rehake`` to apply them.
|
||||
|
||||
4. Run make, and wait ::
|
||||
|
||||
$ make X86_64_Basic
|
||||
|
||||
5. If everything worked, you should now be able to run Barrelfish inside QEMU
|
||||
(make sure you have followed the optional qemu step in required tools) ::
|
||||
|
||||
$ make qemu_x86_64
|
||||
|
||||
Installing and Booting
|
||||
--------------------------------
|
||||
|
||||
Barrelfish requires a Multiboot-compliant bootloader that is capable of loading
|
||||
an ELF64 image. At the time of writing, this doesn't include the default GRUB.
|
||||
Your options are either:
|
||||
|
||||
* use the pre-loader "elver" that can be found in the tools directory
|
||||
* patch GRUB to support a 64-bit kernel image, using this patch_.
|
||||
|
||||
.. _patch: http://savannah.gnu.org/bugs/?17963
|
||||
|
||||
"Installing" Barrelfish currently consists of copying the ELF files for the CPU
|
||||
driver and user programs to a location that the target machine can boot from,
|
||||
and writing a suitable menu.lst file that instructs the bootloader (GRUB) which
|
||||
programs to load and the arguments to pass them.
|
||||
|
||||
If you specify an appropriate INSTALL_PREFIX, ``make install`` will copy the
|
||||
binaries to the right place for you, eg ::
|
||||
|
||||
$ make install INSTALL_PREFIX=/tftpboot/barrelfish
|
||||
|
||||
We usually boot Barrelfish via PXE/TFTP, although loading from a local disk
|
||||
also works. Instructions for setting up GRUB to do this are beyond the scope of
|
||||
this document. Assuming you have such a setup, a sample menu.lst can
|
||||
be found in build/x86/menu.lst.x86_64 after executin make qemu_x86_64. It
|
||||
is a basic diskless boot that doesn't do anything useful beyond probing the
|
||||
PCI buses and starting a basic shell.
|
||||
|
||||
There are many other programs you can load (take a look around the usr tree for
|
||||
examples). To start a program on a core other than the BSP core, pass
|
||||
``core=N`` as its first argument.
|
||||
|
||||
If things work, you should see output on both the VGA console and COM1.
|
||||
|
||||
Generating Documentation
|
||||
--------------------------------
|
||||
|
||||
Barrelfish documentation can be found on Barrelfish website
|
||||
(http://www.barrelfish.org/). And it can be also generated from the code tree.
|
||||
For documentation generation, you will need ``latex`` packages installed,
|
||||
including support for ``pdflatex``. Following are the instructions for
|
||||
generating the documentation assuming you have already unpacked the sources ::
|
||||
|
||||
$ mkdir build && cd build
|
||||
$ ../hake/hake.sh -s ../
|
||||
$ make docs
|
||||
|
||||
You will find all the technotes in ``docs/`` directory.
|
||||
|
||||
Known Issues
|
||||
--------------------------------
|
||||
|
||||
There are many. Those you're likely to encounter include:
|
||||
|
||||
* The documentation is incomplete and out of date.
|
||||
* Some drivers and user programs are known not to build, and are
|
||||
not included in the default set of targets (MODULES) in the Makefile.
|
||||
|
||||
Likely FAQs
|
||||
--------------------------------
|
||||
|
||||
Q: How do I run a program?
|
||||
A: Add it to the boot sequence by specifying the module in your menu.lst file.
|
||||
For example, to run the memtest program, add the line:
|
||||
module /PATH/x86_64/sbin/memtest
|
||||
to the end of menu.lst, where PATH is relative either to your TFTP
|
||||
server's root directory (when booting on hardware) or to your build
|
||||
directory (when using a simulator such as QEMU).
|
||||
If memtest runs, you should see it output "memtest passed successfully!".
|
||||
|
||||
Q: How do develop a program?
|
||||
A: Check out Technote 18, Practical Guide. Either on barrelfish.org or
|
||||
in the generated technotes (see Generating Documentation)
|
||||
|
||||
|
||||
Q: Where's the CPU driver?
|
||||
A: It's in the directory named kernel :) But don't worry, it really does run
|
||||
independently on each core.
|
||||
|
||||
Q: Where is the source for the SPLASH2 benchmarks? It seems to be missing.
|
||||
A: The license for these prevents redistribution, so we were forced to ship our
|
||||
changes as a patch. See usr/splash2/README for further instructions.
|
||||
|
||||
Q: Can I use a debugger?
|
||||
A: Maybe. There are two options at the moment:
|
||||
* On a simulator, using whatever debug interfaces it supports.
|
||||
For QEMU, you could try the "debugsim" target.
|
||||
* On hardware, using the kernel-mode remote GDB stubs that operate on the
|
||||
primary serial port and are entered in response to a kernel trap or
|
||||
exception. However, these are not well maintained, and may not be usable
|
||||
beyond reading/writing memory locations and inspecting the stack.
|
||||
When debugging the kernel, beware that it is relocated to an address
|
||||
determined at core boot time. Look for output such as:
|
||||
"Kernel starting at address 0xffffffffc072b000".
|
||||
|
||||
Q: Where can I find more information, including papers and new releases?
|
||||
A: http://www.barrelfish.org/
|
||||
http://wiki.barrelfish.org/
|
||||
|
||||
Q: Can I contribute?
|
||||
A: We'd certainly like to hear from you. Feel free to send patches (or even
|
||||
git merge requests) to the Barrelfish mailing list.
|
||||
|
||||
To keep track of contributions to Barrelfish, we use a sign-off procedure
|
||||
similar to the Linux kernel:
|
||||
|
||||
The sign-off is a simple line at the end of the explanation for the patch,
|
||||
which certifies that you wrote it or otherwise have the right to pass it on
|
||||
as an open-source patch. The rules are pretty simple: if you can certify
|
||||
the below:
|
||||
|
||||
Developer's Certificate of Origin 1.1
|
||||
|
||||
By making a contribution to this project, I certify that:
|
||||
|
||||
(a) The contribution was created in whole or in part by me and I
|
||||
have the right to submit it under the open source license
|
||||
indicated in the file; or
|
||||
|
||||
(b) The contribution is based upon previous work that, to the best
|
||||
of my knowledge, is covered under an appropriate open source
|
||||
license and I have the right under that license to submit that
|
||||
work with modifications, whether created in whole or in part
|
||||
by me, under the same open source license (unless I am
|
||||
permitted to submit under a different license), as indicated
|
||||
in the file; or
|
||||
|
||||
(c) The contribution was provided directly to me by some other
|
||||
person who certified (a), (b) or (c) and I have not modified
|
||||
it.
|
||||
|
||||
(d) I understand and agree that this project and the contribution
|
||||
are public and that a record of the contribution (including all
|
||||
personal information I submit with it, including my sign-off) is
|
||||
maintained indefinitely and may be redistributed consistent with
|
||||
this project or the open source license(s) involved.
|
||||
|
||||
then you just add a line saying
|
||||
|
||||
Signed-off-by: Random J Developer <random@developer.example.org>
|
||||
|
||||
Note that git has support for adding such a message in the end of the commit
|
||||
log message.
|
||||
59
README.md
Normal file
59
README.md
Normal file
@ -0,0 +1,59 @@
|
||||
# AOS Code Repository
|
||||
|
||||
Welcome to AOS. This is the code handout repository.
|
||||
|
||||
The code in this repository is a simplified version of the [Barrelfish OS](barrelfish.org).
|
||||
|
||||
## License
|
||||
|
||||
see the LICENSE file.
|
||||
|
||||
## Dependencies
|
||||
|
||||
Before you can start, make sure you have installed the following dependencies:
|
||||
|
||||
```
|
||||
apt-get install build-essential bison flex ghc libghc-src-exts-dev \
|
||||
libghc-ghc-paths-dev libghc-parsec3-dev libghc-random-dev \
|
||||
libghc-ghc-mtl-dev libghc-async-dev picocom cabal-install freebsd-glue \
|
||||
libelf-freebsd-dev git gcc-aarch64-linux-gnu g++-aarch64-linux-gnu \
|
||||
qemu-efi-aarch64 qemu-system-arm qemu-utils python3 parted wget mtools
|
||||
|
||||
wget -P $HOME/bin https://github.com/NXPmicro/mfgtools/releases/download/uuu_1.4.165/uuu
|
||||
chmod 755 $HOME/bin/uuu
|
||||
```
|
||||
|
||||
## Docker
|
||||
|
||||
Use the following command to obtain and start a Docker container with all dependencies.
|
||||
|
||||
```
|
||||
./tools/bfdocker.sh
|
||||
```
|
||||
|
||||
## Building
|
||||
|
||||
To build Barrelfish, create a build directory, and execute Hake to generate the Makefile
|
||||
|
||||
```
|
||||
mkdir build
|
||||
cd build
|
||||
../hake/hake.sh -s ../ -a armv8
|
||||
```
|
||||
|
||||
Then you can use `make` to build Barrelfish. To obtain an overview of all targets execute
|
||||
```
|
||||
make help
|
||||
```
|
||||
|
||||
Likewise, for all platforms that can be build
|
||||
|
||||
```
|
||||
make help-platforms
|
||||
```
|
||||
|
||||
and finally the boot targets with
|
||||
|
||||
```
|
||||
make help-boot
|
||||
```
|
||||
13
capabilities/Hakefile
Normal file
13
capabilities/Hakefile
Normal file
@ -0,0 +1,13 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Copyright (c) 2007-2009, ETH Zurich.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This file is distributed under the terms in the attached LICENSE file.
|
||||
-- If you do not find this file, copies can be found by writing to:
|
||||
-- ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
--
|
||||
-- Hakefile for /capabilities/
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
[ hamletFile (options arch) "caps" | arch <- allArchitectures ]
|
||||
388
capabilities/caps.hl
Normal file
388
capabilities/caps.hl
Normal file
@ -0,0 +1,388 @@
|
||||
/*
|
||||
* Copyright (c) 2009, 2010, 2012, 2015, 2016, ETH Zurich.
|
||||
* Copyright (c) 2015, 2016 Hewlett Packard Enterprise Development LP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/**
|
||||
Hamlet input file.
|
||||
|
||||
This file defines the Barrelfish capability type system.
|
||||
|
||||
(Meta-)Comments about the syntax are enclosed between /** ... **/
|
||||
Comments of the Hamlet language are enclosed between /* ... */
|
||||
**/
|
||||
|
||||
/** We can define some constants using the "define" construct **/
|
||||
|
||||
/* XXX: these must match the corresponding OBJBITS definitions in
|
||||
* barrelfish_kpi/capabilities.h */
|
||||
|
||||
/* Size of L2 CNode: L2 resolves 8 bits of Cap address space */
|
||||
define objsize_l2cnode 16384;
|
||||
/* Size of DCB: */
|
||||
define objsize_dispatcher 1024;
|
||||
/* Size of (x86_64) VNode: */
|
||||
define objsize_vnode 4096; /* BASE_PAGE_SIZE */
|
||||
/* Size of ARMv7 VNodes */
|
||||
define objsize_vnode_arm_l1 16384;
|
||||
define objsize_vnode_arm_l2 1024;
|
||||
/* size of a kernel control block */
|
||||
define objsize_kcb 131072; /* 128*1024, OBJSIZE_KCB */
|
||||
/* size of a mapping cap:
|
||||
* if mappings are zero-sized they mess up range queries */
|
||||
define objsize_mapping 1;
|
||||
|
||||
/**
|
||||
The capabilities of the whole system are listed thereafter.
|
||||
The minimal definition consists of a name and an empty body.
|
||||
**/
|
||||
|
||||
cap Null is_never_copy {
|
||||
/* Null/invalid object type */
|
||||
};
|
||||
|
||||
cap Memory abstract {
|
||||
/**
|
||||
For a populated cap, we need to give the type and name of each
|
||||
of its fields, such as:
|
||||
"genpaddr base;" for instance
|
||||
|
||||
In order to implement various comparisons, we need to specify a address
|
||||
and size for each type that is backed by memory. The size may be
|
||||
specified directly with "size" or as "size_bits".
|
||||
|
||||
Additional equality fields can be specified with an "eq" prefix, as in
|
||||
"eq genpaddr base;"
|
||||
**/
|
||||
|
||||
address genpaddr base; /* Physical base address of Memory object */
|
||||
size gensize bytes; /* Size of region in bytes */
|
||||
pasid pasid; /* Physical Address Space ID */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* Physical address range (root of cap tree) */
|
||||
cap PhysAddr from_self inherit Memory;
|
||||
|
||||
cap Mapping abstract {
|
||||
"struct capability" cap;
|
||||
eq "struct cte" ptable;
|
||||
/* We currently never use the offset into the source capability, so remove
|
||||
* it to make room for a more expressive way of referring to the pte */
|
||||
/* uint32 offset; */
|
||||
eq uint16 entry;
|
||||
uint16 pte_count;
|
||||
|
||||
address { get_address(cap) };
|
||||
size { objsize_mapping };
|
||||
};
|
||||
|
||||
cap VNode abstract {
|
||||
address genpaddr base; /* Base address of VNode */
|
||||
size { objsize_vnode };
|
||||
};
|
||||
|
||||
/** The following caps are similar to the previous one **/
|
||||
|
||||
/* RAM memory object */
|
||||
cap RAM from PhysAddr from_self inherit Memory;
|
||||
|
||||
/* Abstract CNode, need to define size */
|
||||
cap CNode abstract {
|
||||
address lpaddr cnode; /* Base address of CNode */
|
||||
caprights rightsmask; /* Cap access rights */
|
||||
};
|
||||
|
||||
/* Level 1 CNode table, resizable */
|
||||
cap L1CNode from RAM inherit CNode {
|
||||
size gensize allocated_bytes; /* Allocated size of L1 CNode in bytes */
|
||||
};
|
||||
|
||||
/* Level 2 CNode table, resolves 8 bits of cap address */
|
||||
cap L2CNode from RAM inherit CNode {
|
||||
size { objsize_l2cnode }; /* Size of L2 CNode in bytes (16kB) */
|
||||
};
|
||||
|
||||
cap FCNode {
|
||||
/* Foreign CNode capability */
|
||||
|
||||
eq genpaddr cnode; /* Base address of CNode */
|
||||
eq uint8 bits; /* Number of bits this CNode resolves */
|
||||
caprights rightsmask;
|
||||
eq coreid core_id; /* The core the cap is local on */
|
||||
uint8 guard_size; /* Number of bits in guard */
|
||||
caddr guard; /* Bitmask already resolved when reaching this CNode */
|
||||
};
|
||||
|
||||
/** Dispatcher is interesting is several ways. **/
|
||||
|
||||
/**
|
||||
XXX: The whole multi_retype stuff is hack in hamlet that should be removed as
|
||||
soon as parts of an object can be retyped individually. -MN
|
||||
**/
|
||||
|
||||
cap Dispatcher from RAM {
|
||||
/* Dispatcher */
|
||||
|
||||
/**
|
||||
The Dispatcher is a special case that can be retyped several
|
||||
times to an end-point
|
||||
**/
|
||||
/** Note: This must be the first statement */
|
||||
can_retype_multiple;
|
||||
|
||||
/**
|
||||
We allow the use of unknow structures. However, equality will
|
||||
be defined by address, not by structure.
|
||||
**/
|
||||
"struct dcb" dcb; /* Pointer to kernel DCB */
|
||||
|
||||
address { mem_to_phys(dcb) };
|
||||
size { objsize_dispatcher };
|
||||
};
|
||||
|
||||
cap EndPointLMP from Dispatcher {
|
||||
/* IDC endpoint */
|
||||
|
||||
"struct dcb" listener; /* Dispatcher listening on this endpoint */
|
||||
lvaddr epoffset; /* Offset of endpoint buffer in disp frame */
|
||||
uint32 epbuflen; /* Length of endpoint buffer in words */
|
||||
uint16 iftype; /* interface of the endpoint */
|
||||
address { mem_to_phys(listener) };
|
||||
|
||||
/** XXX
|
||||
Preferable definitions for address and size would be as below. These
|
||||
should be used as soon as the whole multi retype hack stuff is fixed:
|
||||
|
||||
address { mem_to_phys(listener + epoffset) };
|
||||
size { epbuflen };
|
||||
|
||||
-MN
|
||||
**/
|
||||
};
|
||||
|
||||
/** Then, we go back to routine **/
|
||||
|
||||
cap Frame from RAM from_self inherit Memory;
|
||||
|
||||
cap Frame_Mapping from Frame inherit Mapping;
|
||||
|
||||
cap EndPointUMP from RAM inherit Memory {
|
||||
uint16 iftype;
|
||||
};
|
||||
|
||||
cap EndPointUMP_Mapping from EndpointUMP inherit Mapping;
|
||||
|
||||
cap DevFrame from PhysAddr from_self inherit Memory;
|
||||
|
||||
cap DevFrame_Mapping from DevFrame inherit Mapping;
|
||||
|
||||
cap Kernel is_always_copy {
|
||||
/* Capability to a kernel */
|
||||
};
|
||||
|
||||
|
||||
/* x86_64-specific capabilities: */
|
||||
|
||||
/* PML5 */
|
||||
cap VNode_x86_64_pml5 from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_64_pml5_Mapping from VNode_x86_64_pml5 inherit Mapping;
|
||||
|
||||
/* PML4 */
|
||||
cap VNode_x86_64_pml4 from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_64_pml4_Mapping from VNode_x86_64_pml4 inherit Mapping;
|
||||
|
||||
/* PDPT */
|
||||
cap VNode_x86_64_pdpt from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_64_pdpt_Mapping from VNode_x86_64_pdpt inherit Mapping;
|
||||
|
||||
/* Page directory */
|
||||
cap VNode_x86_64_pdir from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_64_pdir_Mapping from VNode_x86_64_pdir inherit Mapping;
|
||||
|
||||
/* Page table */
|
||||
cap VNode_x86_64_ptable from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_64_ptable_Mapping from VNode_x86_64_ptable inherit Mapping;
|
||||
|
||||
/* Extended page table types for x86 nested paging */
|
||||
cap VNode_x86_64_ept_pml4 from RAM inherit VNode;
|
||||
cap VNode_x86_64_ept_pml4_Mapping from VNode_x86_64_ept_pml4 inherit Mapping;
|
||||
cap VNode_x86_64_ept_pdpt from RAM inherit VNode;
|
||||
cap VNode_x86_64_ept_pdpt_Mapping from VNode_x86_64_ept_pdpt inherit Mapping;
|
||||
cap VNode_x86_64_ept_pdir from RAM inherit VNode;
|
||||
cap VNode_x86_64_ept_pdir_Mapping from VNode_x86_64_ept_pdir inherit Mapping;
|
||||
cap VNode_x86_64_ept_ptable from RAM inherit VNode;
|
||||
cap VNode_x86_64_ept_ptable_Mapping from VNode_x86_64_ept_ptable inherit Mapping;
|
||||
|
||||
/* Intel VT-d */
|
||||
|
||||
cap VNode_VTd_root_table from RAM inherit VNode;
|
||||
|
||||
cap VNode_VTd_root_table_Mapping from VNode_VTd_root_table inherit Mapping;
|
||||
|
||||
cap VNode_VTd_ctxt_table from RAM inherit VNode;
|
||||
|
||||
cap VNode_VTd_ctxt_table_Mapping from VNode_VTd_ctxt_table inherit Mapping;
|
||||
|
||||
/* cap IntelVTd from PhysAddr from_self inherit Memory; */
|
||||
|
||||
|
||||
/* x86_32-specific capabilities: */
|
||||
|
||||
/* PDPT */
|
||||
cap VNode_x86_32_pdpt from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_32_pdpt_Mapping from VNode_x86_32_pdpt inherit Mapping;
|
||||
|
||||
/* Page directory */
|
||||
cap VNode_x86_32_pdir from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_32_pdir_Mapping from VNode_x86_32_pdir inherit Mapping;
|
||||
|
||||
/* Page table */
|
||||
cap VNode_x86_32_ptable from RAM inherit VNode;
|
||||
|
||||
cap VNode_x86_32_ptable_Mapping from VNode_x86_32_ptable inherit Mapping;
|
||||
|
||||
/* ARM specific capabilities: */
|
||||
|
||||
/* L1 Page Table */
|
||||
cap VNode_ARM_l1 from RAM inherit VNode {
|
||||
size { objsize_vnode_arm_l1 };
|
||||
};
|
||||
|
||||
cap VNode_ARM_l1_Mapping from VNode_ARM_l1 inherit Mapping;
|
||||
|
||||
/* L2 Page Table */
|
||||
cap VNode_ARM_l2 from RAM inherit VNode {
|
||||
size { objsize_vnode_arm_l2 };
|
||||
};
|
||||
|
||||
cap VNode_ARM_l2_Mapping from VNode_ARM_l2 inherit Mapping;
|
||||
|
||||
/* ARM AArch64-specific capabilities: */
|
||||
|
||||
/* L0 Page Table */
|
||||
cap VNode_AARCH64_l0 from RAM inherit VNode;
|
||||
|
||||
cap VNode_AARCH64_l0_Mapping from VNode_AARCH64_l0 inherit Mapping;
|
||||
|
||||
/* L1 Page Table */
|
||||
cap VNode_AARCH64_l1 from RAM inherit VNode;
|
||||
|
||||
cap VNode_AARCH64_l1_Mapping from VNode_AARCH64_l1 inherit Mapping;
|
||||
|
||||
/* L2 Page Table */
|
||||
cap VNode_AARCH64_l2 from RAM inherit VNode;
|
||||
|
||||
cap VNode_AARCH64_l2_Mapping from VNode_AARCH64_l2 inherit Mapping;
|
||||
|
||||
/* L3 Page Table */
|
||||
cap VNode_AARCH64_l3 from RAM inherit VNode;
|
||||
|
||||
cap VNode_AARCH64_l3_Mapping from VNode_AARCH64_l3 inherit Mapping;
|
||||
|
||||
/** IRQTable and IO are slightly different **/
|
||||
|
||||
cap IRQTable is_always_copy {
|
||||
/* IRQ Routing table */
|
||||
/**
|
||||
When testing two IRQTable caps for is_copy, we always return True: all
|
||||
IRQ entries originate from a single, primitive Cap. Grand'pa Cap, sort
|
||||
of.
|
||||
**/
|
||||
};
|
||||
|
||||
cap IRQDest {
|
||||
/* IRQ Destination capability.
|
||||
Represents a slot in a CPUs int vector table.
|
||||
Can be connected to a LMP endpoint to recv this interrupt. */
|
||||
eq uint64 cpu;
|
||||
eq uint64 vector;
|
||||
};
|
||||
|
||||
cap IRQSrc from_self {
|
||||
/* IRQ Source capability.
|
||||
Represents an interrupt source. It contains a range of interrupt
|
||||
source numbers. */
|
||||
eq uint64 vec_start;
|
||||
eq uint64 vec_end;
|
||||
};
|
||||
|
||||
cap IO {
|
||||
/* Legacy IO capability */
|
||||
eq uint16 start;
|
||||
eq uint16 end; /* Granted IO range */
|
||||
};
|
||||
|
||||
/* IPI notify caps */
|
||||
cap Notify_IPI {
|
||||
eq coreid coreid;
|
||||
eq uint16 chanid;
|
||||
};
|
||||
|
||||
/* ID capability, system-wide unique */
|
||||
cap ID {
|
||||
eq coreid coreid; /* core cap was created */
|
||||
eq uint32 core_local_id; /* per core unique id */
|
||||
};
|
||||
|
||||
cap PerfMon is_always_copy {
|
||||
};
|
||||
|
||||
/** KernelControlBlock represents a struct kcb which contains all the pointers
|
||||
* to core-local global state of the kernel.
|
||||
**/
|
||||
cap KernelControlBlock from RAM {
|
||||
"struct kcb" kcb;
|
||||
|
||||
address { mem_to_phys(kcb) };
|
||||
/* base page size for now so we can map the kcb in boot driver */
|
||||
size { objsize_kcb };
|
||||
};
|
||||
|
||||
cap IPI is_always_copy {};
|
||||
|
||||
cap ProcessManager is_always_copy {
|
||||
// Capability to act as process manager, i.e. create new domain caps.
|
||||
};
|
||||
|
||||
cap Domain from ProcessManager {
|
||||
eq coreid coreid; /* Core where the domain was created. */
|
||||
eq uint32 core_local_id; /* Core-local ID of the domain. */
|
||||
};
|
||||
|
||||
/*
|
||||
cap ProtectionDomainManager is_always_copy {
|
||||
// Capability to act as device manager, i.e. create new device id caps
|
||||
};
|
||||
|
||||
cap ProtectionDomain from IOMMUDomainManager {
|
||||
uint16 id;
|
||||
uint16 type
|
||||
};
|
||||
*/
|
||||
|
||||
cap DeviceIDManager is_always_copy {
|
||||
// Capability to act as device manager, i.e. create new device id caps
|
||||
};
|
||||
|
||||
cap DeviceID from DeviceIDManager {
|
||||
uint16 segment;
|
||||
uint8 bus;
|
||||
uint8 device;
|
||||
uint8 function;
|
||||
uint8 type;
|
||||
uint16 flags;
|
||||
};
|
||||
80
default.nix
Normal file
80
default.nix
Normal file
@ -0,0 +1,80 @@
|
||||
{ stdenv, fetchgit, haskell, pythonPackages
|
||||
|
||||
, autoconf
|
||||
, automake
|
||||
, binutils
|
||||
, coreutils
|
||||
, cpio
|
||||
, curl
|
||||
, gcc5
|
||||
, gdb
|
||||
, git
|
||||
, gmp
|
||||
, gnugrep
|
||||
, gnused
|
||||
, m4
|
||||
, qemu
|
||||
|
||||
, ghc-version ? "ghc801"
|
||||
|
||||
, propagate-deps ? false
|
||||
, use-repo-source ? false
|
||||
, repo-url ? ""
|
||||
, repo-commit-id ? ""
|
||||
, repo-commit-sha256 ? ""
|
||||
}:
|
||||
|
||||
let src-repo = fetchgit {
|
||||
url = repo-url;
|
||||
rev = repo-commit-id;
|
||||
sha256 = repo-commit-sha256;
|
||||
};
|
||||
ghc = haskell.packages."${ghc-version}".ghcWithPackages
|
||||
(haskellPackages: with haskellPackages; [
|
||||
async
|
||||
bytestring-trie
|
||||
ghc-paths
|
||||
ghc-mtl
|
||||
haskell-src-exts
|
||||
parsec
|
||||
random
|
||||
]);
|
||||
deps = [
|
||||
autoconf
|
||||
automake
|
||||
binutils
|
||||
coreutils
|
||||
cpio
|
||||
curl
|
||||
gcc5
|
||||
gdb
|
||||
git
|
||||
gmp
|
||||
gnugrep
|
||||
gnused
|
||||
m4
|
||||
qemu
|
||||
|
||||
pythonPackages.pexpect
|
||||
|
||||
# custom GHC
|
||||
ghc
|
||||
];
|
||||
in
|
||||
stdenv.mkDerivation {
|
||||
version = "2016-11-09";
|
||||
name = "barrelfish";
|
||||
src = if use-repo-source
|
||||
then src-repo
|
||||
else builtins.filterSource
|
||||
(path: type: baseNameOf path != ".git" && baseNameOf path != "build")
|
||||
./.;
|
||||
|
||||
buildInputs = deps;
|
||||
propagatedBuildInputs = if propagate-deps
|
||||
then deps
|
||||
else [];
|
||||
|
||||
description = "The Barrelfish OS";
|
||||
license = "MIT";
|
||||
}
|
||||
161
devices/Hakefile
Normal file
161
devices/Hakefile
Normal file
@ -0,0 +1,161 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Copyright (c) 2007-2013, ETH Zurich.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This file is distributed under the terms in the attached LICENSE file.
|
||||
-- If you do not find this file, copies can be found by writing to:
|
||||
-- ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
--
|
||||
-- Hakefile for devices/
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
-- Mackerel 2 device descriptions
|
||||
--
|
||||
-- THIS is the place for new device descriptions.
|
||||
--
|
||||
[ mackerel2 (options arch) f
|
||||
| f <- [ "ac97_base_audio",
|
||||
"ac97_ext_audio",
|
||||
"armv8",
|
||||
"cpuid_intel",
|
||||
"cpuid_amd",
|
||||
"cpuid_arm",
|
||||
"ac97_ext_codec",
|
||||
"ac97_ext_modem",
|
||||
"ahci_hba",
|
||||
"ahci_port",
|
||||
"acpi_ec",
|
||||
"acpi_ec_mem",
|
||||
"arm",
|
||||
"ata_identify",
|
||||
"audio_nbm",
|
||||
"e1000",
|
||||
"e1000e",
|
||||
"e10k",
|
||||
"e10k_vf",
|
||||
"e10k_q",
|
||||
"ehci",
|
||||
"fat16_ebpb",
|
||||
"fat32_ebpb",
|
||||
"fat_bpb",
|
||||
"fat_direntry",
|
||||
"fat_long_direntry",
|
||||
"gic_v3_dist",
|
||||
"gic_v3_redist",
|
||||
"gic_v2_cpu",
|
||||
"hpet",
|
||||
"ia32",
|
||||
"ixp2800_icp_pic0",
|
||||
"ixp2800_icp_pit",
|
||||
"ixp2800_uart",
|
||||
"lpc_bridge",
|
||||
"lpc_dma",
|
||||
"lpc_kbd",
|
||||
"lpc_pic",
|
||||
"lpc_pci_config",
|
||||
"lpc_rtc",
|
||||
"lpc_rtc_spaces",
|
||||
"msix",
|
||||
"msix_e1000",
|
||||
"ohci",
|
||||
"pc16550d",
|
||||
"rtl8029as",
|
||||
"tulip",
|
||||
"uhci",
|
||||
"xapic",
|
||||
"x2apic",
|
||||
"amd64",
|
||||
"pl390_gic_dist",
|
||||
"pl390_gic_cpuif",
|
||||
"pl011_uart",
|
||||
"lpuart",
|
||||
"rpi3_miniuart",
|
||||
"sp804_pit",
|
||||
"cortex_a9_pit",
|
||||
"cortex_a9_gt",
|
||||
"cortex_a9_scu",
|
||||
"ti_i2c",
|
||||
"ti_twl6030",
|
||||
"sdhc",
|
||||
"apm88xxxx/apm88xxxx_pc16550",
|
||||
"armv8/armv8_cache_ctrl",
|
||||
"imx8x/imx8x_gpio",
|
||||
"imx8x/enet",
|
||||
"imx8x/sdhc",
|
||||
"omap/ehci",
|
||||
"omap/ohci",
|
||||
"omap/omap_uart",
|
||||
"omap/omap44xx_boot",
|
||||
"omap/omap44xx_cam_cm2",
|
||||
"omap/omap44xx_cam_prm",
|
||||
"omap/omap44xx_ckgen_cm1",
|
||||
"omap/omap44xx_ckgen_cm2",
|
||||
"omap/omap44xx_ckgen_prm",
|
||||
"omap/omap44xx_cortexa9_wugen",
|
||||
"omap/omap44xx_cortex_m3_nvic",
|
||||
"omap/omap44xx_ctrlmod",
|
||||
"omap/omap44xx_device_prm",
|
||||
"omap/omap44xx_ehci",
|
||||
"omap/omap44xx_emif",
|
||||
"omap/omap44xx_fdif",
|
||||
"omap/omap44xx_gpio",
|
||||
"omap/omap44xx_hsusbhost",
|
||||
"omap/omap44xx_id",
|
||||
"omap/omap44xx_l3init_cm2",
|
||||
"omap/omap44xx_l4per_cm2",
|
||||
"omap/omap44xx_mmchs",
|
||||
"omap/omap44xx_mmchs1",
|
||||
"omap/omap44xx_mmu",
|
||||
"omap/omap44xx_scrm",
|
||||
"omap/omap44xx_sdma",
|
||||
"omap/omap44xx_spinlock",
|
||||
"omap/omap44xx_sysctrl_padconf_core",
|
||||
"omap/omap44xx_sysctrl_padconf_wkup",
|
||||
"omap/omap44xx_usbconf",
|
||||
"omap/omap44xx_usbtllhs_config",
|
||||
"omap/omap44xx_uart3",
|
||||
"virtio/virtio_blk",
|
||||
"virtio/virtio_mmio",
|
||||
"virtio/virtio_pci",
|
||||
"virtio/virtio_io",
|
||||
"xeon_phi/xeon_phi_serial",
|
||||
"xeon_phi/xeon_phi_boot",
|
||||
"xeon_phi/xeon_phi_apic",
|
||||
"xeon_phi/xeon_phi_smpt",
|
||||
"xeon_phi/xeon_phi_irq",
|
||||
"xeon_phi/xeon_phi_dma",
|
||||
"xeon_phi/xeon_phi_dma_chan",
|
||||
"ioat_dma",
|
||||
"ioat_dma_chan",
|
||||
"pci_sr_iov_cap",
|
||||
"pci_msix_cap",
|
||||
"pci_e1000_msix_cap",
|
||||
"megaraid",
|
||||
"vtd",
|
||||
"zynq7/zynq_uart",
|
||||
"zynq7/zynq_slcr",
|
||||
"sfn5122f",
|
||||
"sfn5122f_q"
|
||||
], arch <- allArchitectures
|
||||
] ++
|
||||
|
||||
-- Mackerel 1 device descriptions
|
||||
--
|
||||
-- DO NOT add new devices to this list - the interface is non-portable
|
||||
-- and liable to break with new C compiler versions!
|
||||
--
|
||||
[ mackerel (options arch) f
|
||||
| f <- [ "amd_vmcb",
|
||||
"arm_icp_pic0",
|
||||
"arm_icp_pit",
|
||||
"cpuid",
|
||||
"ht_config",
|
||||
"lpc_ioapic",
|
||||
"lpc_timer",
|
||||
"pc16550d_mem",
|
||||
"pci_hdr0",
|
||||
"pci_hdr0_mem",
|
||||
"pci_hdr1"
|
||||
], arch <- allArchitectures
|
||||
]
|
||||
68
devices/a9scu.dev
Normal file
68
devices/a9scu.dev
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* a9scu.dev
|
||||
*
|
||||
* DESCRIPTION: Cortex A9 Snoop Control Unit
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* ARM Cortex-A9 MPCore Technical Reference Manual
|
||||
*
|
||||
*/
|
||||
|
||||
device a9scu msbfirst ( addr base ) "Cortex A9 SCU" {
|
||||
|
||||
register SCUControl addr(base, 0x0) "SCU Control" {
|
||||
_ 25 rsvd;
|
||||
IC_standby 1 rw "IC standby enable";
|
||||
SCU_standby 1 rw "SCU standby enable";
|
||||
all_device_to_port0 1 rw "Force all Device to port 0 enable";
|
||||
SCU_spec_linefill 1 rw "SCU speculative linefills enable";
|
||||
SCU_ram_parity 1 rw "SCU RAMs parity enable";
|
||||
address_filtering 1 rw "Address Filtering enable";
|
||||
SCU_enable 1 rw "SCU enable";
|
||||
};
|
||||
|
||||
register SCUConfig ro addr(base, 0x4) "SCU Configuration" {
|
||||
_ 16;
|
||||
tag_ram_sizes 8 ro "Tag RAM sizes";
|
||||
cpu_smp 4 ro "CPUs SMP bits";
|
||||
_ 2;
|
||||
cpu_number 2 ro "Number of CPUs present";
|
||||
};
|
||||
|
||||
constants cpu_status "CPU Status" {
|
||||
normal_mode = 0b00 "Normal mode";
|
||||
dormant_mode = 0b10 "Dormant mode";
|
||||
powered_off_mode = 0b11 "Powered-off mode";
|
||||
};
|
||||
|
||||
register SCUPowerStatus addr(base, 0x8) "SCU CPU Power Status" {
|
||||
_ 6;
|
||||
cpu3_status 2 rw "Status CPU3";
|
||||
_ 6;
|
||||
cpu2_status 2 rw "Status CPU2";
|
||||
_ 6;
|
||||
cpu1_status 2 rw "Status CPU1";
|
||||
_ 6;
|
||||
cpu0_status 2 rw "Status CPU0";
|
||||
};
|
||||
|
||||
register SCUFilteringStart addr(base, 0x40) "Filtering Start Address" {
|
||||
start_address 12 rw "Filtering Start address";
|
||||
_ 20;
|
||||
};
|
||||
|
||||
register SCUFilteringEnd addr(base, 0x44) "Filtering End Address" {
|
||||
end_address 12 rw "Filtering Start address";
|
||||
_ 20;
|
||||
};
|
||||
|
||||
};
|
||||
215
devices/ac97_base_audio.dev
Normal file
215
devices/ac97_base_audio.dev
Normal file
@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (c) 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ac97_base_audio.dev
|
||||
*
|
||||
* DESCRIPTION: AC'97 Baseline Audio Register Set
|
||||
*
|
||||
* Numbers in comments refer to the Intel Audio Codec '97 specification,
|
||||
* revision 2.3 revision 1.0, April, 2002
|
||||
*/
|
||||
|
||||
device ac97_base_audio msbfirst ( io base ) "AC97 Baseline Audio" {
|
||||
|
||||
// 5.7.1
|
||||
constants s3dsev "3D stereo enhancement vendor ID" {
|
||||
none = 0 "No 3D stereo enhancement";
|
||||
analogdev = 1 "Analog Devices";
|
||||
creative = 2 "Creative Technology";
|
||||
natsemi = 3 "National Semiconductor";
|
||||
yamaha = 4 "Yamaha";
|
||||
bbesound = 5 "BBE Sound";
|
||||
crystal = 6 "Crystal Semiconductor";
|
||||
qsound = 7 "Qsound Labs";
|
||||
spatial = 8 "Spatializer Audio Laboratories";
|
||||
srs = 9 "SRS Labs";
|
||||
platform = 10 "Platform Tech";
|
||||
akm = 11 "AKM Semiconductor";
|
||||
aureal = 12 "Aureal";
|
||||
aztech = 13 "Aztech Labs";
|
||||
binaura = 14 "Binaura";
|
||||
ess = 15 "ESS Technology";
|
||||
harman = 16 "Harman International";
|
||||
nvidia = 17 "Nvidia";
|
||||
philips = 18 "Philips";
|
||||
ti = 19 "Texas Instruments";
|
||||
vlsi = 20 "VLSI Technology";
|
||||
tritech = 21 "Tritech";
|
||||
realtek = 22 "Realtek";
|
||||
samsung = 23 "Samsung";
|
||||
wolfson = 24 "Wolfson Microelectronics";
|
||||
delta = 25 "Delta Integration";
|
||||
sigma = 26 "SigmaTel";
|
||||
kswav = 27 "KS Waves";
|
||||
rockwell = 28 "Rockwell";
|
||||
};
|
||||
|
||||
register reset rwc io( base, 0x00) "Reset" {
|
||||
_ 1 rsvd;
|
||||
se 5 ro type(s3dsev) "3D stereo enhancement vendor id";
|
||||
id9 1 ro "20-bit ADC resolution";
|
||||
id8 1 ro "18-bit ADC resolution";
|
||||
id7 1 ro "20-bit DAC resolution";
|
||||
id6 1 ro "18-bit DAC resolution";
|
||||
id5 1 ro "Loudness support";
|
||||
id4 1 ro "Headphone out support";
|
||||
id3 1 ro "Simulated stereo";
|
||||
id2 1 ro "Bass & treble control";
|
||||
id1 1 rsvd;
|
||||
id0 1 ro "Dedicated MIC PCM in";
|
||||
};
|
||||
|
||||
// 5.7.2
|
||||
regtype stereo_vol "Stereo volume" {
|
||||
mute 1 "Mute";
|
||||
_ 1 rsvd;
|
||||
ml 6 "Left volume";
|
||||
_ 2 rsvd;
|
||||
mr 6 "Right volume";
|
||||
};
|
||||
register master_vol io( base, 0x02 ) "Master volume" type(stereo_vol);
|
||||
register auxout_vol io( base, 0x04 ) "Aux out volume" type(stereo_vol);
|
||||
register mono_vol io( base, 0x06 ) "Mono volume" {
|
||||
mute 1 "Mute";
|
||||
_ 9 rsvd;
|
||||
mm 6 "Volume";
|
||||
};
|
||||
|
||||
// 5.7.3
|
||||
register master_tone io( base, 0x08 ) "Master tone control" {
|
||||
_ 4 rsvd;
|
||||
ba 4 "Bass";
|
||||
_ 4 rsvd;
|
||||
tr 4 "Treble";
|
||||
};
|
||||
|
||||
// 5.7.4
|
||||
register pcbeep io( base, 0x0a ) "PC beep" {
|
||||
mute 1 "Mute";
|
||||
_ 2 rsvd;
|
||||
freq 8 "Frequency";
|
||||
vol 4 "Volume";
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
// 5.7.5
|
||||
regtype analog_gain "Stereo analog mixer gain" {
|
||||
mute 1 "Mute";
|
||||
_ 2 rsvd;
|
||||
left 5 "Left gain";
|
||||
_ 3 rsvd;
|
||||
right 5 "Right gain";
|
||||
};
|
||||
register phone_vol io( base, 0x0c ) "Phone volume" {
|
||||
mute 1 "Mute";
|
||||
_ 10 rsvd;
|
||||
gain 5 "Gain";
|
||||
};
|
||||
register mic_vol io( base, 0x0e ) "Mic volume" {
|
||||
mute 1 "Mute";
|
||||
_ 8 rsvd;
|
||||
db20 1 "20 dB";
|
||||
_ 1 rsvd;
|
||||
gain 5 "Gain";
|
||||
};
|
||||
register linein_vol io( base, 0x10 ) "Line in volume" type(analog_gain);
|
||||
register cd_vol io( base, 0x12 ) "CD volume" type(analog_gain);
|
||||
register video_vol io( base, 0x14 ) "Video volume" type(analog_gain);
|
||||
register auxin_vol io( base, 0x16 ) "Aux in volume" type(analog_gain);
|
||||
register pcmout_vol io( base, 0x18 ) "PCM out volume" type(analog_gain);
|
||||
|
||||
// 5.7.6
|
||||
constants rec_src "Record source" {
|
||||
mic = 0 "Mic";
|
||||
cd = 1 "CD in";
|
||||
video = 2 "Video in";
|
||||
aux = 3 "Aux in";
|
||||
line = 4 "Line in";
|
||||
stereo = 5 "Stereo mix";
|
||||
mono = 6 "Mono mix";
|
||||
phone = 7 "Phone";
|
||||
};
|
||||
register rec_sec io( base, 0x1a ) "Record select" {
|
||||
_ 5 rsvd;
|
||||
left 3 type(rec_src) "Left source";
|
||||
_ 5 rsvd;
|
||||
right 3 type(rec_src) "Right source";
|
||||
};
|
||||
|
||||
// 5.7.7
|
||||
register rec_gain io( base, 0x1c ) "Record gain" {
|
||||
mute 1 "Mute";
|
||||
_ 3 rsvd;
|
||||
left 4 "Left gain";
|
||||
_ 4 rsvd;
|
||||
right 4 "Right gain";
|
||||
};
|
||||
register rec_gain_mic io( base, 0x1e ) "Record gain mic" {
|
||||
mute 1 "Mute";
|
||||
_ 11 rsvd;
|
||||
gain 4 "Gain";
|
||||
};
|
||||
|
||||
// 5.7.8
|
||||
register general io( base, 0x20 ) "General purpose" {
|
||||
pop 1 "PCM out path & mute";
|
||||
st 1 "Simulated stereo enhancement";
|
||||
s3d 1 "3D stereo enhancement";
|
||||
ld 1 "Loudness";
|
||||
drss 2 "Double rate slot select";
|
||||
mix 1 "Mono output select";
|
||||
ms 1 "Mic select";
|
||||
lpbk 1 "ADC/DAC loopback mode";
|
||||
_ 7 rsvd;
|
||||
};
|
||||
|
||||
// 5.7.9
|
||||
register s3d_ctrl io( base, 0x22 ) "3D control" {
|
||||
_ 4 rsvd;
|
||||
cr 4 "Center";
|
||||
_ 4 rsvd;
|
||||
dp 4 "Depth";
|
||||
};
|
||||
|
||||
// 5.7.10
|
||||
constants page_sel "Page selector" {
|
||||
vs = 0 "Vendor-specific";
|
||||
p1 = 1 "Paged ID 01";
|
||||
};
|
||||
|
||||
register aipm io( base, 0x24 ) "Audio interrupt and paging" {
|
||||
is 1 rw "Interrupt status";
|
||||
ics 1 ro "Sense status cause";
|
||||
icg 1 ro "GPIO status cause";
|
||||
isense 1 rw "Sense cycle start";
|
||||
ie 1 rw "Interrupt enable";
|
||||
_ 7 rsvd;
|
||||
pg 4 rw type(page_sel) "page selector";
|
||||
};
|
||||
|
||||
// 5.7.11
|
||||
register pcsr io( base, 0x26 ) "Powerdown control/status" {
|
||||
eapd 1 rw "External amp powerdown";
|
||||
pr6 1 rw "Aux out powerdown";
|
||||
pr5 1 rw "Internal clk disable";
|
||||
pr4 1 rw "Digital intf powerdown";
|
||||
pr3 1 rw "Analog mixer powerdown (vref off)";
|
||||
pr2 1 rw "Analog mixer powerdown (vref still on)";
|
||||
pr1 1 rw "PCM out DACs powerdown";
|
||||
pr0 1 rw "PCM in ADCs & input mux powerdown";
|
||||
_ 4 rsvd;
|
||||
ref 1 ro "Vref's up to nominal level";
|
||||
anl 1 ro "Analog mixers ready";
|
||||
dac 1 ro "DAC section ready to accept";
|
||||
adc 1 ro "ADC section ready to transmit";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
115
devices/ac97_ext_audio.dev
Normal file
115
devices/ac97_ext_audio.dev
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (c) 2007, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ac97_ext_audio.dev
|
||||
*
|
||||
* DESCRIPTION: AC'97 Extended Audio Register Set
|
||||
*
|
||||
* Numbers in comments refer to the Intel Audio Codec '97 specification,
|
||||
* revision 2.3 revision 1.0, April, 2002
|
||||
*/
|
||||
|
||||
device ac97_ext_audio msbfirst ( io base ) "AC97 Extended Audio" {
|
||||
|
||||
// 5.8.1
|
||||
constants rev_id "Revison ID" {
|
||||
r21 = 0 "Rev. 2.1 or earlier";
|
||||
r22 = 1 "Rev. 2.2";
|
||||
r23 = 2 "Rev. 2.3";
|
||||
unk = 3 "Unknown";
|
||||
};
|
||||
register eaid ro io( base, 0x28) "Extended audio id" {
|
||||
id 2 "Id";
|
||||
_ 2 rsvd;
|
||||
rev 2 type(rev_id) "Revision ID";
|
||||
amap 1 "Slot/DAC mapping support";
|
||||
ldac 1 "PCM LFE DAC support";
|
||||
sdac 1 "PCM Surround L&R DACs support";
|
||||
cdac 1 "PCM Center DAC support";
|
||||
dsa 2 rw "DAC slot assignment";
|
||||
vrm 1 "Variable rate mic support";
|
||||
spdif 1 "SPDIF transmitter support";
|
||||
dra 1 "Double-rate PCM audio support";
|
||||
vra 1 "Variable rate PCM audion support";
|
||||
};
|
||||
|
||||
// 5.8.2
|
||||
register easc rw io( base, 0x2a ) "Extended audio status and control" {
|
||||
vcfg 1 "S/PDIF validity flag";
|
||||
prl 1 "MIC ADC off";
|
||||
prk 1 "PCM LFE DACs off";
|
||||
prj 1 "PCM surround DACs off";
|
||||
pri 1 "PCM center DAC off";
|
||||
spcv 1 ro "S/PDIF configuration valid";
|
||||
madc 1 ro "Mic ADC ready";
|
||||
ldac 1 ro "PCM LFE DAC ready";
|
||||
sdac 1 ro "PCM Surround L&R DACs ready";
|
||||
cdac 1 ro "PCM Center DAC ready";
|
||||
dsa 2 "DAC slot assignment";
|
||||
vrm 1 "Variable rate mic enable";
|
||||
spdif 1 "SPDIF transmitter enable";
|
||||
dra 1 "Double-rate PCM audio enable";
|
||||
vra 1 "Variable rate PCM audion enable";
|
||||
};
|
||||
|
||||
// 5.8.3
|
||||
register front_sr rw io( base, 0x2c) "PCM front DAC rate" type(uint16);
|
||||
register surr_sr rw io( base, 0x2e) "PCM surround DAC rate" type(uint16);
|
||||
register lfe_sr rw io( base, 0x30) "PCM LFE DAC rate" type(uint16);
|
||||
register lr_sr rw io( base, 0x32) "PCM left/right DAC rate" type(uint16);
|
||||
register mic_sr rw io( base, 0x34) "MIC ADC rate" type(uint16);
|
||||
|
||||
// 5.8.4
|
||||
register center_vc rw io( base, 0x36) "Center/LFE volume" {
|
||||
lfe_mute 1 "LFE mute";
|
||||
_ 1 rsvd;
|
||||
lfe_vol 6 "LFE volume";
|
||||
cntr_mute 1 "Center mute";
|
||||
_ 1 rsvd;
|
||||
cntr_vol 6 "Center volume";
|
||||
};
|
||||
register surr_vc rw io( base, 0x38) "Surround volume" {
|
||||
left_mute 1 "Left mute";
|
||||
_ 1 rsvd;
|
||||
left_vol 6 "Left volume";
|
||||
right_mute 1 "Right mute";
|
||||
_ 1 rsvd;
|
||||
right_vol 6 "Right volume";
|
||||
};
|
||||
|
||||
// 5.8.5
|
||||
constants spdif_sr "S/PDIF sample rate" {
|
||||
sr_441 = 0 "44.1kHz";
|
||||
sr_rsvd = 0 "reserved";
|
||||
sr_48 = 0 "48kHz";
|
||||
sr_32 = 0 "32Hz";
|
||||
};
|
||||
register spdif_cntl rw io( base, 0x3a) "S/PDIF control" {
|
||||
v 1 "validity";
|
||||
drs 1 "Double rate";
|
||||
spsr 2 type(spdif_sr) "Sample rate";
|
||||
l 1 "General level";
|
||||
cc 7 "Category code";
|
||||
pre 1 "Preemphasis";
|
||||
copy 1 "Copyright";
|
||||
notaudio 1 "Non-PCM format";
|
||||
pro 1 "Professional";
|
||||
};
|
||||
|
||||
// 5.8.8
|
||||
register vid1 ro io( base, 0x7c) "Vendor ID 1" {
|
||||
f 8 "First PnP vendor ID code";
|
||||
s 8 "Second PnP vendor ID code";
|
||||
};
|
||||
register vid2 ro io( base, 0x7e) "Vendor ID 2" {
|
||||
t 8 "Third PnP vendor ID code";
|
||||
dev 8 "Vendor-specific device ID";
|
||||
};
|
||||
|
||||
};
|
||||
95
devices/ac97_ext_codec.dev
Normal file
95
devices/ac97_ext_codec.dev
Normal file
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ac97_ext_codec.dev
|
||||
*
|
||||
* DESCRIPTION: AC'97 Extended Codec Register Set
|
||||
*
|
||||
* Numbers in comments refer to the Intel Audio Codec '97 specification,
|
||||
* revision 2.3 revision 1.0, April, 2002
|
||||
*/
|
||||
|
||||
device ac97_ext_codec msbfirst ( io base ) "AC97 Extended Codec" {
|
||||
|
||||
// 5.9.1
|
||||
register classrev ro io( base, 0x60 ) "Codec class/rev" {
|
||||
rv 8 "Revision ID";
|
||||
cl 5 "Codec compatibility class";
|
||||
_ 3 rsvd;
|
||||
};
|
||||
register pcisvid ro io( base, 0x62 ) "PCI SVID" type(uint16);
|
||||
register pcisid ro io( base, 0x64 ) "PCI SID" type(uint16);
|
||||
|
||||
// 5.9.2
|
||||
constants fncode "Function code" {
|
||||
dac1 = 0 "DAC 1 (master out)";
|
||||
dac2 = 1 "DAC 2 (aux out)";
|
||||
dac3 = 2 "DAC 3 (C/LFE)";
|
||||
spdif = 3 "S/PDIF out";
|
||||
phone = 4 "Phone in";
|
||||
mic1 = 5 "Mic 1 (mic select=0)";
|
||||
mic2 = 6 "Mic 2 (mic select=1)";
|
||||
line = 7 "Line in";
|
||||
cd = 8 "CD in";
|
||||
video = 9 "Video in";
|
||||
aux = 10 "Aux in";
|
||||
mono = 11 "Mono out";
|
||||
};
|
||||
register fnsel io( base, 0x66 ) "Function select" {
|
||||
tr 1 "Tip or ring select";
|
||||
fc 4 type(fncode) "Function code";
|
||||
_ 11 rsvd;
|
||||
};
|
||||
register fninf io( base, 0x68 ) "Function information" {
|
||||
fip 1 "Function information present";
|
||||
_ 3 rsvd;
|
||||
iv 1 "Information valid";
|
||||
dl 5 "Buffer delays in 20.84us units";
|
||||
inv 1 "Inversion";
|
||||
g 5 "Gain or attenuation";
|
||||
};
|
||||
constants jackloc "Connector/jack location" {
|
||||
rear = 0 "Rear I/O panel";
|
||||
front = 1 "Front panel";
|
||||
mother = 2 "Motherboard";
|
||||
dock = 3 "Dock/External";
|
||||
none = 7 "No connection";
|
||||
};
|
||||
|
||||
register sensedet io( base, 0x6a ) "Sense details" {
|
||||
sr 6 ro "Sense result";
|
||||
or 2 rw "Sense result order bits";
|
||||
// XXX These have complicated meanings not specified here (yet)
|
||||
s 5 ro "Sensed bits";
|
||||
st 3 rw type(jackloc) "Connector/jack location";
|
||||
};
|
||||
|
||||
// 5.9.3
|
||||
constants slot "Slot mapping descriptor" {
|
||||
s0 = 0 "None/not implemented";
|
||||
s34 = 3 "Slot 3/4 (3 for mono)";
|
||||
s69 = 6 "Slot 6/9 (6 for mono)";
|
||||
s7 = 7 "Slot 7,8 (7 for mono)";
|
||||
sa = 10 "Slot 10/11 (10 for mono)";
|
||||
};
|
||||
register dacslot io ( base, 0x6c ) "DAC slot mapping" {
|
||||
_ 4;
|
||||
cld 4 type(slot) "DAC 3 (center/LFE)";
|
||||
sd 4 type(slot) "DAC 2 (surround)";
|
||||
fd 4 type(slot) "DAC 1 (front/headphone)";
|
||||
};
|
||||
register adcslot io ( base, 0x6e ) "ADC slot mapping" {
|
||||
mv 1 "Mapping valid";
|
||||
_ 7;
|
||||
ima 4 type(slot) "Independent mic";
|
||||
lia 4 type(slot) "Line in";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
107
devices/ac97_ext_modem.dev
Normal file
107
devices/ac97_ext_modem.dev
Normal file
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (c) 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ac97_ext_modem.dev
|
||||
*
|
||||
* DESCRIPTION: AC'97 Extended Modem Register Set
|
||||
*
|
||||
* Numbers in comments refer to the Intel Audio Codec '97 specification,
|
||||
* revision 2.3 revision 1.0, April, 2002
|
||||
*/
|
||||
|
||||
device ac97_ext_modem msbfirst ( io base ) "AC97 Extended Modem" {
|
||||
|
||||
// 6.6.1
|
||||
register emid rw io( base, 0x3c ) "Extended modem ID" {
|
||||
lin1 1 "Line 1 supported";
|
||||
lin2 1 "Line 2 supported";
|
||||
hset 1 "Handset DAC/ADC supported";
|
||||
cid1 1 "Caller ID decode on line 1 supported";
|
||||
cid2 1 "Caller ID decode on line 2 supported";
|
||||
_ 9;
|
||||
id 2 "Codec configuration";
|
||||
};
|
||||
|
||||
// 6.6.2
|
||||
register emsc io( base, 0x3e ) "Extended modem control/status" {
|
||||
gpio 1 ro "GPIO ready";
|
||||
mref 1 ro "Modem Vref nominal";
|
||||
adc1 1 ro "Line 1 ADC ready";
|
||||
dac1 1 ro "Line 1 DAC ready";
|
||||
adc2 1 ro "Line 2 ADC ready";
|
||||
dac2 1 ro "Line 2 DAC ready";
|
||||
hadc 1 ro "Handset ADC ready";
|
||||
hdac 1 ro "Handset DAC ready";
|
||||
pra 1 rw "GPIO power down";
|
||||
prb 1 rw "Modem Vref off";
|
||||
prc 1 rw "Line 1 ADC off";
|
||||
prd 1 rw "Line 1 DAC off";
|
||||
pre 1 rw "Line 2 ADC off";
|
||||
prf 1 rw "Line 2 DAC off";
|
||||
prg 1 rw "Handset ADC off";
|
||||
prf 1 rw "Handset DAC off";
|
||||
};
|
||||
|
||||
// 6.6.3
|
||||
register line1rate rw io( base, 0x40 ) "Line 1 sample rate" type(uint16);
|
||||
register line2rate rw io( base, 0x42 ) "Line 2 sample rate" type(uint16);
|
||||
register handsrate rw io( base, 0x44 ) "Handset sample rate" type(uint16);
|
||||
|
||||
// 6.6.4
|
||||
regtype lvlcntl "Modem DAC/ADC level control" {
|
||||
dmute 1 "DAC mute";
|
||||
_ 3;
|
||||
dac 4 "DAC level";
|
||||
amute 1 "ADC mute";
|
||||
_ 3;
|
||||
adc 4 "ADC level";
|
||||
};
|
||||
register line1lvl rw io (base, 0x46 ) "Line 1 level control" type(lvlcntl);
|
||||
register line2lvl rw io (base, 0x48 ) "Line 2 level control" type(lvlcntl);
|
||||
register handslvl rw io (base, 0x4a ) "Handset level control" type(lvlcntl);
|
||||
|
||||
// 6.6.5
|
||||
register gpioconf rw io(base, 0x4c) "GPIO pin configuration" type(uint16);
|
||||
|
||||
// 6.6.6
|
||||
register gpiopol rw io(base, 0x4e) "GPIO pin polarity/type" type(uint16);
|
||||
|
||||
// 6.6.7
|
||||
register gpiosticky rw io(base, 0x50) "GPIO pin sticky" type(uint16);
|
||||
|
||||
// 6.6.8
|
||||
register gpiowake rw io(base, 0x52) "GPIO pin wake-up mask" type(uint16);
|
||||
|
||||
// 6.6.9
|
||||
register gpiostat rw io(base, 0x54) "GPIO pin status" type(uint16);
|
||||
|
||||
// 6.6.10
|
||||
|
||||
constants lpbkmode "Loopback modes" {
|
||||
dis = 0b000 "Disabled";
|
||||
adc = 0b001 "ADC loopback";
|
||||
local = 0b010 "Local analog loopback";
|
||||
dac = 0b011 "DAC loopback";
|
||||
remote = 0b100 "Remote analog loopback";
|
||||
};
|
||||
|
||||
register misc rw io(base, 0x56) "Misc modem AFE status/control" {
|
||||
cid2 1 "Caller ID decode line 2 supported";
|
||||
cid1 1 "Caller ID decode line 1 supported";
|
||||
cidr 1 "Caller ID raw data";
|
||||
mlnk 1 "Secondary modem codec AC-link status";
|
||||
_ 1;
|
||||
hsb 3 type(lpbkmode) "Handset loopback mode";
|
||||
_ 1;
|
||||
l2b 3 type(lpbkmode) "Line 2 loopback mode";
|
||||
_ 1;
|
||||
l1b 3 type(lpbkmode) "Line 1 loopback mode";
|
||||
};
|
||||
};
|
||||
|
||||
54
devices/acpi_ec.dev
Normal file
54
devices/acpi_ec.dev
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* acpi_ec.dev
|
||||
*
|
||||
* DESCRIPTION: ACPI Embedded Controller (EC)
|
||||
*
|
||||
* This file describes the interface to the ACPI standard embedded controller.
|
||||
* See ACPI specification v4.0 section 12.2 (p445).
|
||||
*
|
||||
* The EC device consists of two 8-bit registers: status/command and data.
|
||||
*
|
||||
* FIXME: according to the ACPI spec (12.11) the controller may reside in
|
||||
* either IO or memory space. This driver assumes IO (because supporting
|
||||
* both in Mackerel would be quite clunky).
|
||||
*/
|
||||
|
||||
device acpi_ec msbfirst (io data, io sc) "ACPI embedded controller" {
|
||||
// 12.2.1
|
||||
regtype status "Status" {
|
||||
_ 1;
|
||||
smi_evt 1 "SMI event pending";
|
||||
sci_evt 1 "SCI event pending";
|
||||
burst 1 "Controller is in burst mode";
|
||||
cmd 1 "Byte in data register is a command byte";
|
||||
_ 1;
|
||||
ibf 1 "Input buffer is full";
|
||||
obf 1 "Output buffer is full";
|
||||
};
|
||||
|
||||
// 12.3
|
||||
constants commands width(8) "Command encodings" {
|
||||
read = 0x80 "Read";
|
||||
write = 0x81 "Write";
|
||||
burst_en = 0x82 "Burst enable";
|
||||
burst_dis = 0x83 "Burst disable";
|
||||
query = 0x84 "Query";
|
||||
};
|
||||
|
||||
// 12.2.1
|
||||
register status ro io(sc, 0) "Status" type(status);
|
||||
|
||||
// 12.2.2
|
||||
register cmd wo also io(sc, 0) "Command" type(commands);
|
||||
|
||||
// 12.2.3
|
||||
register data rw io(data, 0) "Data" type(uint8);
|
||||
};
|
||||
54
devices/acpi_ec_mem.dev
Normal file
54
devices/acpi_ec_mem.dev
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* acpi_ec.dev
|
||||
*
|
||||
* DESCRIPTION: ACPI Embedded Controller (EC)
|
||||
*
|
||||
* This file describes the interface to the ACPI standard embedded controller.
|
||||
* See ACPI specification v4.0 section 12.2 (p445).
|
||||
*
|
||||
* The EC device consists of two 8-bit registers: status/command and data.
|
||||
*
|
||||
* FIXME: according to the ACPI spec (12.11) the controller may reside in
|
||||
* either IO or memory space. This driver assumes IO (because supporting
|
||||
* both in Mackerel would be quite clunky).
|
||||
*/
|
||||
|
||||
device acpi_ec_mem msbfirst (addr data, addr sc) "ACPI embedded controller" {
|
||||
// 12.2.1
|
||||
regtype status "Status" {
|
||||
_ 1;
|
||||
smi_evt 1 "SMI event pending";
|
||||
sci_evt 1 "SCI event pending";
|
||||
burst 1 "Controller is in burst mode";
|
||||
cmd 1 "Byte in data register is a command byte";
|
||||
_ 1;
|
||||
ibf 1 "Input buffer is full";
|
||||
obf 1 "Output buffer is full";
|
||||
};
|
||||
|
||||
// 12.3
|
||||
constants commands width(8) "Command encodings" {
|
||||
read = 0x80 "Read";
|
||||
write = 0x81 "Write";
|
||||
burst_en = 0x82 "Burst enable";
|
||||
burst_dis = 0x83 "Burst disable";
|
||||
query = 0x84 "Query";
|
||||
};
|
||||
|
||||
// 12.2.1
|
||||
register status ro addr(sc, 0) "Status" type(status);
|
||||
|
||||
// 12.2.2
|
||||
register cmd wo also addr(sc, 0) "Command" type(commands);
|
||||
|
||||
// 12.2.3
|
||||
register data rw addr(data, 0) "Data" type(uint8);
|
||||
};
|
||||
136
devices/ahci_hba.dev
Normal file
136
devices/ahci_hba.dev
Normal file
@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ahci_hba.dev
|
||||
*
|
||||
* DESCRIPTION: AHCI (SATA) Host bus adaptor, generic registers (ports
|
||||
* have their own devive definition.
|
||||
*
|
||||
* Section numbers refer to the Serial ATA Advanced Host Controller
|
||||
* Interface (AHCI) specification 1.3, June 2008
|
||||
*/
|
||||
|
||||
device ahci_hba msbfirst (addr b) "AHCI generic" {
|
||||
|
||||
// 3.1.1
|
||||
|
||||
constants speed "Interface speed" {
|
||||
gen1 = 0b0001 "Gen 1 (1.5 Gbps)";
|
||||
gen2 = 0b0010 "Gen 2 (3 Gbps)";
|
||||
gen3 = 0b0011 "Gen 3 (6 Gbps)";
|
||||
};
|
||||
|
||||
register cap ro addr(b,0x00) "HBA capabilities" {
|
||||
s64a 1 "Supports 64-bit addressing";
|
||||
sncq 1 "Supports native command queueing";
|
||||
ssntf 1 "Supports SNotification register";
|
||||
smps 1 "Supports mechanical presence switch";
|
||||
sss 1 "Supports staggered spin-up";
|
||||
salp 1 "Supports aggressive link power management";
|
||||
sal 1 "Supports activity LED";
|
||||
sclo 1 "Supports command list override";
|
||||
iss 4 type(speed) "Interface speed support";
|
||||
_ 1 rsvd;
|
||||
sam 1 "Supports AHCI mode only";
|
||||
spm 1 "Supports port multiplier";
|
||||
fbss 1 "FIS-based switching supported";
|
||||
pmd 1 "PIO multiple DRQ block";
|
||||
ssc 1 "Slumber state capable";
|
||||
psc 1 "Partial state capable";
|
||||
ncs 5 "Number of command slots";
|
||||
cccs 1 "Command completion coalescing supported";
|
||||
ems 1 "Enclosure management supported";
|
||||
sxs 1 "Supports external SATA";
|
||||
np 5 "Number of ports";
|
||||
};
|
||||
|
||||
// 3.1.2
|
||||
register ghc rw addr(b,0x04) "Global HBA control" {
|
||||
ae 1 rw "AHCI enable";
|
||||
_ 28 rsvd;
|
||||
mrsm 1 ro "MSI revert to single message";
|
||||
ie 1 rw "Interrupt enable";
|
||||
hr 1 rw "HBA reset";
|
||||
};
|
||||
|
||||
// 3.1.3
|
||||
register is rwc addr(b,0x08) "Interrupt status" type(uint32);
|
||||
|
||||
// 3.1.4
|
||||
register pi ro addr(b,0x0c) "Ports implemented" type(uint32);
|
||||
|
||||
// 3.1.5
|
||||
register vs ro addr(b,0x10) "AHCI version" {
|
||||
major 16 "Major version";
|
||||
minor 16 "Minor version";
|
||||
};
|
||||
|
||||
// 3.1.6
|
||||
register ccc_ctl rw addr(b,0x14) "Command completion coalescing control" {
|
||||
tv 16 "Timeout value";
|
||||
cc 8 "Command completions";
|
||||
intr 5 ro "Interrupt";
|
||||
_ 2 rsvd;
|
||||
en 1 "Enable";
|
||||
};
|
||||
|
||||
// 3.1.7
|
||||
register ccc_ports rw addr(b,0x18) "Command completions coalescing ports"
|
||||
type(uint32);
|
||||
|
||||
// 3.1.8
|
||||
register em_loc ro addr(b,0x1c) "Enclosure management location" {
|
||||
ofst 16 "Offset";
|
||||
sz 16 "Bufer size";
|
||||
};
|
||||
|
||||
// 3.1.9
|
||||
register em_ctl addr(b,0x20) "Enclosure management control" {
|
||||
_ 4 rsvd;
|
||||
pm 1 ro "Port multiplier support";
|
||||
alhd 1 ro "Activity LED hardware driven";
|
||||
xmt 1 ro "Transmit only";
|
||||
smb 1 ro "Single message buffer";
|
||||
_ 4 rsvd;
|
||||
sgpio 1 ro "SGPIO enclosure management messages";
|
||||
ses2 1 ro "SES-2 enclosure management messages";
|
||||
safte 1 ro "SAF-TE enclosure management messages";
|
||||
led 1 ro "LED message types";
|
||||
_ 6 rsvd;
|
||||
rst 1 rw "Reset";
|
||||
tm 1 rw "Transmit message";
|
||||
_ 7 rsvd;
|
||||
mr 1 rw1c "Message received";
|
||||
};
|
||||
|
||||
// 3.1.10
|
||||
register cap2 ro addr(b,0x24) "HBA capabilities extended" {
|
||||
_ 29 rsvd;
|
||||
apst 1 "Automatic partial to slumber transitions";
|
||||
nvmp 1 "NVMHCI present";
|
||||
boh 1 "BIOS/OS handoff";
|
||||
};
|
||||
|
||||
// 3.1.11
|
||||
register bohc addr(b,0x28) "BIOS/OS handoff control and status" {
|
||||
_ 27 rsvd;
|
||||
bb 1 rw "BIOS busy";
|
||||
ooc 1 rw1c "OS ownership change";
|
||||
sooe 1 rw "SMI on OS ownership change enable";
|
||||
oos 1 rw "OS owned semaphore";
|
||||
bos 1 rw "BIOS owned semaphore";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
277
devices/ahci_port.dev
Normal file
277
devices/ahci_port.dev
Normal file
@ -0,0 +1,277 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ahci_port.dev
|
||||
*
|
||||
* DESCRIPTION: AHCI (SATA) Host bus adaptor, per-port registers
|
||||
*
|
||||
* Section numbers refer to the Serial ATA Advanced Host Controller
|
||||
* Interface (AHCI) specification 1.3, June 2008
|
||||
*/
|
||||
|
||||
device ahci_port msbfirst (addr b) "AHCI port" {
|
||||
|
||||
// 3.3.1-2
|
||||
// Low 10 bits mbz
|
||||
register clb rw addr(b,0x00) "Command list base address" type(uint64);
|
||||
|
||||
// 3.3.3-4
|
||||
// Low 10 bits mbz
|
||||
register fb rw addr(b,0x08) "FIS base address" type(uint64);
|
||||
|
||||
// 3.3.5
|
||||
register is addr(b,0x10) "Interrupt status" {
|
||||
cpds 1 rw1c "Cold port detect";
|
||||
tfes 1 rw1c "Task file error";
|
||||
hbfs 1 rw1c "Host bus fatal error";
|
||||
hbds 1 rw1c "Host bus data error";
|
||||
ifs 1 rw1c "Interface fatal error";
|
||||
infs 1 rw1c "Interface non-fatal error";
|
||||
_ 1 rsvd;
|
||||
ofs 1 rw1c "Overflow status";
|
||||
ipms 1 rw1c "Incorrect port multiplier status";
|
||||
prcs 1 ro "PhyRdy change status";
|
||||
_ 14 rsvd;
|
||||
dmps 1 rw1c "Device mechanical presence";
|
||||
pcs 1 ro "Port connect change";
|
||||
dps 1 rw1c "Descriptor processed";
|
||||
ufs 1 ro "Unknown FIS interrupt";
|
||||
sdbs 1 rw1c "Set device bits interrupt";
|
||||
dss 1 rw1c "DMA setup FIS interrupt";
|
||||
pss 1 rw1c "PIO setup FIS interrupt";
|
||||
dhrs 1 rw1c "Device to host register FIS interrupt";
|
||||
};
|
||||
|
||||
// 3.3.6
|
||||
register ie addr(b,0x14) "Interrupt enable" {
|
||||
cpde 1 rw "Cold port detect";
|
||||
tfee 1 rw "Task file error";
|
||||
hbfe 1 rw "Host bus fatal error";
|
||||
hbde 1 rw "Host bus data error";
|
||||
ife 1 rw "Interface fatal error";
|
||||
infe 1 rw "Interface non-fatal error";
|
||||
_ 1 rsvd;
|
||||
ofe 1 rw "Overflow enable";
|
||||
ipme 1 rw "Incorrect port multiplier status";
|
||||
prce 1 ro "PhyRdy change status";
|
||||
_ 14 rsvd;
|
||||
dmpe 1 rw "Device mechanical presence";
|
||||
pce 1 ro "Port connect change";
|
||||
dpe 1 rw "Descriptor processed";
|
||||
ufe 1 ro "Unknown FIS interrupt";
|
||||
sdbe 1 rw "Set device bits interrupt";
|
||||
dse 1 rw "DMA setup FIS interrupt";
|
||||
pse 1 rw "PIO setup FIS interrupt";
|
||||
dhre 1 rw "Device to host register FIS interrupt";
|
||||
};
|
||||
|
||||
// 3.3.7
|
||||
constants icct "Interface communication control" {
|
||||
slumber = 0x6 "Slumber";
|
||||
partial = 0x2 "Partial";
|
||||
active = 0x1 "Active";
|
||||
idle = 0x0 "No-Op / Idle";
|
||||
};
|
||||
register cmd addr(b,0x18) "Command and status" {
|
||||
icc 4 rw type(icct) "Interface communication control";
|
||||
asp 1 rw "Aggressive slumber / partial";
|
||||
alpe 1 rw "Aggressive link power management enable";
|
||||
dlae 1 rw "Drive LED on ATAPI enable";
|
||||
atapi 1 rw "Device is ATAPI";
|
||||
apste 1 rw "Automatic partial to slumber transitions enabled";
|
||||
fbscp 1 ro "FIS-based switching capable port";
|
||||
esp 1 ro "External SATA port";
|
||||
cpd 1 ro "Cold presence detection";
|
||||
mpsp 1 ro "Mechanical presence switch";
|
||||
hpcp 1 ro "Hot plug capable port";
|
||||
pma 1 rw "Port multiplier attached";
|
||||
cps 1 ro "Cold presence state";
|
||||
cr 1 ro "Command list running";
|
||||
fr 1 ro "FIS receive running";
|
||||
mpss 1 ro "Mechanical presence switch state";
|
||||
ccs 5 ro "Current command slot";
|
||||
_ 3 rsvd;
|
||||
fre 1 rw "FIS receive enable";
|
||||
clo 1 rw "Command list override";
|
||||
pod 1 rw "Power on device";
|
||||
sud 1 rw "Spin-up device";
|
||||
st 1 rw "Start";
|
||||
};
|
||||
|
||||
// 3.3.8
|
||||
register tfd ro addr(b,0x20) "Task file data" {
|
||||
_ 16 rsvd;
|
||||
err 8 "Error";
|
||||
bsy 1 ro "Indicates the interface is busy";
|
||||
cs2 3 ro "Command specific";
|
||||
drq 1 ro "Indicates a data transfer is requested";
|
||||
cs1 2 ro "Command specific";
|
||||
serr 1 ro "Indicates an error during the transfer.";
|
||||
};
|
||||
|
||||
// 3.3.9
|
||||
register sig ro addr(b,0x24) "Signature" {
|
||||
lbah 8 "LBA high";
|
||||
lbam 8 "LBA mid";
|
||||
lbal 8 "LBA low";
|
||||
sectors 8 "Sector count";
|
||||
};
|
||||
|
||||
// 3.3.10
|
||||
constants speed "Interface speed" {
|
||||
gen1 = 0b0001 "Gen 1 (1.5 Gbps)";
|
||||
gen2 = 0b0010 "Gen 2 (3 Gbps)";
|
||||
gen3 = 0b0011 "Gen 3 (6 Gbps)";
|
||||
};
|
||||
constants dets "Device detection state" {
|
||||
nodev = 0x0 "No device, no PHY";
|
||||
nophy = 0x1 "Device detected, no PHY comm. established";
|
||||
detect = 0x3 "Device detected and PHY comm. established";
|
||||
offline = 0x4 "PHY in offline mode or loopback";
|
||||
};
|
||||
register ssts ro addr(b,0x28) "Serial ATA status" {
|
||||
_ 20 rsvd;
|
||||
ipm 4 type(icct) "Interface power management";
|
||||
spd 4 type(speed) "Current interface speed";
|
||||
det 4 type(dets) "Device detection";
|
||||
};
|
||||
|
||||
// 3.3.11
|
||||
constants ipmall "Interface transitions" {
|
||||
noipm = 0x0 "No interface restrictions";
|
||||
noprtl = 0x1 "Transitions to Partial state disabled";
|
||||
noslmb = 0x2 "Transitions to Slumber state disabled";
|
||||
noboth = 0x3 "Transitions to both Partial and Slumber disabled";
|
||||
};
|
||||
register sctl addr(b,0x2c) "Serial ATA control" {
|
||||
_ 12 rsvd;
|
||||
_ 4 rsvd "Port multiplier port (unused)";
|
||||
_ 4 rsvd "Select power mgmt (unused)";
|
||||
ipm 4 rw type(ipmall) "Interface power mgmt transitions allowed";
|
||||
spd 4 rw type(speed) "Speed allowed";
|
||||
det 4 rw type(dets) "Device detection initialization";
|
||||
};
|
||||
|
||||
// 3.3.12
|
||||
register serr rw1c addr(b,0x30) "Serial ATA error" {
|
||||
_ 5 rsvd;
|
||||
dx 1 "Exchanged";
|
||||
df 1 "Unknown FIS type";
|
||||
dt 1 "Transport state transition error";
|
||||
ds 1 "Link sequence error";
|
||||
dh 1 "Handshake error";
|
||||
dc 1 "CRC error";
|
||||
dd 1 "Disparity error";
|
||||
db 1 "10b to 8b decode error";
|
||||
dw 1 "Comm wake";
|
||||
di 1 "Phy internal error";
|
||||
dn 1 "PhyRdy change";
|
||||
_ 4 rsvd;
|
||||
ee 1 "Internal error";
|
||||
ep 1 "Protocol error";
|
||||
ec 1 "Persistent communication or data integrity error";
|
||||
et 1 "Transient data integrity error";
|
||||
_ 6 rsvd;
|
||||
em 1 "Recovered communications error";
|
||||
ei 1 "Recovered data integrity error";
|
||||
};
|
||||
|
||||
// 3.3.13
|
||||
register sact rw addr(b,0x34) "Serial ATA active" type(uint32);
|
||||
|
||||
// 3.3.14
|
||||
register ci rw addr(b,0x38) "Command issue" type(uint32);
|
||||
|
||||
// 3.3.15
|
||||
register sntf addr(b,0x3c) "Serial ATA notification" {
|
||||
_ 16 mbz;
|
||||
pmn 16 rw1c "PMN notify";
|
||||
};
|
||||
|
||||
// 3.3.16
|
||||
register fbs addr(b,0x40) "FIS-based switching control" {
|
||||
_ 12 mbz;
|
||||
dwe 4 ro "Device with error";
|
||||
ado 4 ro "Active device optimization";
|
||||
dev 4 rw "Device to issue";
|
||||
_ 5 mbz;
|
||||
sde 1 ro "Single device error";
|
||||
dec 1 rw1c "Device error clear";
|
||||
en 1 rw "Enable";
|
||||
};
|
||||
|
||||
// 4.2.2 Command List Structure, elements are Command Headers
|
||||
datatype chdr msbfirst(32) "Command Header" {
|
||||
prdtl 16 "Physical region descriptor table length";
|
||||
pmp 4 "Port multiplier port";
|
||||
_ 1;
|
||||
c 1 "Clear busy upon R_OK";
|
||||
b 1 "BIST";
|
||||
r 1 "Reset";
|
||||
p 1 "Prefetchable";
|
||||
w 1 "Write";
|
||||
a 1 "ATAPI";
|
||||
cfl 5 "Command FIS length";
|
||||
|
||||
prdbc 32 "Physical region descriptor byte count";
|
||||
|
||||
ctba 64 "Command table descriptor base address";
|
||||
|
||||
_ 32;
|
||||
_ 32;
|
||||
_ 32;
|
||||
_ 32;
|
||||
};
|
||||
|
||||
// 4.2.3.3 Physical Region Descriptor Table
|
||||
datatype prd msbfirst(32) "Physical region descriptor" {
|
||||
dba 32 "Data base address";
|
||||
dbau 32 "Data base address upper";
|
||||
_ 32;
|
||||
i 1 "Interrupt on completion";
|
||||
_ 9;
|
||||
dbc 22 "Data byte count";
|
||||
};
|
||||
|
||||
// 12.2
|
||||
constants emtype "Enclosure message type" {
|
||||
led = 0x0 "LED";
|
||||
saf_te = 0x1 "SAF-TE";
|
||||
ses_2 = 0x2 "SES-2";
|
||||
sgpio = 0x3 "SGPOI (register-based interface";
|
||||
};
|
||||
datatype encmsg "Enclosure management message" {
|
||||
_ 4;
|
||||
mtype 4 type(emtype) "Message type";
|
||||
dsize 8 "Data size";
|
||||
msize 8 "Message size";
|
||||
_ 8;
|
||||
};
|
||||
|
||||
// 12.2.1
|
||||
constants emledstate "Enclosure LED state" {
|
||||
off = 0b000 "LED shall be off";
|
||||
solid = 0b001 "LED shall be solid on";
|
||||
vs1 = 0b100 "Vendor specific 1";
|
||||
vs2 = 0b101 "Vendor specific 2";
|
||||
vs3 = 0b110 "Vendor specific 3";
|
||||
vs4 = 0b111 "Vendor specific 4";
|
||||
};
|
||||
datatype emledmsg "Enclosure LED message" {
|
||||
_ 7;
|
||||
fault 3 type(emledstate) "Vendor-specific LED (e.g. fault)";
|
||||
locate 3 type(emledstate) "Vendor-specific LED (e.g. locate)";
|
||||
activity 3 type(emledstate) "Activity LED";
|
||||
_ 4;
|
||||
pmi 4 "Port multiplier information";
|
||||
_ 2;
|
||||
vsm 1 "Vendor-specific enclosure message";
|
||||
hbapn 5 "HBA port number for update";
|
||||
};
|
||||
};
|
||||
113
devices/amd64.dev
Normal file
113
devices/amd64.dev
Normal file
@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, 2011 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* amd64.dev
|
||||
*
|
||||
* DESCRIPTION: amd64 and Intel64 architecture definitions.
|
||||
*
|
||||
* This is derived from the "Intel 64 and IA-32 Architectures Software
|
||||
* Developer's Manual", volumes 3A and 3B, "System Programming Guide,
|
||||
* Parts 1 and 2"
|
||||
*/
|
||||
|
||||
device amd64 msbfirst ( ) "Intel64 and AMD 64-bit architecture definitions" {
|
||||
|
||||
//
|
||||
// Section 2.5: Control registers
|
||||
//
|
||||
register cr0 noaddr "Control register 0" {
|
||||
pg 1 "Paging";
|
||||
cd 1 "Cache disable";
|
||||
nw 1 "Not write-through";
|
||||
_ 10;
|
||||
am 1 "Alignment mask";
|
||||
_ 1;
|
||||
wp 1 "Write protect";
|
||||
_ 10;
|
||||
ne 1 "Numeric error";
|
||||
et 1 "Extension type";
|
||||
ts 1 "Task switched";
|
||||
em 1 "Emulation";
|
||||
mp 1 "Monitor coprocessor";
|
||||
pe 1 "Protection enable";
|
||||
};
|
||||
|
||||
// Control register 1 is reserved.
|
||||
|
||||
register cr2 noaddr "Page-fault linear address" type(uint64);
|
||||
|
||||
register cr3 noaddr "Control register 3 (PDBR)" {
|
||||
pdb 52 "Page-directory base";
|
||||
_ 7;
|
||||
pcd 1 "Page-level cache disable";
|
||||
pwt 1 "Page-level writes transparent";
|
||||
_ 3;
|
||||
};
|
||||
|
||||
register cr4 noaddr "Control register 4" {
|
||||
_ 49 mbz;
|
||||
smxe 1 "SMX enable";
|
||||
vmxe 1 "VMX enable";
|
||||
_ 2 mbz;
|
||||
osxmmexcpt 1 "OS support for unmasked SIMD FP exceptions";
|
||||
osfxsr 1 "OS support for FXSAVE and FXRSTOR instructions";
|
||||
pce 1 "Performance-monitoring counter enable";
|
||||
pge 1 "Page global enable";
|
||||
mce 1 "Machine-check enable";
|
||||
pae 1 "Physical address extensions";
|
||||
pse 1 "Page size extensions";
|
||||
de 1 "Debugging extensions";
|
||||
tsd 1 "Time stamp disable";
|
||||
pvi 1 "Protected-mode virtual interrupts";
|
||||
vme 1 "Virtual 8086 mode extensions";
|
||||
};
|
||||
|
||||
regtype cr8 "Control register 8" {
|
||||
_ 60;
|
||||
tpl 4 "Task priority level";
|
||||
};
|
||||
|
||||
//
|
||||
// Section 3.10: PAE-Enabled Paging in IA-32e Mode
|
||||
//
|
||||
|
||||
regtype pdir_entry "Page-Directory Entry" {
|
||||
exb 1 "Execute-Disable";
|
||||
avail 11 "Available";
|
||||
_ 12 mbz;
|
||||
base 28 "Base address";
|
||||
avail2 3 "Available";
|
||||
_ 2 mbz;
|
||||
avail3 1 "Available";
|
||||
accessed 1 "Accessed";
|
||||
pcd 1 "Cache disabled";
|
||||
pwt 1 "Write-through";
|
||||
us 1 "User/Supervisor";
|
||||
rw 1 "Read/Write";
|
||||
present 1 "Present";
|
||||
};
|
||||
|
||||
regtype ptable_entry "Page-Table Entry" {
|
||||
exb 1 "Execute-Disable";
|
||||
avail 11 "Available";
|
||||
_ 12 mbz;
|
||||
base 28 "Base address";
|
||||
avail2 3 "Available";
|
||||
global 1 "Global";
|
||||
pat 1 "Page-Attribute index";
|
||||
dirty 1 "Dirty";
|
||||
accessed 1 "Accessed";
|
||||
pcd 1 "Cache disabled";
|
||||
pwt 1 "Write-through";
|
||||
us 1 "User/Supervisor";
|
||||
rw 1 "Read/Write";
|
||||
present 1 "Present";
|
||||
};
|
||||
|
||||
};
|
||||
378
devices/amd_vmcb.dev
Normal file
378
devices/amd_vmcb.dev
Normal file
@ -0,0 +1,378 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
device amd_vmcb lsbfirst ( addr base ) "AMD Virtual Machine Control Block"
|
||||
{
|
||||
register cr_access addr(base, 0x000) "Intercept reads/writes to CR0-15" {
|
||||
rdcr0 1 "Intercept reads of CR0";
|
||||
rdcr1 1 "Intercept reads of CR1";
|
||||
rdcr2 1 "Intercept reads of CR2";
|
||||
rdcr3 1 "Intercept reads of CR3";
|
||||
rdcr4 1 "Intercept reads of CR4";
|
||||
rdcr5 1 "Intercept reads of CR5";
|
||||
rdcr6 1 "Intercept reads of CR6";
|
||||
rdcr7 1 "Intercept reads of CR7";
|
||||
rdcr8 1 "Intercept reads of CR8";
|
||||
rdcr9 1 "Intercept reads of CR9";
|
||||
rdcr10 1 "Intercept reads of CR10";
|
||||
rdcr11 1 "Intercept reads of CR11";
|
||||
rdcr12 1 "Intercept reads of CR12";
|
||||
rdcr13 1 "Intercept reads of CR13";
|
||||
rdcr14 1 "Intercept reads of CR14";
|
||||
rdcr15 1 "Intercept reads of CR15";
|
||||
wrcr0 1 "Intercept writes of CR0";
|
||||
wrcr1 1 "Intercept writes of CR1";
|
||||
wrcr2 1 "Intercept writes of CR2";
|
||||
wrcr3 1 "Intercept writes of CR3";
|
||||
wrcr4 1 "Intercept writes of CR4";
|
||||
wrcr5 1 "Intercept writes of CR5";
|
||||
wrcr6 1 "Intercept writes of CR6";
|
||||
wrcr7 1 "Intercept writes of CR7";
|
||||
wrcr8 1 "Intercept writes of CR8";
|
||||
wrcr9 1 "Intercept writes of CR9";
|
||||
wrcr10 1 "Intercept writes of CR10";
|
||||
wrcr11 1 "Intercept writes of CR11";
|
||||
wrcr12 1 "Intercept writes of CR12";
|
||||
wrcr13 1 "Intercept writes of CR13";
|
||||
wrcr14 1 "Intercept writes of CR14";
|
||||
wrcr15 1 "Intercept writes of CR15";
|
||||
};
|
||||
|
||||
register dr_access addr(base, 0x004) "Intercept reads/writes to DR0-15" {
|
||||
rddr0 1 "Intercept reads of DR0";
|
||||
rddr1 1 "Intercept reads of DR1";
|
||||
rddr2 1 "Intercept reads of DR2";
|
||||
rddr3 1 "Intercept reads of DR3";
|
||||
rddr4 1 "Intercept reads of DR4";
|
||||
rddr5 1 "Intercept reads of DR5";
|
||||
rddr6 1 "Intercept reads of DR6";
|
||||
rddr7 1 "Intercept reads of DR7";
|
||||
rddr8 1 "Intercept reads of DR8";
|
||||
rddr9 1 "Intercept reads of DR9";
|
||||
rddr10 1 "Intercept reads of DR10";
|
||||
rddr11 1 "Intercept reads of DR11";
|
||||
rddr12 1 "Intercept reads of DR12";
|
||||
rddr13 1 "Intercept reads of DR13";
|
||||
rddr14 1 "Intercept reads of DR14";
|
||||
rddr15 1 "Intercept reads of DR15";
|
||||
wrdr0 1 "Intercept writes of DR0";
|
||||
wrdr1 1 "Intercept writes of DR1";
|
||||
wrdr2 1 "Intercept writes of DR2";
|
||||
wrdr3 1 "Intercept writes of DR3";
|
||||
wrdr4 1 "Intercept writes of DR4";
|
||||
wrdr5 1 "Intercept writes of DR5";
|
||||
wrdr6 1 "Intercept writes of DR6";
|
||||
wrdr7 1 "Intercept writes of DR7";
|
||||
wrdr8 1 "Intercept writes of DR8";
|
||||
wrdr9 1 "Intercept writes of DR9";
|
||||
wrdr10 1 "Intercept writes of DR10";
|
||||
wrdr11 1 "Intercept writes of DR11";
|
||||
wrdr12 1 "Intercept writes of DR12";
|
||||
wrdr13 1 "Intercept writes of DR13";
|
||||
wrdr14 1 "Intercept writes of DR14";
|
||||
wrdr15 1 "Intercept writes of DR15";
|
||||
};
|
||||
|
||||
register exceptions addr(base, 0x008) "Intercept exception vectors 0-31" {
|
||||
vector0 1 "Intercept exception vector 0";
|
||||
vector1 1 "Intercept exception vector 1";
|
||||
vector2 1 "Intercept exception vector 2";
|
||||
vector3 1 "Intercept exception vector 3";
|
||||
vector4 1 "Intercept exception vector 4";
|
||||
vector5 1 "Intercept exception vector 5";
|
||||
vector6 1 "Intercept exception vector 6";
|
||||
vector7 1 "Intercept exception vector 7";
|
||||
vector8 1 "Intercept exception vector 8";
|
||||
vector9 1 "Intercept exception vector 9";
|
||||
vector10 1 "Intercept exception vector 10";
|
||||
vector11 1 "Intercept exception vector 11";
|
||||
vector12 1 "Intercept exception vector 12";
|
||||
vector13 1 "Intercept exception vector 13";
|
||||
vector14 1 "Intercept exception vector 14";
|
||||
vector15 1 "Intercept exception vector 15";
|
||||
vector16 1 "Intercept exception vector 16";
|
||||
vector17 1 "Intercept exception vector 17";
|
||||
vector18 1 "Intercept exception vector 18";
|
||||
vector19 1 "Intercept exception vector 19";
|
||||
vector20 1 "Intercept exception vector 20";
|
||||
vector21 1 "Intercept exception vector 21";
|
||||
vector22 1 "Intercept exception vector 22";
|
||||
vector23 1 "Intercept exception vector 23";
|
||||
vector24 1 "Intercept exception vector 24";
|
||||
vector25 1 "Intercept exception vector 25";
|
||||
vector26 1 "Intercept exception vector 26";
|
||||
vector27 1 "Intercept exception vector 27";
|
||||
vector28 1 "Intercept exception vector 28";
|
||||
vector29 1 "Intercept exception vector 29";
|
||||
vector30 1 "Intercept exception vector 30";
|
||||
vector31 1 "Intercept exception vector 31";
|
||||
};
|
||||
|
||||
register intercepts addr(base, 0x00c) "Various intercepts" {
|
||||
intr 1 "Intercept INTR instruction";
|
||||
nmi 1 "Intercept NMI instruction";
|
||||
smi 1 "Intercept SMI instruction";
|
||||
init 1 "Intercept INIT instruction";
|
||||
vintr 1 "Intercept VINTR instruction";
|
||||
wrcr0 1 "Intercept CR0 writes that change bits other than TS or MP";
|
||||
rdidtr 1 "Intercept reads of IDTR";
|
||||
rdgdtr 1 "Intercept reads of GDTR";
|
||||
rdldtr 1 "Intercept reads of LDTR";
|
||||
rdtr 1 "Intercept reads of TR";
|
||||
wridtr 1 "Intercept writes of IDRT";
|
||||
wrgdtr 1 "Intercept writes of GDTR";
|
||||
wrldtr 1 "Intercept writes of LDTR";
|
||||
wrtr 1 "Intercept writes of TR";
|
||||
rdtsc 1 "Intercept RDTSC instruction";
|
||||
rdpmc 1 "Intercept RDPMC instruction";
|
||||
pushf 1 "Intercept PUSHF instruction";
|
||||
popf 1 "Intercept POPF instruction";
|
||||
cpuid 1 "Intercept CPUID instruction";
|
||||
rsm 1 "Intercept RSM instruction";
|
||||
iret 1 "Intercept IRET instruction";
|
||||
intn 1 "Intercept INTn instruction";
|
||||
invd 1 "Intercept INVD instruction";
|
||||
pause 1 "Intercept PAUSE instruction";
|
||||
hlt 1 "Intercept HLT instruction";
|
||||
invlpg 1 "Intercept INVLPG instruction";
|
||||
invlpga 1 "Intercept INVLPGA instruction";
|
||||
ioio_prot 1 "Intercept IN/OUT accesses to selected ports";
|
||||
msr_prot 1 "Intercept RDMSR or WRMSR accesses to selected MSRs";
|
||||
task_switch 1 "Intercept task switches";
|
||||
ferr_freeze 1 "Intercept processor freezing durich legacy FERR handling";
|
||||
shutdown 1 "Intercept shutdown events";
|
||||
vmrun 1 "Intercept VMRUN instruction";
|
||||
vmmcall 1 "Intercept VMMCALL instruction";
|
||||
vmload 1 "Intercept VMLOAD instruction";
|
||||
vmsave 1 "Intercept VMSAVE instruction";
|
||||
stgi 1 "Intercept STGI instruction";
|
||||
clgi 1 "Intercept CLGI instruction";
|
||||
skinit 1 "Intercept SKINIT instruction";
|
||||
rdtscp 1 "Intercept RDTSCP instruction";
|
||||
icebp 1 "Intercept ICEBP instruction";
|
||||
wbinvd 1 "Intercept WBINVD instruction";
|
||||
monitor 1 "Intercept MONITOR instruction";
|
||||
mwait0 1 "Intercept MWAIT instruction unconditionally";
|
||||
mwait1 1 "Intercept MWAIT instruction if monitor hardware is armed";
|
||||
_ 19 rsvd;
|
||||
};
|
||||
|
||||
register iopm_base_pa addr(base, 0x040) "Physical base address of IOPM (bits 11:0 are ignored)" type(uint64);
|
||||
|
||||
register msrpm_base_pa addr(base, 0x048) "Physical base address of MSRPM (bits 11:0 are ignored)" type(uint64);
|
||||
|
||||
register tsc_offset addr(base, 0x050) "To be added in RDTSC and RDTSCP" type(uint64);
|
||||
|
||||
register tlb addr(base, 0x058) "Guest TLB settings" {
|
||||
guest_asid 32 "Guest ASID";
|
||||
control 8 "TLB control values";
|
||||
_ 24 rsvd;
|
||||
};
|
||||
|
||||
register vintr addr(base, 0x060) "Virtual interrupt settings" {
|
||||
vtpr 8 "Virtual TPR for the guest";
|
||||
virq 1 "Virtual interrupt pernding";
|
||||
_ 7 "Reserved, SBZ";
|
||||
vintr_prio 4 "Priority for virtual interrupt";
|
||||
v_ign_tpr 1 "Virtual interrupt ignores the virtual TPR";
|
||||
_ 3 "Reserved, SBZ";
|
||||
vintr_masking 1 "Virtualize masking of INTR interrupt";
|
||||
_ 7 "Reserved, SBZ";
|
||||
vintr_vector 8 "Vector to use for this interrupt";
|
||||
_ 24 rsvd;
|
||||
};
|
||||
|
||||
register intr addr(base, 0x068) "Guest interrupt settings" {
|
||||
interrupt_shadow 1 "Guest is in an interrupt shadow";
|
||||
_ 63 rsvd;
|
||||
};
|
||||
|
||||
register exitcode addr(base, 0x070) "Guest EXITCODE" type(uint64);
|
||||
|
||||
register exitinfo1 addr(base, 0x078) "Guest EXITINFO1" type(uint64);
|
||||
|
||||
register exitinfo2 addr(base, 0x080) "Guest EXITINFO2" type(uint64);
|
||||
|
||||
register exitintinfo addr(base, 0x088) "Guest EXITINTINFO" type(uint64);
|
||||
|
||||
register np addr(base, 0x090) "Nested paging settings" {
|
||||
enable 1 "Enable nested paging";
|
||||
_ 63 rsvd;
|
||||
};
|
||||
|
||||
register eventinj addr(base, 0x0a8) "Event injection" type(uint64);
|
||||
|
||||
register ncr3 addr(base, 0x0b0) "Nested page table CR3 to use for nested paging" type(uint64);
|
||||
|
||||
register lbr addr(base, 0x0b8) "Guest LBR settings" {
|
||||
lbr_virtualization_enable 1 "Enable LBR virtualization";
|
||||
_ 63 rsvd;
|
||||
};
|
||||
|
||||
/* Guest State */
|
||||
|
||||
regtype seg_attrib "Segment attributes" {
|
||||
segtype 4 "Segment type";
|
||||
s 1 "Segment descriptor type";
|
||||
dpl 2 "Descriptor privilege level";
|
||||
p 1 "Segment present";
|
||||
avl 1 "Available for use by system software";
|
||||
l 1 "64-bit code segment";
|
||||
db 1 "Default operation size (0: 16-bit, 1: 32-bit segment)";
|
||||
g 1 "Granularity";
|
||||
_ 4 rsvd;
|
||||
};
|
||||
|
||||
register es_selector addr(base, 0x400) "Guest ES selector" type(uint16);
|
||||
register es_attrib addr(base, 0x402) "Guest ES attrib" type(seg_attrib);
|
||||
register es_limit addr(base, 0x404) "Guest ES limit" type(uint32);
|
||||
register es_base addr(base, 0x408) "Guest ES base" type(uint64);
|
||||
|
||||
register cs_selector addr(base, 0x410) "Guest CS selector" type(uint16);
|
||||
register cs_attrib addr(base, 0x412) "Guest CS attrib" type(seg_attrib);
|
||||
register cs_limit addr(base, 0x414) "Guest CS limit" type(uint32);
|
||||
register cs_base addr(base, 0x418) "Guest CS base" type(uint64);
|
||||
|
||||
register ss_selector addr(base, 0x420) "Guest SS selector" type(uint16);
|
||||
register ss_attrib addr(base, 0x422) "Guest SS attrib" type(seg_attrib);
|
||||
register ss_limit addr(base, 0x424) "Guest SS limit" type(uint32);
|
||||
register ss_base addr(base, 0x428) "Guest SS base" type(uint64);
|
||||
|
||||
register ds_selector addr(base, 0x430) "Guest DS selector" type(uint16);
|
||||
register ds_attrib addr(base, 0x432) "Guest DS attrib" type(seg_attrib);
|
||||
register ds_limit addr(base, 0x434) "Guest DS limit" type(uint32);
|
||||
register ds_base addr(base, 0x438) "Guest DS base" type(uint64);
|
||||
|
||||
register fs_selector addr(base, 0x440) "Guest FS selector" type(uint16);
|
||||
register fs_attrib addr(base, 0x442) "Guest FS attrib" type(seg_attrib);
|
||||
register fs_limit addr(base, 0x444) "Guest FS limit" type(uint32);
|
||||
register fs_base addr(base, 0x448) "Guest FS base" type(uint64);
|
||||
|
||||
register gs_selector addr(base, 0x450) "Guest GS selector" type(uint16);
|
||||
register gs_attrib addr(base, 0x452) "Guest GS attrib" type(seg_attrib);
|
||||
register gs_limit addr(base, 0x454) "Guest GS limit" type(uint32);
|
||||
register gs_base addr(base, 0x458) "Guest GS base" type(uint64);
|
||||
|
||||
register gdtr_selector addr(base, 0x460) "Guest GTDR selector" type(uint16);
|
||||
register gdtr_attrib addr(base, 0x462) "Guest GTDR attrib" type(seg_attrib);
|
||||
register gdtr_limit addr(base, 0x464) "Guest GTDR limit" type(uint32);
|
||||
register gdtr_base addr(base, 0x468) "Guest GTDR base" type(uint64);
|
||||
|
||||
register ldtr_selector addr(base, 0x470) "Guest LTDR selector" type(uint16);
|
||||
register ldtr_attrib addr(base, 0x472) "Guest LTDR attrib" type(seg_attrib);
|
||||
register ldtr_limit addr(base, 0x474) "Guest LTDR limit" type(uint32);
|
||||
register ldtr_base addr(base, 0x478) "Guest LTDR base" type(uint64);
|
||||
|
||||
register idtr_selector addr(base, 0x480) "Guest ITDR selector" type(uint16);
|
||||
register idtr_attrib addr(base, 0x482) "Guest ITDR attrib" type(seg_attrib);
|
||||
register idtr_limit addr(base, 0x484) "Guest ITDR limit" type(uint32);
|
||||
register idtr_base addr(base, 0x488) "Guest ITDR base" type(uint64);
|
||||
|
||||
register tr_selector addr(base, 0x490) "Guest TR selector" type(uint16);
|
||||
register tr_attrib addr(base, 0x492) "Guest TR attrib" type(seg_attrib);
|
||||
register tr_limit addr(base, 0x494) "Guest TR limit" type(uint32);
|
||||
register tr_base addr(base, 0x498) "Guest TR base" type(uint64);
|
||||
|
||||
register cpl addr(base, 0x4cb) "Guest current protection level" type(uint8);
|
||||
|
||||
register efer addr(base, 0x4d0) "Guest EFER" {
|
||||
sce 1 "System Call Extensions";
|
||||
_ 7 mbz;
|
||||
lme 1 "Long Mode Enable";
|
||||
_ 1 mbz;
|
||||
lma 1 "Long Mode Active";
|
||||
nxe 1 "No-Execute Enable";
|
||||
svme 1 "Secure Virtual Machine Enable";
|
||||
_ 1 mbz;
|
||||
ffxsr 1 "Fast FXSAVE/FXRSTOR";
|
||||
_ 49 mbz;
|
||||
};
|
||||
|
||||
register cr4 addr(base, 0x548) "Guest CR4" {
|
||||
vme 1 "Virtual-8086 Mode Extensions";
|
||||
pvi 1 "Protected-Mode Virtual Interrupts";
|
||||
tsd 1 "Time Stamp Disable";
|
||||
de 1 "Debugging Extensions";
|
||||
pse 1 "Page Size Extensions";
|
||||
pae 1 "Physical-Address Extension";
|
||||
mce 1 "Machine Check Enable";
|
||||
pge 1 "Page-Global Enable";
|
||||
pce 1 "Performance-Monitoring Counter Enable";
|
||||
osfxsr 1 "Operating System FXSAVE/FXRSTOR Support";
|
||||
osxmmecept 1 "Operating System Unmasked Exception Support";
|
||||
_ 53 mbz;
|
||||
};
|
||||
|
||||
register cr3 addr(base, 0x550) "Guest CR3" type(uint64);
|
||||
|
||||
register cr0 addr(base, 0x558) "Guest CR0" {
|
||||
pe 1 "Protection Enabled";
|
||||
mp 1 "Monitor Coprocessor";
|
||||
em 1 "Emulation";
|
||||
ts 1 "Task Switched";
|
||||
et 1 ro "Extension Type";
|
||||
ne 1 "Numeric Error";
|
||||
_ 10 rsvd;
|
||||
wp 1 "Write Protect";
|
||||
_ 1 rsvd;
|
||||
am 1 "Alignment Mask";
|
||||
_ 10 rsvd;
|
||||
nw 1 "Not Writethrough";
|
||||
cd 1 "Cache Disable";
|
||||
pg 1 "Paging";
|
||||
_ 32 mbz;
|
||||
};
|
||||
|
||||
register dr7 addr(base, 0x560) "Guest DR7" type(uint64);
|
||||
register dr6 addr(base, 0x568) "Guest DR6" type(uint64);
|
||||
|
||||
register rflags addr(base, 0x570) "Guest RFLAGS" {
|
||||
cf 1 "Carry Flag";
|
||||
_ 1 rsvd;
|
||||
pf 1 "Parity Flag";
|
||||
_ 1 rsvd;
|
||||
af 1 "Auxiliary Flag";
|
||||
_ 1 rsvd;
|
||||
zf 1 "Zero Flag";
|
||||
sf 1 "Sign Flag";
|
||||
tf 1 "Trap Flag";
|
||||
intrf 1 "Interrupt Flag";
|
||||
df 1 "Direction Flag";
|
||||
of 1 "Overflow Flag";
|
||||
iopl 2 "I/O Privilege Level";
|
||||
nt 1 "Nested Task";
|
||||
_ 1 rsvd;
|
||||
rf 1 "Resume Flag";
|
||||
vm 1 "Virtual-8086 Mode";
|
||||
ac 1 "Alignment Check";
|
||||
vif 1 "Virtual Interrupt Flag";
|
||||
vip 1 "Virtual Interrupt Pending";
|
||||
id 1 "ID Flag";
|
||||
_ 42 rsvd;
|
||||
};
|
||||
|
||||
register rip addr(base, 0x578) "Guest RIP" type(uint64);
|
||||
register rsp addr(base, 0x5d8) "Guest RSP" type(uint64);
|
||||
register rax addr(base, 0x5F8) "Guest RAX" type(uint64);
|
||||
register star addr(base, 0x600) "Guest STAR" type(uint64);
|
||||
register lstar addr(base, 0x608) "Guest LSTAR" type(uint64);
|
||||
register cstar addr(base, 0x610) "Guest CSTAR" type(uint64);
|
||||
register sfmask addr(base, 0x618) "Guest SFMASK" type(uint64);
|
||||
register kernel_gs_base addr(base, 0x620) "Guest KernelGsBase" type(uint64);
|
||||
register sysenter_cs addr(base, 0x628) "Guest SYSENTER_CS" type(uint64);
|
||||
register sysenter_esp addr(base, 0x630) "Guest SYSENTER_ESP" type(uint64);
|
||||
register sysenter_eip addr(base, 0x638) "Guest SYSENTER_EIP" type(uint64);
|
||||
register cr2 addr(base, 0x640) "Guest CR2" type(uint64);
|
||||
register gpat addr(base, 0x668) "Guest PAT" type(uint64);
|
||||
register dbgctl addr(base, 0x670) "Guest DBGCTL MSR" type(uint64);
|
||||
register br_from addr(base, 0x678) "Guest LastBranchFromIP MSR" type(uint64);
|
||||
register br_to addr(base, 0x680) "Guest LastBranchToIP MSR" type(uint64);
|
||||
register lastexcpfrom addr(base, 0x688) "Guest LastExceptionFromIP MSR" type(uint64);
|
||||
register lastexcpto addr(base, 0x690) "Guest LastExceptionToIP MSR" type(uint64);
|
||||
};
|
||||
68
devices/apm88xxxx/apm88xxxx_pc16550.dev
Normal file
68
devices/apm88xxxx/apm88xxxx_pc16550.dev
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2015, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* apm88xxxx/apm88xxxx_pc16550.dev
|
||||
*
|
||||
* DESCRIPTION: APM88xxxx PC16550 UART
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* APM88xx0x Processor Family Register Reference -- Volume 1
|
||||
* Document Issue 0.98 (APM 2012-0052-1)
|
||||
*
|
||||
* This file only incorporates the parts relevant for UART operation.
|
||||
* Registers relevant for IrDA, CIR, and other modes are not yet
|
||||
* described.
|
||||
*/
|
||||
device apm88xxxx_pc16550 msbfirst (addr base) "APM88xxxx UART" {
|
||||
|
||||
constants data_len "Data Length" {
|
||||
bits5 = 0b00 "5 Bits";
|
||||
bits6 = 0b01 "6 Bits";
|
||||
bits7 = 0b10 "7 Bits";
|
||||
bits8 = 0b11 "8 Bits";
|
||||
};
|
||||
|
||||
register RBR ro addr (base, 0x0) "Receive Buffer" {
|
||||
_ 24;
|
||||
rbr 8 ro "Receive buffer register";
|
||||
};
|
||||
|
||||
register THR wo also addr (base, 0x0) "Transmit Register" {
|
||||
_ 24;
|
||||
thr 8 wo "Transmit register";
|
||||
};
|
||||
|
||||
register IIR ro addr (base, 0x8) "Interrupt Identity" type(uint32);
|
||||
|
||||
register lcr rw addr (base, 0xc) "Line control" {
|
||||
_ 24;
|
||||
dlab 1 "Divisor latch access bit";
|
||||
bc 1 "Break control bit";
|
||||
sp 1 rsvd "Stick parity";
|
||||
eps 1 "Even parity select";
|
||||
pen 1 "Parity enable";
|
||||
stop 1 "stop bit";
|
||||
dls 2 type(data_len) "Data length select";
|
||||
};
|
||||
|
||||
register LSR ro addr (base, 0x14) "Line Status" {
|
||||
_ 24;
|
||||
rfe 1 "Receive FIFO error";
|
||||
temt 1 "Transmitter empty";
|
||||
thre 1 "Transmit holding register empty";
|
||||
bi 1 "Break interrupt";
|
||||
fe 1 "Framing error";
|
||||
pe 1 "Parity error";
|
||||
oe 1 "Overrun error";
|
||||
dr 1 "Data ready";
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
137
devices/arm.dev
Normal file
137
devices/arm.dev
Normal file
@ -0,0 +1,137 @@
|
||||
/*
|
||||
* Copyright (c) 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* arm.dev
|
||||
*
|
||||
* DESCRIPTION: ARM architecture definitions
|
||||
*
|
||||
* See:
|
||||
* ARM Architecture Reference Manual
|
||||
*/
|
||||
|
||||
device arm msbfirst () "ARM architecture" {
|
||||
|
||||
// A.2.5
|
||||
regtype status "Status register" {
|
||||
n 1 "Negative result";
|
||||
z 1 "Zero result";
|
||||
c 1 "Carry";
|
||||
v 1 "Overflow";
|
||||
q 1 "DSP overflow";
|
||||
_ 19;
|
||||
i 1 "IRQ disable";
|
||||
f 1 "FIQ disable";
|
||||
t 1 "Thumb mode";
|
||||
m 5 type(cpu_mode) "Mode";
|
||||
};
|
||||
constants cpu_mode "CPU mode bits" {
|
||||
user = 0b10000 "User";
|
||||
fiq = 0b10001 "FIQ";
|
||||
irq = 0b10010 "IRQ";
|
||||
super = 0b10011 "Supervisor";
|
||||
abort = 0b10111 "Abort";
|
||||
undef = 0b11011 "Undefined";
|
||||
system = 0b11111 "System";
|
||||
};
|
||||
|
||||
// A.2.6
|
||||
constants exc_vector "Exception vector addresses" {
|
||||
vec_reset = 0x00000000 "Reset";
|
||||
vec_undef = 0x00000004 "Undefined instruction";
|
||||
vec_swi = 0x00000008 "Software interrupt";
|
||||
vec_pref_abort = 0x0000000C "Prefetch abort";
|
||||
vec_data_abort = 0x00000010 "Data abort";
|
||||
vec_irq = 0x00000018 "Interrupt";
|
||||
vec_fiq = 0x0000001C "Fast interrupt";
|
||||
};
|
||||
|
||||
space cp15(reg, opcode) valuewise "Coprocessor 15";
|
||||
|
||||
// B.2.4
|
||||
register control rw cp15(0x01) "CP15 control register" {
|
||||
_ 16 mbz;
|
||||
l4 1 "Backwards compatible loads";
|
||||
rr 1 "Predictable cache replacement strategy";
|
||||
v 1 "High exception vectors enable";
|
||||
i 1 "Instruction cache enable";
|
||||
z 1 "Branch prediction enable";
|
||||
f 1 "Implementation defined";
|
||||
r 1 "ROM protection bit";
|
||||
s 1 "System protection bit";
|
||||
b 1 "Big endian";
|
||||
l 1 "Late abort model";
|
||||
d 1 "26-bit address exception checking";
|
||||
p 1 "26/32-bit exception handler mode";
|
||||
w 1 "Write buffer enable";
|
||||
c 1 "Data or unified cache enable";
|
||||
a 1 "Alignment fault checking enable";
|
||||
m 1 "MMU enable";
|
||||
};
|
||||
|
||||
//
|
||||
// Memory Management Unit functions
|
||||
//
|
||||
|
||||
// B.3.6.1
|
||||
constants fault_type "Faulting access type" {
|
||||
terminal = 0b0010 "Terminal exception";
|
||||
vector = 0b0000 "Vector exception";
|
||||
alignment = 0b0001 "Alignment";
|
||||
alignment_2 = 0b0011 "Alternate alignment";
|
||||
l1extabort = 0b1100 "Level 1 external abort on translation";
|
||||
l2extabort = 0b1110 "Level 2 external abort on translation";
|
||||
sec_trans = 0b0101 "Section translation";
|
||||
page_trans = 0b0111 "Page transation";
|
||||
sec_dom = 0b1001 "Section domain";
|
||||
page_dom = 0b1011 "Page domain";
|
||||
sec_perm = 0b1101 "Section permissions";
|
||||
page_perm = 0b1111 "Page permissions";
|
||||
sec_linef = 0b0100 "Section external abort on linefetch";
|
||||
page_linef = 0b0110 "Page external abort on linefetch";
|
||||
sec_nlinef = 0b1000 "Section external abort on non-linefetch";
|
||||
page_nlinef = 0b1010 "Page external abort on non-linefetch";
|
||||
};
|
||||
|
||||
|
||||
// B.3.7.2
|
||||
register ttbase rw cp15(0x02) "Translation table base" {
|
||||
base 18 "Base address high bits";
|
||||
_ 14 mbz;
|
||||
};
|
||||
|
||||
// B.3.7.3
|
||||
register domacc rw cp15(0x03) "Domain access control" type(uint32);
|
||||
|
||||
// B.3.7.5
|
||||
register faultstat rw cp15(0x05) "Fault status" {
|
||||
_ 23 mbz;
|
||||
_ 1 mbz;
|
||||
domain 4 "Faulting domain";
|
||||
status 4 type(fault_type) "Access type";
|
||||
};
|
||||
|
||||
// 3.7.6
|
||||
register faultaddr rw cp15(6) "Fault address" type(uint32);
|
||||
|
||||
// 3.7.7 XXX opcode2, and CRm dependent
|
||||
register tlbfunc wo cp15(8) "TLB functions" type(uint32);
|
||||
|
||||
// 3.7.8 XXX opcode2, and CRm dependent
|
||||
register tlblock rw cp15(10) "TLB lockdown" {
|
||||
entry 31 "Base and victim (variable width)";
|
||||
p 1 "Protected from CP8 invalidates";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
75
devices/arm_icp_pic0.dev
Normal file
75
devices/arm_icp_pic0.dev
Normal file
@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* arm_icp_pic0.dev
|
||||
*
|
||||
* DESCRIPTION: Primary interrupt controller for integrator/cp
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* Integrator/CP User Guide
|
||||
* (DUI0159B_integratorcp_1_0_ug.pdf)
|
||||
*
|
||||
*/
|
||||
|
||||
device arm_icp_pic0 msbfirst ( addr base ) "ARM Integrator Primary PIC"
|
||||
{
|
||||
regtype source "Interrupt controller sources" {
|
||||
_ 3;
|
||||
TS_PENINT 1 "Touchscreen pen-down event interrupt";
|
||||
ETH_INT 1 "Ethernet interface interrupt";
|
||||
CPPLDINT 1 "Interrupt from secondary interrupt controller";
|
||||
AACIINT 1 "Audio interface interrupt";
|
||||
MMCIINT1 1 "MultiMedia card interface 1";
|
||||
MMCIINT0 1 "MultiMedia card interface 0";
|
||||
CLCDCINT 1 "Display controller interrupt";
|
||||
_ 11;
|
||||
LM_LLINT1 1 "Logic module low-latency interrupt 1";
|
||||
LM_LLINT0 1 "Logic module low-latency interrupt 0";
|
||||
RTCINT 1 "Real time clock interrupt";
|
||||
TIMERINT2 1 "Counter-timer 2 interrupt";
|
||||
TIMERINT1 1 "Counter-timer 1 interrupt";
|
||||
TIMERINT0 1 "Counter-timer 0 interrupt";
|
||||
MOUSEINT 1 "Mouse interrupt";
|
||||
KBDINT 1 "Keyboard interrupt";
|
||||
UARTINT1 1 "UART 1 interrupt";
|
||||
UARTINT0 1 "UART 0 interrupt";
|
||||
SOFTINT 1 "Software interrupt";
|
||||
};
|
||||
|
||||
register PIC_IRQ_STATUS ro addr (base, 0x00) "IRQ gated interrupt status"
|
||||
type(source);
|
||||
|
||||
register PIC_IRQ_RAWSTAT ro addr (base, 0x04) "IRQ raw interrupt status"
|
||||
type(source);
|
||||
|
||||
register PIC_IRQ_ENABLESET rw addr (base, 0x08) "IRQ enable set"
|
||||
type(source);
|
||||
|
||||
register PIC_IRQ_ENABLECLR wo addr (base, 0x0c) "IRQ enable clear"
|
||||
type(source);
|
||||
|
||||
register PIC_INT_SOFTSET rw addr (base, 0x10) "Software interrupt set"
|
||||
type(source);
|
||||
|
||||
register PIC_INT_SOFTCLR wo addr (base, 0x14) "Software interrupt clear"
|
||||
type(source);
|
||||
|
||||
register PIC_FIQ_STATUS ro addr (base, 0x20) "FIQ gated interrupt status"
|
||||
type(source);
|
||||
|
||||
register PIC_FIQ_RAWSTAT ro addr (base, 0x24) "FIQ raw interrupt status"
|
||||
type(source);
|
||||
|
||||
register PIC_FIQ_ENABLESET rw addr (base, 0x28) "FIQ enable set"
|
||||
type(source);
|
||||
|
||||
register PIC_FIQ_ENABLECLR wo addr (base, 0x2c) "FIQ enable clear"
|
||||
type(source);
|
||||
};
|
||||
71
devices/arm_icp_pit.dev
Normal file
71
devices/arm_icp_pit.dev
Normal file
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* arm_icp_pit.dev
|
||||
*
|
||||
* DESCRIPTION: Timers for for integrator/cp
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* Integrator/CP User Guide
|
||||
* (DUI0159B_integratorcp_1_0_ug.pdf)
|
||||
*
|
||||
*/
|
||||
|
||||
device arm_icp_pit msbfirst ( addr base ) "ARM Integrator timer"
|
||||
{
|
||||
constants scale "Timer scaling factors" {
|
||||
none = 0b00 "none";
|
||||
div16 = 0b01 "divide by 16";
|
||||
div256 = 0b10 "divide by 256";
|
||||
};
|
||||
|
||||
constants mode "Timer Mode" {
|
||||
free = 0b0 "Counts once and then wraps to 0xffff";
|
||||
reload = 0b1 "Reloads from load register at end of each count";
|
||||
};
|
||||
|
||||
register LOAD addr(base, 0x00) "Load value for timer" {
|
||||
value 32 rw;
|
||||
};
|
||||
|
||||
register CURRENT addr(base, 0x04) "Current value for timer" {
|
||||
value 32 ro;
|
||||
};
|
||||
|
||||
register CONTROL addr(base, 0x08) "Control register" {
|
||||
_ 24;
|
||||
enable 1 rw;
|
||||
mode 1 rw type(mode);
|
||||
int_enable 1 rw;
|
||||
_ 1;
|
||||
prescale 2 rw type(scale);
|
||||
timer32 1 rw "Timer 32-bit (otherwise 16-bit)";
|
||||
oneshot 1 rw "Stop rather than wrap.";
|
||||
};
|
||||
|
||||
register INTCLR addr(base, 0x0c) "Interrupt clear" {
|
||||
value 32 wo;
|
||||
};
|
||||
|
||||
register RIS addr(base, 0x10) "Raw interrupt status" {
|
||||
_ 31;
|
||||
status 1 ro "Raw status";
|
||||
};
|
||||
|
||||
register MIS addr(base, 0x14) "Masked interrupt status" {
|
||||
_ 31;
|
||||
status 1 ro "Masked status";
|
||||
};
|
||||
|
||||
register BGLOAD addr(base, 0x18) "Background load value for timer" {
|
||||
value 32 rw "Reload value for periodic timer, does not affect CURRENT";
|
||||
};
|
||||
};
|
||||
|
||||
2392
devices/armv8.dev
Normal file
2392
devices/armv8.dev
Normal file
File diff suppressed because it is too large
Load Diff
62
devices/armv8/armv8_cache_ctrl.dev
Normal file
62
devices/armv8/armv8_cache_ctrl.dev
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2016, 2017 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* armv8.dev
|
||||
*
|
||||
* DESCRIPTION: ARMv8 architecture definitions
|
||||
*
|
||||
* See:
|
||||
* ARM Architecture Reference Manual
|
||||
*/
|
||||
|
||||
device armv8_cache_ctrl msbfirst () "ARMv8 Cache Control registers" {
|
||||
|
||||
space cache_ctrl(name) registerwise "Cache control register";
|
||||
|
||||
register DC_CSIW wo cache_ctrl(cisw) "Data or unified Cache line Clean and Invalidate by Set/Way" {
|
||||
_ 32 mbz;
|
||||
SetWay 28 "Set and ways. depends on the cache settings";
|
||||
Level 3 "Cache level to operate on, minus 1.";
|
||||
_ 1 mbz;
|
||||
};
|
||||
|
||||
register DC_CIVAC wo cache_ctrl(civac) "Data or unified Cache line Clean and Invalidate by VA to PoC" {
|
||||
addr 64 "Virtual address to use.";
|
||||
};
|
||||
|
||||
register DC_CSW wo cache_ctrl(csw) "Data or unified Cache line Clean by Set/Way" {
|
||||
_ 32 mbz;
|
||||
SetWay 28 "Set and ways. depends on the cache settings";
|
||||
Level 3 "Cache level to operate on, minus 1.";
|
||||
_ 1 mbz;
|
||||
};
|
||||
|
||||
register DC_CVAC wo cache_ctrl(cvac) "Data or unified Cache line Clean by VA to PoC" {
|
||||
addr 64 "Virtual address to use.";
|
||||
};
|
||||
|
||||
register DC_CVAU wo cache_ctrl(cvau) "Data or unified Cache line Clean by VA to PoU" {
|
||||
addr 64 "Virtual address to use.";
|
||||
};
|
||||
|
||||
register DC_ISW wo cache_ctrl(isw) "Data or unified Cache line Invalidate by Set/Way" {
|
||||
_ 32 mbz;
|
||||
SetWay 28 "Set and ways. depends on the cache settings";
|
||||
Level 3 "Cache level to operate on, minus 1.";
|
||||
_ 1 mbz;
|
||||
};
|
||||
|
||||
register DC_IVAC wo cache_ctrl(ivac) "Data or unified Cache line Invalidate by VA to PoC" {
|
||||
addr 64 "Virtual address to use.";
|
||||
};
|
||||
|
||||
register DC_ZVA wo cache_ctrl(zva) "Data or unified Cache line Invalidate by VA to PoC" {
|
||||
addr 64 "Virtual address to use.";
|
||||
};
|
||||
};
|
||||
177
devices/ata_identify.dev
Normal file
177
devices/ata_identify.dev
Normal file
@ -0,0 +1,177 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ata_identify.dev
|
||||
*
|
||||
* DESCRIPTION: ATA IDENTIFY command's result.
|
||||
*
|
||||
*/
|
||||
|
||||
device ata_identify msbfirst (addr b) "ATA IDENTIFY results" {
|
||||
|
||||
register gcbsi ro addr(b, 0x00) "General configuration bit-significant information" {
|
||||
ad 1 "0 = ATA device";
|
||||
_ 7 "Retired";
|
||||
_ 2 "Obsolete";
|
||||
_ 3 "Retired";
|
||||
ri 1 "Response incomplete";
|
||||
_ 1 "Retired";
|
||||
_ 1 "Reserved";
|
||||
};
|
||||
//register word1 ro addr(b, 0x02) "Obsolete" type(uint16);
|
||||
register sc ro addr(b, 0x04) "Specific configuration" type(uint16);
|
||||
//register word3 ro addr(b, 0x06) "Obsolete" type(uint16);
|
||||
//register word4 ro addr(b, 0x08) "Retired" type(uint16);
|
||||
//register word5 ro addr(b, 0x0A) "Retired" type(uint16);
|
||||
//register word6 ro addr(b, 0x0C) "Obsolete" type(uint16);
|
||||
register cfrsvd0 ro addr(b, 0x0E) "Reserved for assignment by the CompactFlash(TM) Association" type(uint16);
|
||||
register cfrsvd1 ro addr(b, 0x10) "Reserved for assignment by the CompactFlash(TM) Association" type(uint16);
|
||||
//register word9 ro addr(b, 0x12) "Retired" type(uint16);
|
||||
regarray sn ro addr(b, 0x14) [20] "Serial number" type(uint8);
|
||||
//register word20 ro addr(b, 0x28) "Retired" type(uint16);
|
||||
//register word21 ro addr(b, 0x2A) "Retired" type(uint16);
|
||||
//register word22 ro addr(b, 0x2C) "Obsolete" type(uint16);
|
||||
regarray fwrev ro addr(b, 0x2E) [8] "Firmware revision" type(uint8);
|
||||
regarray mn ro addr(b, 0x36) [40] "Model number" type(uint8);
|
||||
register word47 ro addr(b, 0x5E) "Stuff" {
|
||||
unk 8 "Must be 80h";
|
||||
maxls 8 "00h = Reserved, 01h-FFh = Maximum number of logical sectors that shall be transferred per DRQ data block on READ/WRITE MULTIPLE commands";
|
||||
};
|
||||
register tcfso ro addr(b, 0x60) "Trusted Computing feature set options" {
|
||||
_ 1 "Must be 0";
|
||||
_ 1 "Must be 0";
|
||||
rsvd 13 "Reserved for the Trusted Computing Group";
|
||||
tc 1 "Trusted Computing feature set is supported";
|
||||
};
|
||||
register caps0 ro addr(b, 0x62) "Capabilities part 1" {
|
||||
_ 2 "Reserved for the IDENTIFY PACKET DEVICE command";
|
||||
sby 1 "Standby tiemr values (0 = managed by device, 1 = as in standard)";
|
||||
_ 1 "Reserved for the IDENTIFY PACKET DEVICE command";
|
||||
iors 1 "IORDY supported";
|
||||
iord 1 "IORDY may be disabled";
|
||||
lbas 1 "LBA supported";
|
||||
dmas 1 "DMA supported";
|
||||
_ 8 "Retired";
|
||||
};
|
||||
register caps1 ro addr(b, 0x64) "Capabilities part 2" {
|
||||
_ 1 "Shall be cleared to zero";
|
||||
_ 1 "Shall be set to one";
|
||||
_ 12 "Reserved";
|
||||
_ 1 "Obsolete";
|
||||
dstm 1 "Shall be set to one to indicate a device specific Standby timer value minimum.";
|
||||
};
|
||||
//register word51 ro addr(b, 0x66) "Obsolete" type(uint16);
|
||||
//register word52 ro addr(b, 0x68) "Obsolete" type(uint16);
|
||||
|
||||
register tnuas ro addr(b, 0x78) "Total number of user addressable sectors" type(uint32);
|
||||
|
||||
register mwdma ro addr(b, 0x7E) "Supported DMA Modes" {
|
||||
_ 5 "Reserved";
|
||||
m2sel 1 "Multiword DMA mode 2 selected";
|
||||
m1sel 1 "Multiword DMA mode 1 selected";
|
||||
m0sel 1 "Multiword DMA mode 0 selected";
|
||||
_ 5 "Reserved";
|
||||
m2sup 1 "Multiword DMA mode 2 and below are supported";
|
||||
m1sup 1 "Multiword DMA mode 1 and below are supported";
|
||||
m0sup 1 "Multiword DMA mode 0 is supported";
|
||||
};
|
||||
|
||||
register pio ro addr(b, 0x80) "Supported PIO modes" {
|
||||
_ 8 "Reserved";
|
||||
msup 8 "PIO modes supported";
|
||||
};
|
||||
|
||||
register majrn ro addr(b, 0xA0) "Major revision number" {
|
||||
_ 7 "Reserved";
|
||||
a8 1 "Supports ATA8-ACS";
|
||||
a7 1 "Supports ATA/ATAPI-7";
|
||||
a6 1 "Supports ATA/ATAPI-6";
|
||||
a5 1 "Supports ATA/ATAPI-5";
|
||||
a4 1 "Supports ATA/ATAPI-4";
|
||||
_ 3 "Obsolete";
|
||||
_ 1 "Reserved";
|
||||
};
|
||||
register minrn ro addr(b, 0xA2) "Minor revision number" type(uint16);
|
||||
register css0 ro addr(b, 0xA4) "Command set supported part 1" {
|
||||
_ 1 "Obsolete";
|
||||
nop 1 "NOP command supported";
|
||||
reab 1 "READ BUFFER command supported";
|
||||
wrtb 1 "WRITE BUFFER command supported";
|
||||
_ 1 "Obsolete";
|
||||
hpa 1 "Host Protected Area feature set supported";
|
||||
drst 1 "DEVICE RESET command supported";
|
||||
svci 1 "SERVICE interrupt supported";
|
||||
reli 1 "Release interrupt supported";
|
||||
loka 1 "Look-ahead supported";
|
||||
wrtc 1 "Write cache supported";
|
||||
pack 1 "Cleared to indicate PACKET feature set not supported";
|
||||
pwrm 1 "Mandatory Power Management feature set supported";
|
||||
_ 1 "Obsolete";
|
||||
secm 1 "Security Mode feature set supported";
|
||||
smrt 1 "SMART feature set supported";
|
||||
};
|
||||
register css1 ro addr(b, 0xA6) "Command sets supported part 2" {
|
||||
_ 1 "Shall be cleared to zero";
|
||||
_ 1 "Shall be set to one";
|
||||
flcx 1 "FLUSH CACHE EXT command supported";
|
||||
flc 1 "Mandatory FLUSH CACHE command supported";
|
||||
dco 1 "Mandatory Device Configuration Overlay feature set supported";
|
||||
lba48 1 "48-bit Address feature set supported";
|
||||
aam 1 "Automatic Acoustic Management feature set supported";
|
||||
smsec 1 "SET MAX security extension supported";
|
||||
orab 1 "See Address Offset Reserved Area Boot, INCITS TR27:2001";
|
||||
sfspn 1 "SET FEATUREs subcommand required to spin-up after power-up";
|
||||
puis 1 "Power-Up In Standby feature set supported";
|
||||
_ 1 "Obsolete";
|
||||
apm 1 "Advanced Power Management feature set supported";
|
||||
cfa 1 "CFA feature set supported";
|
||||
dmaq 1 "READ/WRITE DMA QUEUED supported";
|
||||
dlmc 1 "DOWNLOAD MICROCODE command supported";
|
||||
};
|
||||
register css2 ro addr(b, 0xA8) "Command set/feature supported part 3" {
|
||||
_ 1 "Shall be cleared to zero";
|
||||
_ 1 "Shall be set to one";
|
||||
iiwuf 1 "IDLE IMMEDIATE with UNLOAD FEATURE supported";
|
||||
_ 2 "Reserved for technical report INCITS TR-37-2004 (TLC)";
|
||||
_ 2 "Obsolete";
|
||||
wwn64 1 "64-bit World wide name supported";
|
||||
wdmaqfuax 1 "WRITE DMA QUEUED FUA EXT command supported";
|
||||
wdmafuax 1 "WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands supported";
|
||||
gpl 1 "General Purpose Logging feature set supported";
|
||||
strm 1 "Streaming feature set supported";
|
||||
mcptc 1 "Media Card Pass Through Command feature set supported";
|
||||
msn 1 "Media serial number supported";
|
||||
smtst 1 "SMART self-test supported";
|
||||
smtel 1 "SMART error logging supported";
|
||||
};
|
||||
|
||||
register tnuas48 ro addr(b, 0xC8) "Total Number of User Addressable Sectors for the 48-bit Address feature set" type(uint64);
|
||||
|
||||
register plss ro addr(b, 0xD4) "Physical Sector Size / Logical Sector Size" {
|
||||
_ 1 "Shall be cleared to zero";
|
||||
_ 1 "Shall be set to one";
|
||||
mlpp 1 "Device has multiple logical sectors per phyiscal sector";
|
||||
lls 1 "Device Logical Sector Longer than 256 Words";
|
||||
_ 8 "Reserved";
|
||||
lpp 4 "2^X logical sectors per physical sector";
|
||||
};
|
||||
|
||||
register wpls ro addr(b, 0xEA) "Words per Logical Sector" type(uint32);
|
||||
|
||||
register tmajrn ro addr(b, 0x1BC) "Transport Major revision number" {
|
||||
tt 4 "Transport Type - 0 = Parallel, 1 = Serial, 2-15 = Reserved";
|
||||
_ 8 "Reserved";
|
||||
v3 1 "Type Serial: SATA Rev 2.5";
|
||||
v2 1 "Type Serial: SATA II: Extensions";
|
||||
v1 1 "Type Serial: SATA 1.0a";
|
||||
v0 1 "Type Parallel: ATA8-APT. Type Serial: ATA8-AST";
|
||||
};
|
||||
register tminrn ro addr(b, 0x1BE) "Transport Minor revision number" type(uint16);
|
||||
|
||||
};
|
||||
168
devices/audio_nbm.dev
Normal file
168
devices/audio_nbm.dev
Normal file
@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* audio_nbm.dev
|
||||
*
|
||||
* DESCRIPTION: Intel Native Audio Bus Master registers
|
||||
*
|
||||
* Numbers in comments refer to the Intel 631xESB/632xESB I/O
|
||||
* Controller Hub Datasheet
|
||||
*/
|
||||
|
||||
device audio_nbm msbfirst ( io base ) "Native Audio Bus Master" {
|
||||
|
||||
// 19.2.1
|
||||
regtype bdbar "Buffer descriptor base address" {
|
||||
a 29 "Address [31:3]";
|
||||
_ 3 mbz;
|
||||
};
|
||||
|
||||
// 19.2.4
|
||||
regtype sr "Status" {
|
||||
_ 11;
|
||||
fifoe 1 rwc "FIFO error";
|
||||
bcis 1 rwc "Buffer completion interrupt status";
|
||||
lvbci 1 rwc "Last valid buffer completion interrupt";
|
||||
celv 1 ro "Current equals last valid";
|
||||
dch 1 ro "DMA controller halted";
|
||||
};
|
||||
|
||||
// 19.2.7
|
||||
regtype cr "Control" {
|
||||
_ 3;
|
||||
ioce 1 "Interrupt on completion enable";
|
||||
feie 1 "FIFO error interrupt enable";
|
||||
lvbie 1 "Last valid buffer interrupt enable";
|
||||
rr 1 "Reset registers";
|
||||
rpbm 1 "Run/pause bus master";
|
||||
};
|
||||
|
||||
// 19.2.8
|
||||
constants pcm_om "PCM output mode" {
|
||||
b16 = 0b00 "16 bit audio";
|
||||
b20 = 0b01 "20 bit audio";
|
||||
};
|
||||
constants pcm_cm "PCM channel mode" {
|
||||
c2 = 0b00 "2 channels";
|
||||
c4 = 0b01 "4 channels";
|
||||
c6 = 0b10 "6 channels";
|
||||
};
|
||||
|
||||
register glob_cnt rw io(base, 0x2c) "Global control" {
|
||||
ssm 2 "S/PDIF slot map";
|
||||
_ 6;
|
||||
pom 2 type(pcm_om) "PCM out mode";
|
||||
pcm46 2 type(pcm_cm) "PCM channel mode";
|
||||
_ 13;
|
||||
s2ie 1 "ACZ_SDIN2 interrupt enable";
|
||||
s1ie 1 "ACZ_SDIN1 interrupt enable";
|
||||
s0ie 1 "ACZ_SDIN0 interrupt enable";
|
||||
ldo 1 "AC-LINK shut off";
|
||||
awr 1 "AC97 warm reset";
|
||||
acr 1 "AC97 cold reset";
|
||||
gie 1 "GPI interrupt enable";
|
||||
};
|
||||
|
||||
|
||||
// 19.2.9
|
||||
register glob_sta io(base, 0x30) "Global status" {
|
||||
_ 2;
|
||||
s2ri 1 rwc "ACZ_SDIN2 resume interrupt";
|
||||
s2cr 1 ro "ACZ_SDIN2 codec ready";
|
||||
bcs 1 ro "Bit clock stopped";
|
||||
spint 1 ro "S/PDIF interrupt";
|
||||
p2int 1 ro "PCM in 2 interrupt";
|
||||
m2int 1 ro "Microphone 2 in interrupt";
|
||||
scap 2 ro "Sample capabilities";
|
||||
mcap 2 ro "Multichannel capabilities";
|
||||
_ 2;
|
||||
md3 1 rw "Power down semaphore for modem";
|
||||
ad3 1 rw "Power down semaphore for audio";
|
||||
rcs 1 rwc "Read completion status";
|
||||
slot12 3 ro "Display bits 1-3 of most recent slot 12";
|
||||
s1ri 1 rwc "ACZ_SDIN1 resume interrupt";
|
||||
s0ri 1 rwc "ACZ_SDIN0 resume interrupt";
|
||||
s1cr 1 ro "ACZ_SDIN1 codec ready";
|
||||
s0cr 1 ro "ACZ_SDIN0 codec ready";
|
||||
mint 1 ro "Microphone in interrupt";
|
||||
point 1 ro "PCM out interrupt";
|
||||
piint 1 ro "PCM in interrupt";
|
||||
_ 2;
|
||||
moint 1 ro "Modem out interrupt";
|
||||
miint 1 ro "Modem in interrupt";
|
||||
gsci 1 rwc "GPI status change interrupt";
|
||||
};
|
||||
|
||||
// 19.2.10
|
||||
register cas rw io(base, 0x34) "Codec access semaphore" {
|
||||
_ 7;
|
||||
s 1 "read to set";
|
||||
};
|
||||
|
||||
// 19.2.11
|
||||
register sdm io(base, 0x80) "SDATA_IN map" {
|
||||
di2l 2 rw "PCM in 2, Mic in 2 data in line";
|
||||
di1l 2 rw "PCM in 1, Mic in 1 data in line";
|
||||
se 1 rw "Steer enable";
|
||||
_ 1;
|
||||
ldi 2 ro "Last codec read data input";
|
||||
};
|
||||
|
||||
// 19.2
|
||||
register pi_bdbar rw io(base, 0x00) "PCM in buffer desc. list base" type(bdbar);
|
||||
register pi_civ ro io(base, 0x04) "PCM in cur. index value" type(uint8);
|
||||
register pi_lvi rw io(base, 0x05) "PCM in last valud index" type(uint8);
|
||||
register pi_sr io(base, 0x06) "PCM in status" type(sr);
|
||||
register pi_picb ro io(base, 0x08) "PCM in pos. in cur. buffer" type(uint16);
|
||||
register pi_piv ro io(base, 0x0a) "PCM in prefetched index val" type(uint8);
|
||||
register pi_cr rw io(base, 0x0b) "PCM in control" type(cr);
|
||||
|
||||
register po_bdbar rw io(base, 0x10) "PCM out buffer desc. list base" type(bdbar);
|
||||
register po_civ ro io(base, 0x14) "PCM out cur. index value" type(uint8);
|
||||
register po_lvi rw io(base, 0x15) "PCM out last valud index" type(uint8);
|
||||
register po_sr io(base, 0x16) "PCM out status" type(sr);
|
||||
register po_picb ro io(base, 0x18) "PCM out pos. in cur. buffer" type(uint16);
|
||||
register po_piv ro io(base, 0x1a) "PCM out prefetched index val" type(uint8);
|
||||
register po_cr rw io(base, 0x1b) "PCM out control" type(cr);
|
||||
|
||||
register mc_bdbar rw io(base, 0x20) "Mic in buffer desc. list base" type(bdbar);
|
||||
register mc_civ ro io(base, 0x24) "Mic in cur. index value" type(uint8);
|
||||
register mc_lvi rw io(base, 0x25) "Mic in last valud index" type(uint8);
|
||||
register mc_sr io(base, 0x26) "Mic in status" type(sr);
|
||||
register mc_picb ro io(base, 0x28) "Mic in pos. in cur. buffer" type(uint16);
|
||||
register mc_piv ro io(base, 0x2a) "Mic in prefetched index val" type(uint8);
|
||||
register mc_cr rw io(base, 0x2b) "Mic in control" type(cr);
|
||||
|
||||
register mc2_bdbar rw io(base, 0x40) "Mic 2 buffer desc. list base" type(bdbar);
|
||||
register mc2_civ ro io(base, 0x44) "Mic 2 cur. index value" type(uint8);
|
||||
register mc2_lvi rw io(base, 0x45) "Mic 2 last valud index" type(uint8);
|
||||
register mc2_sr io(base, 0x46) "Mic 2 status" type(sr);
|
||||
register mc2_picb ro io(base, 0x48) "Mic 2 pos. in cur. buffer" type(uint16);
|
||||
register mc2_piv ro io(base, 0x4a) "Mic 2 prefetched index val" type(uint8);
|
||||
register mc2_cr rw io(base, 0x4b) "Mic 2 control" type(cr);
|
||||
|
||||
register pi2_bdbar rw io(base, 0x50) "PCM in 2 buf desc. list base" type(bdbar);
|
||||
register pi2_civ ro io(base, 0x54) "PCM in 2 cur. index value" type(uint8);
|
||||
register pi2_lvi rw io(base, 0x55) "PCM in 2 last valud index" type(uint8);
|
||||
register pi2_sr io(base, 0x56) "PCM in 2 status" type(sr);
|
||||
register pi2_picb ro io(base, 0x58) "PCM in 2 pos. in cur. buf" type(uint16);
|
||||
register pi2_piv ro io(base, 0x5a) "PCM in 2 pref. index val" type(uint8);
|
||||
register pi2_cr rw io(base, 0x5b) "PCM in 2 control" type(cr);
|
||||
|
||||
register sp_bdbar rw io(base, 0x60) "S/PDIF buf desc. list base" type(bdbar);
|
||||
register sp_civ ro io(base, 0x64) "S/PDIF cur. index value" type(uint8);
|
||||
register sp_lvi rw io(base, 0x65) "S/PDIF last valud index" type(uint8);
|
||||
register sp_sr io(base, 0x66) "S/PDIF status" type(sr);
|
||||
register sp_picb ro io(base, 0x68) "S/PDIF pos. in cur. buf" type(uint16);
|
||||
register sp_piv ro io(base, 0x6a) "S/PDIF pref. index val" type(uint8);
|
||||
register sp_cr rw io(base, 0x6b) "S/PDIF control" type(cr);
|
||||
|
||||
};
|
||||
|
||||
|
||||
59
devices/cortex_a9_gt.dev
Normal file
59
devices/cortex_a9_gt.dev
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2013, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* cortex_a9_gt.dev
|
||||
*
|
||||
* DESCRIPTION: Cortex A9 Global Timer
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* Cortex-A9 MPCore Technical Reference Manual
|
||||
* (DDI0407G_cortex_a9_mpcore_r4p1_trm.pdf)
|
||||
*
|
||||
* This implements private timers and watchdogs
|
||||
*/
|
||||
|
||||
device cortex_a9_gt msbfirst ( addr base ) "Cortex A9 Global Timer" {
|
||||
|
||||
register TimerCounterLow addr(base, 0x0)
|
||||
"Counter (Lower Word)"
|
||||
type(uint32);
|
||||
|
||||
register TimerCounterHigh addr(base, 0x4)
|
||||
"Counter (Upper Word)"
|
||||
type(uint32);
|
||||
|
||||
register TimerControl addr(base, 0x8) "Control" {
|
||||
_ 16 rsvd;
|
||||
prescale 8 rw "Prescale factor";
|
||||
_ 4 rsvd;
|
||||
auto_increment 1 rw "Single shot or increment mode";
|
||||
int_enable 1 rw "Interrupt enable bit";
|
||||
comp_enable 1 rw "Enable comparision between counter and comparator";
|
||||
timer_enable 1 rw "Timer enable bit";
|
||||
};
|
||||
|
||||
register TimerIntStat addr(base, 0xc) "Interrupt Status" {
|
||||
_ 31 rsvd;
|
||||
event_flag 1 rw;
|
||||
};
|
||||
|
||||
register TimerComparatorLow addr(base, 0x10)
|
||||
"Comparator (Lower Word)"
|
||||
type(uint32);
|
||||
|
||||
register TimerComparatorHigh addr(base, 0x14)
|
||||
"Comparator (Upper Word)"
|
||||
type(uint32);
|
||||
|
||||
register TimerAutoIncrement addr(base, 0x18)
|
||||
"Comparator Auto-Increment"
|
||||
type(uint32);
|
||||
|
||||
};
|
||||
70
devices/cortex_a9_pit.dev
Normal file
70
devices/cortex_a9_pit.dev
Normal file
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* cortex_a9_pit.dev
|
||||
*
|
||||
* DESCRIPTION: Cortex A9 Private Timer and watchdog
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* Cortex-A9 MPCore Technical Reference Manual
|
||||
* (DDI0407G_cortex_a9_mpcore_r3p0_trm.pdf)
|
||||
*
|
||||
* This implements private timers and watchdogs
|
||||
*/
|
||||
|
||||
device cortex_a9_pit msbfirst ( addr base ) "Cortex A9 Private Timer and watchdog" {
|
||||
|
||||
register TimerLoad addr(base, 0x0) "Private Timer Load Register" type(uint32);
|
||||
|
||||
register TimerCounter addr(base, 0x4) "Private Timer Counter Register" type(uint32);
|
||||
|
||||
register TimerControl addr(base, 0x8) "Private Timer Control Register" {
|
||||
_ 16 mbz;
|
||||
prescale 8 rw "Prescale factor";
|
||||
_ 5 mbz;
|
||||
int_enable 1 rw "Interrupt enable bit";
|
||||
auto_reload 1 rw "Single shot or reload mode";
|
||||
timer_enable 1 rw "Timer enable bit";
|
||||
};
|
||||
|
||||
register TimerIntStat addr(base, 0xc) "Private Timer Interrupt Status Register" {
|
||||
_ 31 mbz;
|
||||
event_flag 1 rw1c;
|
||||
};
|
||||
|
||||
register WatchdogLoad addr(base, 0x20) "Watchdog Load Register" type(uint32);
|
||||
|
||||
register WatchdogCounter addr(base, 0x24) "Watchdog Counter Register" type(uint32);
|
||||
|
||||
register WatchdogControl addr(base, 0x28) "Watchdog Control Register" {
|
||||
_ 16 mbz;
|
||||
prescale 8 rw "Prescale factor";
|
||||
_ 4 mbz;
|
||||
wd_mode 1 rw "Selects Watchdog or Timer mode";
|
||||
int_enable 1 rw "Interrupt enable bit";
|
||||
auto_reload 1 rw "Single shot or reload mode";
|
||||
wd_enable 1 rw "Timer enable bit";
|
||||
};
|
||||
|
||||
register WatchdogIntStat addr(base, 0x2c) "Watchdog Interrupt Status Register" {
|
||||
_ 31 mbz;
|
||||
event_flag 1 rw1c;
|
||||
};
|
||||
|
||||
register WatchdogResStat addr(base, 0x30) "Watchdog Reset Status Register" {
|
||||
_ 31 mbz;
|
||||
reset_flag 1 rw1c;
|
||||
};
|
||||
|
||||
// Write 0x12345678 then 0x87654321 to this register to disable watchdog mode
|
||||
register WatchdogDisable wo addr(base, 0x34) "Watchdog Disable Register" type(uint32);
|
||||
|
||||
|
||||
};
|
||||
68
devices/cortex_a9_scu.dev
Normal file
68
devices/cortex_a9_scu.dev
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* a9scu.dev
|
||||
*
|
||||
* DESCRIPTION: Cortex A9 Snoop Control Unit
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* ARM Cortex-A9 MPCore Technical Reference Manual
|
||||
*
|
||||
*/
|
||||
|
||||
device cortex_a9_scu msbfirst ( addr base ) "Cortex A9 SCU" {
|
||||
|
||||
register control addr(base, 0x0) "SCU Control" {
|
||||
_ 25 rsvd;
|
||||
ic_standby 1 rw "IC standby enable";
|
||||
scu_standby 1 rw "SCU standby enable";
|
||||
all_device_to_port0 1 rw "Force all Device to port 0 enable";
|
||||
spec_linefill 1 rw "SCU speculative linefills enable";
|
||||
ram_parity 1 rw "SCU RAMs parity enable";
|
||||
address_filtering 1 rw "Address Filtering enable";
|
||||
enable 1 rw "SCU enable";
|
||||
};
|
||||
|
||||
register config ro addr(base, 0x4) "SCU Configuration" {
|
||||
_ 16;
|
||||
tag_ram_sizes 8 ro "Tag RAM sizes";
|
||||
cpu_smp 4 ro "CPUs SMP bits";
|
||||
_ 2;
|
||||
numcpus 2 ro "Number of CPUs present";
|
||||
};
|
||||
|
||||
constants cpu_status "CPU Status" {
|
||||
normal = 0b00 "Normal mode";
|
||||
dormant = 0b10 "Dormant mode";
|
||||
off = 0b11 "Powered-off mode";
|
||||
};
|
||||
|
||||
register powerstatus addr(base, 0x8) "SCU CPU Power Status" {
|
||||
_ 6;
|
||||
cpu3 2 rw "Status CPU3";
|
||||
_ 6;
|
||||
cpu2 2 rw "Status CPU2";
|
||||
_ 6;
|
||||
cpu1 2 rw "Status CPU1";
|
||||
_ 6;
|
||||
cpu0 2 rw "Status CPU0";
|
||||
};
|
||||
|
||||
register filterstart addr(base, 0x40) "Filtering Start Address" {
|
||||
addr 12 rw "Filtering Start address";
|
||||
_ 20;
|
||||
};
|
||||
|
||||
register filterend addr(base, 0x44) "Filtering End Address" {
|
||||
addr 12 rw "Filtering Start address";
|
||||
_ 20;
|
||||
};
|
||||
|
||||
};
|
||||
526
devices/cpuid.dev
Normal file
526
devices/cpuid.dev
Normal file
@ -0,0 +1,526 @@
|
||||
/*
|
||||
* Copyright (c) 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* cpuid.dev
|
||||
*
|
||||
* DESCRIPTION: ia32 CPU ID instruction results
|
||||
*
|
||||
* See:
|
||||
* Intel Architecture Manual, Volume 2A, pp. 3-163 - ff., August 2007
|
||||
* AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008
|
||||
*/
|
||||
|
||||
device cpuid lsbfirst () "ia32 / Intel64 CPUID instruction results" {
|
||||
|
||||
// We define a different address space for each register
|
||||
space eax(i) valuewise "Results in EAX";
|
||||
space ebx(i) valuewise "Results in EBX";
|
||||
space ecx(i) valuewise "Results in ECX";
|
||||
space edx(i) valuewise "Results in EDX";
|
||||
|
||||
//
|
||||
// Basic CPUID information
|
||||
//
|
||||
|
||||
//
|
||||
// EAX=0x00
|
||||
//
|
||||
|
||||
register max_biv ro eax(0x00) "Maximum input val for basic CPUID info"
|
||||
type(uint32);
|
||||
register vendor0 ro ebx(0x00) "Vendor string part 1" type(uint32);
|
||||
register vendor1 ro edx(0x00) "Vendor string part 2" type(uint32);
|
||||
register vendor2 ro ecx(0x00) "Vendor string part 3" type(uint32);
|
||||
|
||||
//
|
||||
// EAX=0x01
|
||||
//
|
||||
|
||||
register ver_info ro eax(0x01) "Version information" {
|
||||
stepping 4 "Stepping ID";
|
||||
model 4 "Model ID";
|
||||
family 4 "Family ID";
|
||||
proc_type 2 "Processor type (Intel only)";
|
||||
_ 2 mbz;
|
||||
extmodel 4 "Extended model ID";
|
||||
extfamily 8 "Extended family ID";
|
||||
_ 4 mbz;
|
||||
};
|
||||
|
||||
register brand_ndx ro ebx(0x01) "Brand Index, APIC info" {
|
||||
brand 8 "Brand index";
|
||||
cflush_sz 8 "CFLUSH line size";
|
||||
max_log_proc 8 "Max. # logical processors in this package";
|
||||
init_apic_id 8 "Initial local APIC physical ID";
|
||||
};
|
||||
|
||||
register feat_info ro edx(0x01) "Feature information" {
|
||||
fpu_x87 1 "FPU on chip";
|
||||
vme 1 "Virtual-8086 mode enhancement";
|
||||
de 1 "Debugging extensions";
|
||||
pse 1 "Page size extensions";
|
||||
tsc 1 "Time stamp counter";
|
||||
msr 1 "RDMSR and WRMSR support";
|
||||
pae 1 "Physical address extensions";
|
||||
mce 1 "Machine check exception";
|
||||
cx8 1 "CMPXCHG8B instruction";
|
||||
apic 1 "APIC on chip";
|
||||
_ 1;
|
||||
sep 1 "SYSENTER and SYSEXIT";
|
||||
mtrr 1 "Memory type range registers";
|
||||
pge 1 "PTE global bit";
|
||||
mca 1 "Machine check architecture";
|
||||
cmov 1 "Conditional move/compare instruction";
|
||||
pat 1 "Page attribute table";
|
||||
pse36 1 "Page size extension";
|
||||
psn 1 "Processor serial number";
|
||||
clfsh 1 "CFLUSH instruction";
|
||||
_ 1;
|
||||
ds 1 "Debug store";
|
||||
acpi 1 "Thermal monitor and clock control";
|
||||
mmx 1 "MMX technology";
|
||||
fxsr 1 "FXSAVE / FXRSTOR";
|
||||
sse 1 "SSE instructions";
|
||||
sse2 1 "SSE2 instructions";
|
||||
ss 1 "Self-snoop";
|
||||
htt 1 "Multi-threading";
|
||||
tm 1 "Thermal monitor";
|
||||
_ 1;
|
||||
pbe 1 "Pending break enable";
|
||||
};
|
||||
|
||||
register ext_feat_info ro ecx(0x01) "Extended feature information" {
|
||||
sse3 1 "SSE3 extensions";
|
||||
_ 2;
|
||||
monitor 1 "MONITOR/MWAIT";
|
||||
ds_cpl 1 "CPL qualified debug store";
|
||||
vmx 1 "Virtual machine extensions";
|
||||
smx 1 "Safer mode extensions";
|
||||
est 1 "Enhanced Intel SpeedStep(tm) technology";
|
||||
tm2 1 "Thermal monitor 2";
|
||||
ssse3 1 "Supplemental SSE3 extensions";
|
||||
cnxt_id 1 "L1 context ID";
|
||||
_ 2;
|
||||
cmpxchg16b 1 "CMPXCHG16B available";
|
||||
xtpr_up 1 "xTPR update control";
|
||||
pdcm 1 "Perfmon and debug capability";
|
||||
_ 3;
|
||||
sse4_1 1 "SSE4.1";
|
||||
sse4_2 1 "SSE4.2";
|
||||
_ 2;
|
||||
popcnt 1 "POPCNT instruction";
|
||||
_ 8;
|
||||
};
|
||||
|
||||
//
|
||||
// EAX=0x02 : Cache descriptors (Intel only)
|
||||
//
|
||||
|
||||
// Intel, Table 3.17
|
||||
constants intel_cache_desc "Intel Cache & TLB descriptors" {
|
||||
null_cd = 0x00 "Null descriptor";
|
||||
itlb_4k_4w_32 = 0x01 "ITLB, 4k pages, 4-way, 32 entries";
|
||||
itlb_4m_4w_2 = 0x02 "ITLB, 4M pages, 4-way, 2 entries";
|
||||
dtlb_4k_4w_64 = 0x03 "DTLB, 4k pages, 4-way, 64 entries";
|
||||
dtlb_4m_4w_8 = 0x04 "DTLB, 4M pages, 4-way, 8 entries";
|
||||
dtlb1_4m_4w_32 = 0x05 "DTLB1, 4M pages, 4-way, 32 entries";
|
||||
l1i_8k_4w_32 = 0x06 "L1 Icache, 8k, 4-way, 32b lines";
|
||||
|
||||
l1i_16k_4w_32 = 0x08 "L1 Icache, 16k, 4-way, 32b lines";
|
||||
|
||||
l1d_8k_2w_32 = 0x0a "L1 Dcache, 8k, 2-way, 32b lines";
|
||||
itlb_4m_4w_4 = 0x0b "ITLB, 4M pages, 4-way, 4 entries";
|
||||
l1d_16k_4w_32 = 0x0c "L1 Dcache, 16k, 4-way, 32b lines";
|
||||
|
||||
l3_512k_4w_64_2 = 0x22 "L3 cache, 512k, 4-way, 64b lines, 2/sector";
|
||||
l3_1m_8w_64_2 = 0x23 "L3 cache, 1M, 8-way, 64b lines, 2/sector";
|
||||
l3_2m_8w_64_2 = 0x25 "L3 cache, 2M, 8-way, 64b lines, 2/sector";
|
||||
l3_4m_8w_64_2 = 0x29 "L3 cache, 4M, 8-way, 64b lines, 2/sector";
|
||||
|
||||
l1d_32k_8w_64 = 0x2c "L1 Dcache, 32k, 8-way, 64b lines";
|
||||
l1i_32k_8w_64 = 0x30 "L1 Icache, 32k, 8-way, 64b lines";
|
||||
|
||||
no_l2_l3 = 0x40 "No L2 or L3 cache";
|
||||
|
||||
l2_128k_4w_32 = 0x41 "L2 cache, 128k, 4-way, 32b lines";
|
||||
l2_256k_4w_32 = 0x42 "L2 cache, 256k, 4-way, 32b lines";
|
||||
l2_512k_4w_32 = 0x43 "L2 cache, 512k, 4-way, 32b lines";
|
||||
l2_1m_4w_32 = 0x44 "L2 cache, 1M, 4-way, 32b lines";
|
||||
l2_2m_4w_32 = 0x45 "L2 cache, 2M, 4-way, 32b lines";
|
||||
|
||||
l3_4m_4w_64 = 0x46 "L3 cache, 4M, 4-way, 64b lines";
|
||||
l3_8m_8w_64 = 0x47 "L3 cache, 8M, 8-way, 64b lines";
|
||||
|
||||
l2_4m_16w_64 = 0x49 "L2 cache, 4M, 16-way, 64b lines";
|
||||
|
||||
itlb_4k2m4n_64 = 0x50 "ITLB, 4k & 2M or 4M pages, 64 entries";
|
||||
itlb_4k2m4n_128 = 0x51 "ITLB, 4k & 2M or 4M pages, 128 entries";
|
||||
itlb_4k2m4n_256 = 0x52 "ITLB, 4k & 2M or 4M pages, 256 entries";
|
||||
|
||||
dtlb0_4m_4w_16 = 0x56 "DTLB0, 4M pages, 4-way, 16 entries";
|
||||
dtlb0_4k_4w_16 = 0x57 "DTLB0, 4k pages, 4-way, 16 entries";
|
||||
|
||||
dtlb_4k4m_64 = 0x5b "DTLB, 4k & 4M pages, 64 entries";
|
||||
dtlb_4k4m_128 = 0x5c "DTLB, 4k & 4M pages, 128 entries";
|
||||
dtlb_4k4m_256 = 0x5d "DTLB, 4k & 4M pages, 256 entries";
|
||||
|
||||
l1d_16k_8w_64 = 0x60 "L1 Dcache, 16k, 8-way, 64b lines";
|
||||
l1d_8k_4w_64 = 0x66 "L1 Dcache, 8k, 4-way, 64b lines";
|
||||
l1d_16k_4w_64 = 0x67 "L1 Dcache, 16k, 4-way, 64b lines";
|
||||
l1d_32k_4w_64 = 0x68 "L1 Dcache, 32k, 4-way, 64b lines";
|
||||
|
||||
tc_12k_8w = 0x70 "Trace cache, 12k-uop, 8-way";
|
||||
tc_16k_8w = 0x71 "Trace cache, 16k-uop, 8-way";
|
||||
tc_32k_8w = 0x72 "Trace cache, 32k-uop, 8-way";
|
||||
|
||||
l2_1M_4w_64 = 0x78 "L2 cache, 1M, 4-way, 64b lines";
|
||||
l2_128k_8w_64_2 = 0x79 "L2 cache, 128k, 8-way, 64b lines, 2/sector";
|
||||
l2_256k_8w_64_2 = 0x7a "L2 cache, 256k, 8-way, 64b lines, 2/sector";
|
||||
l2_512k_8w_64_2 = 0x7b "L2 cache, 512k, 8-way, 64b lines, 2/sector";
|
||||
l2_1M_8w_64_2 = 0x7c "L2 cache, 1M, 8-way, 64b lines, 2/sector";
|
||||
l2_2M_8w_64 = 0x7d "L2 cache, 2M, 8-way, 64b lines";
|
||||
|
||||
l2_512k_2w_64 = 0x7f "L2 cache, 512k, 2-way, 64b lines";
|
||||
|
||||
l2_256k_8w_32 = 0x82 "L2 cache, 256k, 8-way, 32b lines";
|
||||
l2_512k_8w_32 = 0x83 "L2 cache, 512k, 8-way, 32b lines";
|
||||
l2_1M_8w_32 = 0x84 "L2 cache, 1M, 8-way, 32b lines";
|
||||
l2_2M_8w_32 = 0x85 "L2 cache, 2M, 8-way, 32b lines";
|
||||
l2_512k_4w_64 = 0x86 "L2 cache, 512k, 4-way, 64b lines";
|
||||
l2_1M_8w_64 = 0x87 "L2 cache, 1M, 8-way, 64b lines";
|
||||
|
||||
itlb_4k_4w_128 = 0xb0 "ITLB, 4k pages, 4-way, 128 entries";
|
||||
|
||||
dtlb_4k_4w_128 = 0xb3 "DTLB, 4k pages, 4-way, 128 entries";
|
||||
dtlb1_4k_4w_256 = 0xb4 "DTLB1, 4k pages, 4-way, 256 entries";
|
||||
|
||||
pref_64 = 0xf0 "64-byte prefetching";
|
||||
pref_128 = 0xf1 "128-byte prefetching";
|
||||
};
|
||||
|
||||
/*
|
||||
* Exclude this insane mess for now until we really, really need it.
|
||||
*
|
||||
regtype cache_info "Intel cache/TLB info" {
|
||||
d0 8 type(intel_cache_desc) "Descriptor 0";
|
||||
d1 8 type(intel_cache_desc) "Descriptor 1";
|
||||
d2 8 type(intel_cache_desc) "Descriptor 2";
|
||||
d3 7 type(intel_cache_desc) "Descriptor 3";
|
||||
valid 1 "Contains valid descriptors";
|
||||
};
|
||||
register cache_i_a ro eax(0x02) "Intel cache/TLB info eax" type(cache_info);
|
||||
register cache_i_b ro ebx(0x02) "Intel cache/TLB info ebx" type(cache_info);
|
||||
register cache_i_c ro ecx(0x02) "Intel cache/TLB info ecx" type(cache_info);
|
||||
register cache_i_d ro edx(0x02) "Intel cache/TLB info edx" type(cache_info);
|
||||
*/
|
||||
|
||||
//
|
||||
// EAX=0x03 : Processor serial number (Intel only)
|
||||
//
|
||||
|
||||
register pns0 ro ecx(0x03) "Processor serial no. bits 0-31" type(uint32);
|
||||
register pns1 ro edx(0x03) "Processor serial no. bits 32-63" type(uint32);
|
||||
|
||||
//
|
||||
// EAX=0x04 : Deterministic cache parameters leaf (Intel only)
|
||||
//
|
||||
|
||||
constants intel_cachetype "Intel cache type field" {
|
||||
ct_null = 0 "Null, no more caches";
|
||||
ct_data = 1 "Data cache";
|
||||
ct_instruction = 2 "Instruction cache";
|
||||
ct_unified = 3 "Unified cache";
|
||||
};
|
||||
|
||||
space dcpa(i) valuewise "Deterministic cache parameters leaf A";
|
||||
regarray cache_type ro dcpa(0x00)[4] "Cache type information" {
|
||||
ctf 5 type(intel_cachetype) "Cache type";
|
||||
level 3 "Cache level (starts at 1)";
|
||||
self_init 1 "Self initializing";
|
||||
fully_assoc 1 "Fully associative";
|
||||
wb_inval 1 "Write-back invalidate/invalidate";
|
||||
inclusiveness 1 "Cache inclusiveness";
|
||||
_ 2;
|
||||
max_threads 12 "Max. # threads sharing this cache in package";
|
||||
max_procs 6 "Max. # processor cores in this package";
|
||||
};
|
||||
|
||||
space dcpb(i) valuewise "Deterministic cache parameters leaf B";
|
||||
regarray cache_pars ro dcpb(0x00)[4] "Cache parameters" {
|
||||
l 12 "System coherency line size (-1)";
|
||||
p 10 "Physical line partitions (-1)";
|
||||
w 10 "Ways of associativity (-1)";
|
||||
};
|
||||
|
||||
space dcpc(i) valuewise "Deterministic cache parameters leaf C";
|
||||
regarray num_sets ro dcpc(0x00)[4] "Number of sets" type(uint32);
|
||||
|
||||
//
|
||||
// EAX=0x05 : MONITOR / MWAIT leaf
|
||||
//
|
||||
|
||||
register min_monitor ro eax(0x05) "Smallest monitor-line size)" {
|
||||
sz 16 "Smallest monitor-line size (bytes)";
|
||||
_ 16 mbz;
|
||||
};
|
||||
register max_monitor ro ebx(0x05) "Largest monitor-line size)" {
|
||||
sz 16 "Largest monitor-line size (bytes)";
|
||||
_ 16;
|
||||
};
|
||||
register mwait_feat ro ecx(0x05) "MONITOR/MWAIT features" {
|
||||
emx 1 "Supports enum. of Monitor/Mwait extensions";
|
||||
ibe 1 "Supports interrupts as break event";
|
||||
_ 30;
|
||||
};
|
||||
register mwait_cstates ro edx(0x05) "sub-C states supported by MWAIT" {
|
||||
c0 4 "# C0 sub-C-states supported";
|
||||
c1 4 "# C1 sub-C-states supported";
|
||||
c2 4 "# C2 sub-C-states supported";
|
||||
c3 4 "# C3 sub-C-states supported";
|
||||
c4 4 "# C4 sub-C-states supported";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
//
|
||||
// EAX=0x06 : Thermal and Power Management Leaf (Intel only)
|
||||
//
|
||||
|
||||
register tpm_feat ro eax(0x06) "Thermal features" {
|
||||
dts 1 "Digital temperature sensor supported";
|
||||
ida 1 "Intel dynamic acceleration enabled";
|
||||
_ 30 mbz;
|
||||
};
|
||||
register tpm_thresh ro ebx(0x06) "# interrupt thresholds in sensor" {
|
||||
val 4 "# interrupt thresholds in sensor";
|
||||
_ 28;
|
||||
};
|
||||
register tpm_hcfc ro ecx(0x06) "Hardware coordination feedback" {
|
||||
en 1 "HCFC present (MCNT/ACNT MSRs)";
|
||||
_ 31;
|
||||
};
|
||||
|
||||
//
|
||||
// EAX=0x0a : Architectural Performance Monitoring Leaf (Intel
|
||||
// only)
|
||||
|
||||
register apm_gen ro eax(0x0a) "Gen-purpose perf. counter info" {
|
||||
version 8 "Version ID";
|
||||
num_counters 8 "# GP perf. counters per logical processor";
|
||||
width 8 "Bit width of GP perf. counters";
|
||||
vec_length 8 "EBX bit vector length to enumerate events";
|
||||
};
|
||||
register apm_feat ro ebx(0x0a) "Performance monitoring event availability" {
|
||||
cc 1 "Core cycle event";
|
||||
ir 1 "Instruction retired";
|
||||
rc 1 "Reference cycles";
|
||||
llcr 1 "Last-level cache reference";
|
||||
llcm 1 "Last-level cache miss";
|
||||
bir 1 "Branch instruction retired";
|
||||
bmr 1 "Branch mispredict retired";
|
||||
_ 25 mbz;
|
||||
};
|
||||
register apm_fixed ro edx(0x0a) "Fixed-function perf. counter infos" {
|
||||
num 5 "# Fixed-function perf. counters";
|
||||
width 8 "Width of fixed-function perf. counters";
|
||||
_ 19;
|
||||
};
|
||||
|
||||
//
|
||||
// Extended CPU information
|
||||
//
|
||||
|
||||
register ext_biv ro eax(0x80000000) "Max input val for ext. CPUID info"
|
||||
type(uint32);
|
||||
register evendor0 ro ebx(0x80000000) "Ext. Vendor string pt 1" type(uint32);
|
||||
register evendor1 ro edx(0x80000000) "Ext. Vendor string pt 2" type(uint32);
|
||||
register evendor2 ro ecx(0x80000000) "Ext. Vendor string pt 3" type(uint32);
|
||||
|
||||
// Mostly AMD only
|
||||
register brandid ro ebx(0x80000001) "Brand ID identifier" {
|
||||
id 16 "Extended brand ID";
|
||||
_ 12;
|
||||
pkgtype 4 "Package type";
|
||||
};
|
||||
register ext_featc ro ecx(0x80000001) "Extend misc. features 1" {
|
||||
lahfsahf 1 "LAHF & SAHF support in 64-bit mode";
|
||||
cmplegacy 1 "Core multiprocessing legacy mode";
|
||||
svm 1 "Secure virtual machine";
|
||||
extapicspace 1 "Extended APIC space";
|
||||
altmovcr8 1 "LOCK MOV CR0 means MOV CR8";
|
||||
abm 1 "Advanced bit manipulation";
|
||||
sse4a 1 "EXTRQ/INSERTQ/MOVNTSS/MOVNTSD support";
|
||||
misalignsse 1 "Misaligned SSE mode";
|
||||
pref3dnow 1 "PREFETCH/PREFETCHW support";
|
||||
osvw 1 "OS visible workaround";
|
||||
ibs 1 "Instruction-based sampling";
|
||||
sse5 1 "SSE 5 instruction support";
|
||||
skinit 1 "SKINIT/STGI supported";
|
||||
wdt 1 "Watchdog timer support";
|
||||
_ 18;
|
||||
};
|
||||
register ext_featd ro edx(0x80000001) "Extend misc. features 2" {
|
||||
_ 11;
|
||||
syscallsysret 1 "SYSCALL/SYSRET available in 64-bit mode";
|
||||
_ 8;
|
||||
nx 1 "No-execute page protection";
|
||||
_ 1;
|
||||
mmxext 1 "AMD extensions to MMX instructions";
|
||||
_ 2;
|
||||
ffxsr 1 "FFXSR instruction optimizations";
|
||||
page1fb 1 "1-GB large page support";
|
||||
rdtscp 1 "RDTSCP instruction";
|
||||
_ 1;
|
||||
longmode 1 "Long mode / Intel64 available";
|
||||
i3dnowext 1 "AMD extensions to 3DNow! instructions";
|
||||
i3dnow 1 "3DNow! instructions";
|
||||
};
|
||||
|
||||
register brand0 ro eax(0x80000002) "Brand string contd." type(uint32);
|
||||
register brand1 ro ebx(0x80000002) "Brand string contd." type(uint32);
|
||||
register brand2 ro ecx(0x80000002) "Brand string contd." type(uint32);
|
||||
register brand3 ro edx(0x80000002) "Brand string contd." type(uint32);
|
||||
|
||||
register brand4 ro eax(0x80000003) "Brand string contd." type(uint32);
|
||||
register brand5 ro ebx(0x80000003) "Brand string contd." type(uint32);
|
||||
register brand6 ro ecx(0x80000003) "Brand string contd." type(uint32);
|
||||
register brand7 ro edx(0x80000003) "Brand string contd." type(uint32);
|
||||
|
||||
register brand8 ro eax(0x80000004) "Brand string contd." type(uint32);
|
||||
register brand9 ro ebx(0x80000004) "Brand string contd." type(uint32);
|
||||
register branda ro ecx(0x80000004) "Brand string contd." type(uint32);
|
||||
register brandb ro edx(0x80000004) "Brand string contd." type(uint32);
|
||||
|
||||
//
|
||||
// EAX=0x80000005 : L1 cache and TLB identifiers (AMD only)
|
||||
//
|
||||
regtype amd_tlbinfo1 "AMD TLB information" {
|
||||
itlb_sz 8 "Number of instruction TLB entries";
|
||||
itlb_asc 8 "Instruction TLB associativity";
|
||||
dtlb_sz 8 "Number of data DTLB entries";
|
||||
dtlb_asc 8 "Data TLB associativity";
|
||||
};
|
||||
regtype amd_cacheinfo1 "AMD cache information" {
|
||||
linesize 8 "line size";
|
||||
lpt 8 "lines per tag";
|
||||
assoc 8 "associativity";
|
||||
size 8 "size in Kb";
|
||||
};
|
||||
register l1_24m ro eax(0x80000005) "AMD L1 TLB info for 2MB/4MB pages"
|
||||
type(amd_tlbinfo1);
|
||||
register l1_4k ro ebx(0x80000005) "AMD L1 TLB info for 4k pages"
|
||||
type(amd_tlbinfo1);
|
||||
register l1_dci ro ecx(0x80000005) "AMD L1 DCache info"
|
||||
type(amd_cacheinfo1);
|
||||
register l1_ici ro edx(0x80000005) "AMD L1 ICache info"
|
||||
type(amd_cacheinfo1);
|
||||
|
||||
//
|
||||
// EAX=0x80000006 : L2 cache and TLB identifiers (mostly AMD only)
|
||||
//
|
||||
regtype amd_tlbinfo23 "AMD TLB information" {
|
||||
itlb_sz 12 "Number of instruction TLB entries";
|
||||
itlb_asc 4 "Instruction TLB associativity";
|
||||
dtlb_sz 12 "Number of data DTLB entries";
|
||||
dtlb_asc 4 "Data TLB associativity";
|
||||
};
|
||||
regtype amd_cacheinfo23 "AMD cache information" {
|
||||
linesize 8 "line size";
|
||||
lpt 4 "lines per tag";
|
||||
assoc 4 "associativity";
|
||||
size 16 "size in Kb";
|
||||
};
|
||||
register l2_24m ro eax(0x80000006) "AMD L2 TLB info for 2MB/4MB pages"
|
||||
type(amd_tlbinfo23);
|
||||
register l2_4k ro ebx(0x80000006) "AMD L2 TLB info for 4k pages"
|
||||
type(amd_tlbinfo23);
|
||||
register l2_ci ro ecx(0x80000006) "AMD L2 cache info"
|
||||
type(amd_cacheinfo23);
|
||||
register l3_ci ro edx(0x80000006) "AMD L3 cache info"
|
||||
type(amd_cacheinfo23);
|
||||
|
||||
//
|
||||
// EAX=0x80000007 : Advanced Power Management (AMD only)
|
||||
//
|
||||
|
||||
register amd_apm ro edx(0x80000007) "AMD Advanced Power Mgmt" {
|
||||
ts 1 "Temperature sensor";
|
||||
fid 1 "Frequency ID control";
|
||||
vid 1 "Voltage ID control";
|
||||
ttp 1 "THERMTRIP";
|
||||
tm 1 "Hardware thermal control";
|
||||
stc 1 "Software thermal control";
|
||||
Mhz100steps 1 "100MHz multiplier control";
|
||||
hpwstate 1 "Hardware P-State control";
|
||||
tscinvariant 1 "TSC rate invariant";
|
||||
_ 23;
|
||||
};
|
||||
|
||||
//
|
||||
// EAX=0x80000008 : Address size and physical core count
|
||||
//
|
||||
|
||||
register addr_size ro eax(0x80000008) "Address size" {
|
||||
phys 8 "Max physical byte address size in bits";
|
||||
linear 8 "Max linear byte address size in bits";
|
||||
guest 8 "Max guest physical byte address size in bits";
|
||||
_ 8;
|
||||
};
|
||||
// AMD only
|
||||
register core_count ro ecx(0x80000008) "Core count" {
|
||||
nc 8 "Number of CPU cores -1 ";
|
||||
_ 4;
|
||||
apiccoreidsz 4 "APIC core ID size in bits";
|
||||
_ 16;
|
||||
};
|
||||
|
||||
//
|
||||
// EAX=0x8000000A : SVM revision/feature identification (AMD only)
|
||||
//
|
||||
|
||||
register svmrev ro eax(0x8000000A) "Secure Virtual Machine rev." {
|
||||
rev 8 "SVM revision number";
|
||||
_ 24;
|
||||
};
|
||||
register nasid ro ebx(0x8000000A) "# Addr. space identifiers" type(uint32);
|
||||
register svmfeat ro edx(0x8000000A) "SVM features" {
|
||||
np 1 "Nested paging";
|
||||
lbrvirt 1 "LBR virtualization";
|
||||
svml 1 "SVM lock";
|
||||
nrips 1 "NRIP save";
|
||||
_ 5;
|
||||
ssse3sse5dis 1 "SSSE3 and SSE5 opcode set disable";
|
||||
_ 22;
|
||||
};
|
||||
|
||||
//
|
||||
// EAX=0x80000019 : TLB 1GB page identifiers (AMD only)
|
||||
//
|
||||
|
||||
register l1_1G ro eax(0x80000019) "AMD L1 TLB info for 1GB pages"
|
||||
type(amd_tlbinfo23);
|
||||
register l2_1G ro ebx(0x80000019) "AMD L2 TLB info for 1GB pages"
|
||||
type(amd_tlbinfo23);
|
||||
|
||||
//
|
||||
// EAX=0x8000001A : Performance optimization identifiers (AMD only)
|
||||
//
|
||||
|
||||
register opt_id ro eax(0x8000001A) "Perf. optimization identifiers" {
|
||||
fp128 1 "128-bit SSE has full-width execution";
|
||||
movu 1 "MOVU SSE instructions faster than MOVL";
|
||||
_ 30;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
325
devices/cpuid_amd.dev
Normal file
325
devices/cpuid_amd.dev
Normal file
@ -0,0 +1,325 @@
|
||||
/*
|
||||
* Copyright (c) 2015, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* cpuid_amd.dev
|
||||
*
|
||||
* DESCRIPTION: ia32 CPU ID instruction results
|
||||
*
|
||||
* See
|
||||
* AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008
|
||||
*/
|
||||
|
||||
device cpuid_amd lsbfirst () "ia32 / Intel64 CPUID instruction results" {
|
||||
|
||||
/*
|
||||
*============================================================================
|
||||
* Basic Information.
|
||||
*============================================================================
|
||||
*/
|
||||
|
||||
/*
|
||||
* CPUID(0, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype basic lsbfirst (32) "" {
|
||||
max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information";
|
||||
vendor0 32 rw "Vendor string part 1";
|
||||
vendor2 32 rw "Vendor string part 3";
|
||||
vendor1 32 rw "Vendor string part 2";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(1, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
datatype family lsbfirst(32) "family information in eax register" {
|
||||
stepping 4 rw "Processor Stepping ID";
|
||||
model 4 rw "Processor Model";
|
||||
family 4 rw "Processor Family";
|
||||
_ 4 mbz "Reserved";
|
||||
extmodel 4 rw "Extended Model ID";
|
||||
extfamily 8 rw "Extended Family ID";
|
||||
_ 4 mbz "Reserved";
|
||||
};
|
||||
|
||||
datatype miscinfo lsbfirst(32) "info returned in ebx register" {
|
||||
brand_idx 8 rw "Brand index";
|
||||
cflush_sz 8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)";
|
||||
max_log_proc 8 rw "LogicalProcessorCount is the number of cores per processor";
|
||||
init_apicid 8 rw "Initial APIC ID";
|
||||
};
|
||||
|
||||
datatype features lsbfirst(32) "features returned in {ecx, edx}" {
|
||||
/* Feature Information (see Figure 3-6 and Table 3-19) */
|
||||
sse3 1 rw "Streaming SIMD Extensions 3 (SSE3). ";
|
||||
pclmulqdq 1 rw "PCLMULQDQ.";
|
||||
dtes64 1 rw "64-bit DS Area";
|
||||
monitor 1 rw "MONITOR/MWAIT";
|
||||
ds_cpl 1 rw "CPL Qualified Debug Store. ";
|
||||
vmx 1 rw "Virtual Machine Extensions";
|
||||
smx 1 rw "Safer Mode Extensions. ";
|
||||
eist 1 rw "Enhanced Intel SpeedStep(r) technology. ";
|
||||
tm2 1 rw "Thermal Monitor 2";
|
||||
ssse3 1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)";
|
||||
cntx_id 1 rw "L1 Context ID. A";
|
||||
sdbg 1 rw "IA32_DEBUG_INTERFACE MSR ";
|
||||
fma 1 rw "FMA extensions using YMM state.";
|
||||
cmpxchg16b 1 rw "CMPXCHG16B Available";
|
||||
xtpr 1 rw "xTPR Update Control";
|
||||
pdcm 1 rw "Perfmon and Debug Capability";
|
||||
_ 1 mbz "";
|
||||
pcid 1 rw "Process-context identifiers";
|
||||
dca 1 rw "ability to prefetch data from a memory mapped device.";
|
||||
sse4_1 1 rw "supports SSE4.1. ";
|
||||
sse4_2 1 rw "supports SSE4.2. ";
|
||||
x2apic 1 rw "supports x2APIC feature";
|
||||
movbe 1 rw "supports MOVBE instruction";
|
||||
popcnt 1 rw "supports the POPCNT instruction.";
|
||||
tsc_one 1 rw "local APIC timer supports one-shot operation ";
|
||||
aesni 1 rw " AESNI instruction extensions";
|
||||
xsave 1 rw " XSAVE/XRSTOR processor ";
|
||||
osxsave 1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction";
|
||||
avx 1 rw "AVX instruction extensions";
|
||||
f16c 1 rw "16-bit floating-point conversion instructions.";
|
||||
rdrand 1 rw "supports RDRAND instruction.";
|
||||
_ 1 mbz "";
|
||||
|
||||
/* Feature Information (see Figure 3-7 and Table 3-20) */
|
||||
fpu 1 rw "Floating Point Unit On-Chip";
|
||||
vme 1 rw "Virtual 8086 Mode Enhancements";
|
||||
de 1 rw "Debugging Extensions. ";
|
||||
pse 1 rw "Page Size Extension";
|
||||
tsc 1 rw "Time Stamp Counter.";
|
||||
msr 1 rw "Model Specific Registers RDMSR and WRMSR Instructions";
|
||||
pae 1 rw "Physical Address Extension";
|
||||
mce 1 rw "Machine Check Exception. ";
|
||||
cx8 1 rw "CMPXCHG8B Instruction.";
|
||||
apic 1 rw "APIC On-Chip. ";
|
||||
_ 1 mbz "";
|
||||
sep 1 rw "SYSENTER and SYSEXIT Instructions.";
|
||||
mtrr 1 rw "Memory Type Range Registers";
|
||||
pge 1 rw "Page Global Bit";
|
||||
mca 1 rw "Machine Check Architecture.";
|
||||
cmov 1 rw "Conditional Move Instructions";
|
||||
pat 1 rw "Page Attribute Table";
|
||||
pse36 1 rw "36-Bit Page Size Extension";
|
||||
psn 1 rw "Processor Serial Number. ";
|
||||
clfsh 1 rw "CLFLUSH Instruction";
|
||||
_ 1 rw "";
|
||||
ds 1 rw "Debug Store";
|
||||
acpi 1 rw "Thermal Monitor and Software Controlled Clock Facilities";
|
||||
mmx 1 rw "Intel MMX Technology";
|
||||
fxsr 1 rw "FXSAVE and FXRSTOR Instructions";
|
||||
sse 1 rw "SSE1";
|
||||
sse2 1 rw "SSE2";
|
||||
ss 1 rw "Self Snoop";
|
||||
htt 1 rw "Max APIC IDs reserved field is Valid";
|
||||
tm 1 rw "Thermal Monitor";
|
||||
_ 1 mbz "";
|
||||
pbe 1 rw "Pending Break Enable. ";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x80000008, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" {
|
||||
physical 8 rw "Maximum physical byte address size in bits";
|
||||
linear 8 rw "Maximum linear byte address size in bits. ";
|
||||
guest 8 rw " maximum guest physical byte address size in bits";
|
||||
_ 8 mbz "reserved";
|
||||
};
|
||||
|
||||
datatype apicid lsbfirst(32) "APIC ID Size and Core Count (ecx)" {
|
||||
ncores 8 rw "number of physical cores - 1";
|
||||
_ 4 mbz "Reserved";
|
||||
apic_sz 4 rw "APIC ID size";
|
||||
_ 16 mbz "reserved";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x80000005, _) L1 Cache and TLB Identifiers
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype tlb_l1 lsbfirst(32) "" {
|
||||
itlb_sz 8 rw "L2 instruction TLB number of entries for 2/4MB pages ";
|
||||
itlb_assoc 8 rw "L2 instruction TLB associativity for 2/4MB pages ";
|
||||
dtlb_sz 8 rw "L2 data TLB number of entries for 2/4MB pages ";
|
||||
dtlb_assoc 8 rw "L2 data TLB associativity for 2/4MB pages";
|
||||
};
|
||||
|
||||
datatype l1_2m_tlb lsbfirst(32) "Fn8000_0005_EAX L1 Cache and TLB Identifiers" {
|
||||
itlb_sz 8 rw "L2 instruction TLB number of entries for 2/4MB pages ";
|
||||
itlb_assoc 8 rw "L2 instruction TLB associativity for 2/4MB pages ";
|
||||
dtlb_sz 8 rw "L2 data TLB number of entries for 2/4MB pages ";
|
||||
dtlb_assoc 8 rw "L2 data TLB associativity for 2/4MB pages";
|
||||
};
|
||||
|
||||
datatype l1_4k_tlb lsbfirst(32) "Fn8000_0005_EBX L1 Cache and TLB Identifiers" {
|
||||
itlb_sz 8 rw "L2 instruction TLB number of entries for 4 KB pages. ";
|
||||
itlb_assoc 8 rw "L2 instruction TLB associativity for 4 KB pages ";
|
||||
dtlb_sz 8 rw "L2 data TLB number of entries for 4 KB pages ";
|
||||
dtlb_assoc 8 rw "L2 data TLB associativity for 4 KB pages";
|
||||
};
|
||||
|
||||
datatype l1_dcache lsbfirst(32) " Fn8000_0005_ECX L1 Cache and TLB Identifiers" {
|
||||
linesize 8 rw "L1 cache line size in bytes. ";
|
||||
lines_per_tag 8 rw "L1 cache lines per tag. ";
|
||||
assoc 8 rw "L1 cache associativity. See Table 4.";
|
||||
size 8 rw "L1 cache size in KB.";
|
||||
};
|
||||
|
||||
datatype l1_icache lsbfirst(32) "Fn8000_0005_EDX L1 Cache and TLB Identifiers" {
|
||||
linesize 8 rw "L1 cache line size in bytes. ";
|
||||
lines_per_tag 8 rw "L1 cache lines per tag. ";
|
||||
assoc 8 rw "L1 cache associativity. See Table 4.";
|
||||
size 8 rw "L1 cache size in KB.";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x80000006, _) TLB and L2/L3 cache information
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
constants cache_assoc "AMD cache associativity values" {
|
||||
cache_assoc_disabled = 0x0 "";
|
||||
cache_assoc_direct = 0x1 "";
|
||||
cache_assoc_2way = 0x2 "";
|
||||
cache_assoc_4way = 0x4 "";
|
||||
cache_assoc_8way = 0x6 "";
|
||||
cache_assoc_16way = 0x8 "";
|
||||
cache_assoc_32way = 0xa "";
|
||||
cache_assoc_48way = 0xb "";
|
||||
cache_assoc_64way = 0xc "";
|
||||
cache_assoc_96way = 0xd "";
|
||||
cache_assoc_128way = 0xe "";
|
||||
cache_assoc_fully = 0xf "";
|
||||
};
|
||||
|
||||
datatype tlb_l2 lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" {
|
||||
itlb_sz 12 rw "L2 instruction TLB number of entries for 2/4MB pages ";
|
||||
itlb_assoc 4 rw "L2 instruction TLB associativity for 2/4MB pages ";
|
||||
dtlb_sz 12 rw "L2 data TLB number of entries for 2/4MB pages ";
|
||||
dtlb_assoc 4 rw "L2 data TLB associativity for 2/4MB pages";
|
||||
};
|
||||
|
||||
datatype l2_2m_tlb lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" {
|
||||
itlb_sz 12 rw "L2 instruction TLB number of entries for 2/4MB pages ";
|
||||
itlb_assoc 4 rw "L2 instruction TLB associativity for 2/4MB pages ";
|
||||
dtlb_sz 12 rw "L2 data TLB number of entries for 2/4MB pages ";
|
||||
dtlb_assoc 4 rw "L2 data TLB associativity for 2/4MB pages";
|
||||
};
|
||||
|
||||
datatype l2_4k_tlb lsbfirst(32) " Fn8000_0006_EBX L2 TLB Identifiers" {
|
||||
itlb_sz 12 rw "L2 instruction TLB number of entries for 4 KB pages. ";
|
||||
itlb_assoc 4 rw "L2 instruction TLB associativity for 4 KB pages ";
|
||||
dtlb_sz 12 rw "L2 data TLB number of entries for 4 KB pages ";
|
||||
dtlb_assoc 4 rw "L2 data TLB associativity for 4 KB pages";
|
||||
};
|
||||
|
||||
datatype l2_cache lsbfirst(32) "Fn8000_0006_ECX L2 Cache Identifiers" {
|
||||
linesize 8 rw "L2 cache line size in bytes. ";
|
||||
lines_per_tag 4 rw "L2 cache lines per tag. ";
|
||||
assoc 4 rw "L2 cache associativity. See Table 4.";
|
||||
size 16 rw "L2 cache size in KB.";
|
||||
};
|
||||
|
||||
|
||||
datatype l3_cache lsbfirst(32) "Fn8000_0006_EDX L3 Cache Identifiers" {
|
||||
linesize 8 rw "L3 cache line size in bytes. ";
|
||||
lines_per_tag 4 rw "L3 cache lines per tag. ";
|
||||
assoc 4 rw "L3 cache associativity. See Table 4.";
|
||||
_ 2 mbz "Reserved";
|
||||
size 14 rw "Specifies the L3 cache size in 512kb blocks";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x80000019, _) TLB for 1G Pages
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype tlb_1g_l1 lsbfirst(32) "TLB 1GB Page Identifiers eax" {
|
||||
itlb_sz 12 "L1 instruction TLB number of entries for 1 GB pages";
|
||||
itlb_assoc 4 "L1 instruction TLB associativity for 1 GB pages. See Table 4";
|
||||
dtlb_sz 12 "L1 data TLB number of entries for 1 GB pages";
|
||||
dtlb_assoc 4 "L1 data TLB associativity for 1 GB pages. See Table 4.";
|
||||
};
|
||||
|
||||
datatype tlb_1g_l2 lsbfirst(32) "TLB 1GB Page Identifiers ebx" {
|
||||
itlb_sz 12 "L2 instruction TLB number of entries for 1 GB pages";
|
||||
itlb_assoc 4 "L2 instruction TLB associativity for 1 GB pages. See Table 4";
|
||||
dtlb_sz 12 "L2 data TLB number of entries for 1 GB pages";
|
||||
dtlb_assoc 4 "L2 data TLB associativity for 1 GB pages. See Table 4.";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x8000001D, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
constants cache_type "AMD Cache Type values" {
|
||||
cache_type_null = 0x0 "No more caches";
|
||||
cache_type_data = 0x1 "data cache";
|
||||
cache_type_instr = 0x2 "Instruction Cache";
|
||||
cache_type_unified = 0x3 "Unified Cache";
|
||||
};
|
||||
|
||||
/* EAX */
|
||||
datatype cache_info_eax lsbfirst (32) "" {
|
||||
ctype 5 "Cache Type Field";
|
||||
level 3 "Cache Level (starts at 1)";
|
||||
selfinit 1 "Self Initializing cache level (does not need SW initialization)";
|
||||
fullyassoc 1 "Fully Associative cache";
|
||||
_ 4 "Reserved";
|
||||
num_sharing 12 "number of cores sharing cache - 1";
|
||||
_ 6 "";
|
||||
};
|
||||
|
||||
datatype cache_info_ebx lsbfirst (32) "" {
|
||||
cachelinesize 12 "cache line size in bytes - 1";
|
||||
partitions 10 "cache physical line partitions - 1";
|
||||
assoc 10 "cache number of ways - 1";
|
||||
};
|
||||
|
||||
datatype cache_info_ecx lsbfirst (32) "" {
|
||||
num_sets 32 "The number of Sets - 1";
|
||||
};
|
||||
|
||||
datatype cache_info_edx lsbfirst (32) "" {
|
||||
wb_inv 1 "Write-Back Invalidate/Invalidate";
|
||||
inclusive 1 "Cache Inclusiveness";
|
||||
_ 30 "reserved";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x8000001E, _) topology extensions
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype ext_apic lsbfirst (32) "register eax" {
|
||||
extended_apicid 32 "extended APIC ID";
|
||||
};
|
||||
|
||||
datatype cuid lsbfirst (32) "Fn8000_001E_EBX Compute Unit Identifiers" {
|
||||
cuid 8 "compute unit id";
|
||||
ncores 2 "Number of cores per compute unit - 1";
|
||||
_ 22 "Reserved";
|
||||
};
|
||||
|
||||
datatype nid lsbfirst (32) "Fn8000_001E_ECX Node Identifiers" {
|
||||
nodeid 8 "Specifies the node ID";
|
||||
nnodeds 3 "Number of nodes per processor - 1";
|
||||
_ 21 "Reserved";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
86
devices/cpuid_arm.dev
Normal file
86
devices/cpuid_arm.dev
Normal file
@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (c) 2016, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/* ARM CPUID register formats */
|
||||
|
||||
device cpuid_arm msbfirst () "ARMv7+ CPUID fields" {
|
||||
constants ftr_supp "Feature support" {
|
||||
ftr_ni = 0b0000 "Not implemented";
|
||||
ftr_i = 0b0001 "Implemented";
|
||||
};
|
||||
|
||||
constants jaz_supp "Jazelle extension support" {
|
||||
jaz_ni = 0b0000 "Not implemented";
|
||||
jaz_it = 0b0001 "Implemented, trivial";
|
||||
jaz_i = 0b0010 "Implemented, full";
|
||||
};
|
||||
|
||||
constants thm_supp "ThumbEE instruction set support" {
|
||||
thm_ni = 0b0000 "Not implemented";
|
||||
thm_i1 = 0b0001 "Thumb 1";
|
||||
thm_i2 = 0b0011 "Thumb 2";
|
||||
};
|
||||
|
||||
datatype id_pfr0 msbfirst(32) "Processor Feature Register 0" {
|
||||
_ 16 rsvd "Reserved";
|
||||
state3 4 rw type(ftr_supp) "ThumbEE instruction set support";
|
||||
state2 4 rw type(jaz_supp) "Jazelle extension support";
|
||||
state1 4 rw type(thm_supp) "Thumb instruction set support";
|
||||
state0 4 rw type(ftr_supp) "ARM instruction set support";
|
||||
};
|
||||
|
||||
constants mpr_supp "M profile" {
|
||||
mpr_ni = 0b0000 "Not supported";
|
||||
mpr_i = 0b0010 "Supported";
|
||||
};
|
||||
|
||||
constants sec_supp "M profile" {
|
||||
sec_ni = 0b0000 "Not implemented";
|
||||
sec_i = 0b0001 "Implemented";
|
||||
sec_ir = 0b0010 "Implemented, with NSACR.RFR";
|
||||
};
|
||||
|
||||
datatype id_pfr1 msbfirst(32) "Processor Feature Register 1" {
|
||||
_ 12 rsvd "Reserved";
|
||||
generic_timer 4 rw type(ftr_supp) "Generic timer extension";
|
||||
virtualisation 4 rw type(ftr_supp) "Virtualisation extensions";
|
||||
m_profile 4 rw type(mpr_supp) "M profile";
|
||||
security 4 rw type(sec_supp) "Security extensions";
|
||||
prog_model 4 rw type(ftr_supp) "Programmers' model";
|
||||
};
|
||||
|
||||
constants midr_impl "Implementer code" {
|
||||
impl_arm = 0x41 "ARM";
|
||||
impl_dec = 0x44 "DEC";
|
||||
impl_motorola = 0x4d "Motorola/Freescale";
|
||||
impl_qualcomm = 0x51 "Qualcomm";
|
||||
impl_marvell = 0x56 "Marvell";
|
||||
impl_intel = 0x69 "Intel";
|
||||
};
|
||||
|
||||
constants arm_part "ARM part number" {
|
||||
part_a5 = 0xc05 "Cortex-A5";
|
||||
part_a7 = 0xc07 "Cortex-A7";
|
||||
part_a8 = 0xc08 "Cortex-A8";
|
||||
part_a9 = 0xc09 "Cortex-A9";
|
||||
part_a15 = 0xc0f "Cortex-A15";
|
||||
part_a17 = 0xc0e "Cortex-A17";
|
||||
part_a53 = 0xd03 "Cortex-A53";
|
||||
part_a57 = 0xd07 "Cortex-A57";
|
||||
part_a72 = 0xd08 "Cortex-A72";
|
||||
part_a73 = 0xd09 "Cortex-A73";
|
||||
};
|
||||
|
||||
datatype midr msbfirst(32) "Main ID Register" {
|
||||
implementer 8 rw type(midr_impl) "Implementer";
|
||||
variant 4 rw "Variant";
|
||||
architecture 4 rw "Architecture";
|
||||
part 12 rw "Primary part number";
|
||||
revision 4 rw "Revision";
|
||||
};
|
||||
};
|
||||
277
devices/cpuid_intel.dev
Normal file
277
devices/cpuid_intel.dev
Normal file
@ -0,0 +1,277 @@
|
||||
/*
|
||||
* Copyright (c) 2015, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* cpuid_intel.dev
|
||||
*
|
||||
* DESCRIPTION: ia32 CPU ID instruction results
|
||||
*
|
||||
* See:
|
||||
* Intel Architecture Manual, Volume 2A, pp. 3-163 - ff., April 2015
|
||||
* Table 3-17. Information Returned by CPUID Instruction
|
||||
*/
|
||||
|
||||
device cpuid_intel lsbfirst () "ia32 / Intel64 CPUID instruction results" {
|
||||
|
||||
/*
|
||||
*============================================================================
|
||||
* Basic Information.
|
||||
*============================================================================
|
||||
*/
|
||||
|
||||
/*
|
||||
* CPUID(0, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype basic0 lsbfirst (32) "" {
|
||||
max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information";
|
||||
vendor0 32 rw "Vendor string part 1";
|
||||
vendor2 32 rw "Vendor string part 3";
|
||||
vendor1 32 rw "Vendor string part 2";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(1, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
constants proc_type width(2) "" {
|
||||
original = 0x00 "Original OEM Processor";
|
||||
overdrive= 0x01 "Intel OverDrive(r) Processor";
|
||||
dual = 0x02 "Dual processor (not applicable to Intel486 processors)";
|
||||
reserved = 0x03 "Intel reserved";
|
||||
};
|
||||
|
||||
datatype family lsbfirst(32) "" {
|
||||
/* Version Information: Type, Family, Model, and Stepping ID (see Figure 3-5) */
|
||||
|
||||
stepping 4 rw "Processor Stepping ID";
|
||||
model 4 rw "Processor Model";
|
||||
family 4 rw "Processor Family";
|
||||
proctype 2 rw "Processor Type";
|
||||
_ 2 mbz "Reserved";
|
||||
extmodel 4 rw "Extended Model ID";
|
||||
extfamily 8 rw "Extended Family ID";
|
||||
_ 4 mbz "Reserved";
|
||||
};
|
||||
|
||||
/* EAX=1 */
|
||||
|
||||
datatype miscinfo lsbfirst(32) "" {
|
||||
|
||||
brand_idx 8 rw "Brand index";
|
||||
cflush_sz 8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)";
|
||||
max_log_proc 8 rw "Maximum number of addressable IDs for logical processors";
|
||||
/*in this physical package.
|
||||
The nearest power-of-2 integer that is not smaller than
|
||||
EBX[23:16] is the number of unique initial APIC IDs
|
||||
reserved for addressing different logical processors in a
|
||||
physical package. */
|
||||
init_apicid 8 rw "Initial APIC ID";
|
||||
};
|
||||
|
||||
datatype features lsbfirst(32) "" {
|
||||
/* Feature Information (see Figure 3-6 and Table 3-19) */
|
||||
sse3 1 rw "Streaming SIMD Extensions 3 (SSE3). ";
|
||||
pclmulqdq 1 rw "PCLMULQDQ.";
|
||||
dtes64 1 rw "64-bit DS Area";
|
||||
monitor 1 rw "MONITOR/MWAIT";
|
||||
ds_cpl 1 rw "CPL Qualified Debug Store. ";
|
||||
vmx 1 rw "Virtual Machine Extensions";
|
||||
smx 1 rw "Safer Mode Extensions. ";
|
||||
eist 1 rw "Enhanced Intel SpeedStep(r) technology. ";
|
||||
tm2 1 rw "Thermal Monitor 2";
|
||||
ssse3 1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)";
|
||||
cntx_id 1 rw "L1 Context ID. A";
|
||||
sdbg 1 rw "IA32_DEBUG_INTERFACE MSR ";
|
||||
fma 1 rw "FMA extensions using YMM state.";
|
||||
cmpxchg16b 1 rw "CMPXCHG16B Available";
|
||||
xtpr 1 rw "xTPR Update Control";
|
||||
pdcm 1 rw "Perfmon and Debug Capability";
|
||||
_ 1 mbz "";
|
||||
pcid 1 rw "Process-context identifiers";
|
||||
dca 1 rw "ability to prefetch data from a memory mapped device.";
|
||||
sse4_1 1 rw "supports SSE4.1. ";
|
||||
sse4_2 1 rw "supports SSE4.2. ";
|
||||
x2apic 1 rw "supports x2APIC feature";
|
||||
movbe 1 rw "supports MOVBE instruction";
|
||||
popcnt 1 rw "supports the POPCNT instruction.";
|
||||
tsc_one 1 rw "local APIC timer supports one-shot operation ";
|
||||
aesni 1 rw " AESNI instruction extensions";
|
||||
xsave 1 rw " XSAVE/XRSTOR processor ";
|
||||
osxsave 1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction";
|
||||
avx 1 rw "AVX instruction extensions";
|
||||
f16c 1 rw "16-bit floating-point conversion instructions.";
|
||||
rdrand 1 rw "supports RDRAND instruction.";
|
||||
_ 1 mbz "";
|
||||
|
||||
/* Feature Information (see Figure 3-7 and Table 3-20) */
|
||||
fpu 1 rw "Floating Point Unit On-Chip";
|
||||
vme 1 rw "Virtual 8086 Mode Enhancements";
|
||||
de 1 rw "Debugging Extensions. ";
|
||||
pse 1 rw "Page Size Extension";
|
||||
tsc 1 rw "Time Stamp Counter.";
|
||||
msr 1 rw "Model Specific Registers RDMSR and WRMSR Instructions";
|
||||
pae 1 rw "Physical Address Extension";
|
||||
mce 1 rw "Machine Check Exception. ";
|
||||
cx8 1 rw "CMPXCHG8B Instruction.";
|
||||
apic 1 rw "APIC On-Chip. ";
|
||||
_ 1 mbz "";
|
||||
sep 1 rw "SYSENTER and SYSEXIT Instructions.";
|
||||
mtrr 1 rw "Memory Type Range Registers";
|
||||
pge 1 rw "Page Global Bit";
|
||||
mca 1 rw "Machine Check Architecture.";
|
||||
cmov 1 rw "Conditional Move Instructions";
|
||||
pat 1 rw "Page Attribute Table";
|
||||
pse36 1 rw "36-Bit Page Size Extension";
|
||||
psn 1 rw "Processor Serial Number. ";
|
||||
clfsh 1 rw "CLFLUSH Instruction";
|
||||
_ 1 rw "";
|
||||
ds 1 rw "Debug Store";
|
||||
acpi 1 rw "Thermal Monitor and Software Controlled Clock Facilities";
|
||||
mmx 1 rw "Intel MMX Technology";
|
||||
fxsr 1 rw "FXSAVE and FXRSTOR Instructions";
|
||||
sse 1 rw "SSE1";
|
||||
sse2 1 rw "SSE2";
|
||||
ss 1 rw "Self Snoop";
|
||||
htt 1 rw "Max APIC IDs reserved field is Valid";
|
||||
tm 1 rw "Thermal Monitor";
|
||||
_ 1 mbz "";
|
||||
pbe 1 rw "Pending Break Enable. ";
|
||||
};
|
||||
|
||||
|
||||
/* EAX=2 */
|
||||
datatype cache_info lsbfirst (32) "" {
|
||||
d0 8 "ignored, always 0x01";
|
||||
d1 8 "Descriptor 01";
|
||||
d2 8 "Descriptor 02";
|
||||
d3 7 "Descriptor 03";
|
||||
v0 1 "Contains valid descriptors";
|
||||
};
|
||||
|
||||
/* EAX=3 */
|
||||
/* not used post P3 */
|
||||
|
||||
/*
|
||||
*---------------------------------------------------------------------
|
||||
* Deterministic Cache Parameters EAX=4, ECX=idx
|
||||
*---------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
constants cache_type "Intel Cache Type values" {
|
||||
cache_type_null = 0x0 "No more caches";
|
||||
cache_type_data = 0x1 "data cache";
|
||||
cache_type_instr = 0x2 "Instruction Cache";
|
||||
cache_type_unified = 0x3 "Unified Cache";
|
||||
};
|
||||
|
||||
/* EAX */
|
||||
datatype cache_info_basic lsbfirst (32) "" {
|
||||
ctype 5 "Cache Type Field";
|
||||
level 3 "Cache Level (starts at 1)";
|
||||
selfinit 1 "Self Initializing cache level (does not need SW initialization)";
|
||||
fullyassoc 1 "Fully Associative cache";
|
||||
_ 4 "Reserved";
|
||||
maxlog 12 "Maximum number of addressable IDs for logical processors sharing this cache - 1";
|
||||
maxphys 6 "Maximum number of addressable IDs for processor cores in the physical package - 1";
|
||||
};
|
||||
|
||||
datatype cache_info_ebx lsbfirst (32) "" {
|
||||
coherency 12 "System Coherency Line Size - 1";
|
||||
partitions 10 "Physical Line partitions - 1";
|
||||
assoc 10 "Ways of associativity - 1";
|
||||
};
|
||||
|
||||
datatype cache_info_ecx lsbfirst (32) "" {
|
||||
num_sets 32 "The number of Sets - 1";
|
||||
};
|
||||
|
||||
datatype cache_info_edx lsbfirst (32) "" {
|
||||
wb_inv 1 "Write-Back Invalidate/Invalidate";
|
||||
inclusive 1 "Cache Inclusiveness";
|
||||
cpx_idx 1 "Complex Cache Indexing";
|
||||
_ 29 "";
|
||||
};
|
||||
|
||||
/*
|
||||
* CPUID(0x16, _) Processor Frequency Information Leaf
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype frequency lsbfirst (32) "" {
|
||||
mhz 16 "Processor frequency in mhz";
|
||||
_ 16 "Reserved";
|
||||
};
|
||||
|
||||
/*
|
||||
*---------------------------------------------------------------------
|
||||
* Extended Information
|
||||
*---------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* extended topology enumaration leaf, eax = 0xb */
|
||||
datatype topology_eax lsbfirst (32) "" {
|
||||
x2apic_shift 5 "";
|
||||
_ 27 "";
|
||||
};
|
||||
datatype topology_ebx lsbfirst (32) "" {
|
||||
logical_proc 16 "";
|
||||
_ 16 "";
|
||||
};
|
||||
datatype topology_ecx lsbfirst (32) "" {
|
||||
level_number 8 "";
|
||||
level_type 8 "";
|
||||
_ 16 "";
|
||||
};
|
||||
datatype topology_edx lsbfirst (32) "" {
|
||||
x2apic 32 "";
|
||||
};
|
||||
|
||||
constants topology_level "Intel Cache Type values" {
|
||||
topology_level_invalid = 0x0 "Invalid";
|
||||
topology_level_smt = 0x1 "SMT";
|
||||
topology_level_core = 0x2 "Core";
|
||||
topology_level_package = 0x3 "Package";
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPUID(0x80000001, _) Extended Function CPUID Informatio
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype features_ext_edx "" {
|
||||
_ 11 "";
|
||||
syscall 1 "SYSCALL/SYSRET available in 64-bit mode";
|
||||
_ 8 "";
|
||||
nx 1 "Execute Disable Bit available";
|
||||
_ 5 "";
|
||||
page1G 1 "1-GByte pages are available if 1";
|
||||
rdtscp 1 "RDTSCP and IA32_TSC_AUX are available if 1";
|
||||
_ 1 "";
|
||||
lm 1 "Intel 64 Architecture available if 1";
|
||||
_ 2 "";
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* CPUID(0x80000008, _)
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" {
|
||||
physical 8 rw "Maximum physical byte address size in bits";
|
||||
linear 8 rw "Maximum linear byte address size in bits. ";
|
||||
_ 16 mbz "reserved";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
1625
devices/e1000.dev
Normal file
1625
devices/e1000.dev
Normal file
File diff suppressed because it is too large
Load Diff
2557
devices/e10k.dev
Normal file
2557
devices/e10k.dev
Normal file
File diff suppressed because it is too large
Load Diff
244
devices/e10k_q.dev
Normal file
244
devices/e10k_q.dev
Normal file
@ -0,0 +1,244 @@
|
||||
/*
|
||||
* Copyright (c) 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* e10k_q.dev
|
||||
*
|
||||
* DESCRIPTION: Intel 82599 10 GbE Controller Queues
|
||||
*
|
||||
* Numbers in comments refer to the Intel 82599 10 GbE Controller Datasheet
|
||||
* 322429-007, Revison 2.6, December 2010
|
||||
*/
|
||||
|
||||
device e10k_q lsbfirst () "Intel 82599 10 GbE Controller Queues" {
|
||||
|
||||
/************************************
|
||||
* 7.1.5 - 7.1.6 Recieve Descriptors
|
||||
***********************************/
|
||||
|
||||
// 7.1.5
|
||||
datatype rdesc_legacy "Legacy Receive Descriptor" {
|
||||
buffer 64 "Buffer Address";
|
||||
length 16 "Length Field";
|
||||
checksum 16 "Fragment Checksum";
|
||||
|
||||
// Recieve Status
|
||||
dd 1 "Descriptor Done";
|
||||
eop 1 "End of Packet";
|
||||
_ 1 rsvd;
|
||||
vp 1 "VLAN Packet";
|
||||
udpcs 1 "UDP Checksum";
|
||||
l4cs 1 "L4 Checksum";
|
||||
ipcs 1 "Ipv4 Checksum";
|
||||
pif 1 "Non Unicast Address";
|
||||
|
||||
// Error Field
|
||||
rxe 1 "MAC error";
|
||||
_ 5 rsvd;
|
||||
tcpe 1 "TCP/UDP Checksum Error";
|
||||
ipe 1 "Ipv4 Checksum Error";
|
||||
|
||||
vlan_tag 16 "VLAN Tag";
|
||||
};
|
||||
|
||||
// 7.1.6.1
|
||||
datatype rdesc_adv_rd "Advanced Receive Descriptor (read)" {
|
||||
buffer 64 "Packet Buffer Address";
|
||||
hdr_buffer 64 "Header Buffer Address";
|
||||
};
|
||||
|
||||
// 7.1.6.2
|
||||
datatype rdesc_adv_wb "Advanced Receive Descriptor (write-back)" {
|
||||
rss_type 4 "RSS type";
|
||||
|
||||
// Packet type
|
||||
pt_ipv4 1 "IPv4 header present";
|
||||
pt_ipv4e 1 "IPv4 with extensions";
|
||||
pt_ipv6 1 "IPv6 header present";
|
||||
pt_ipv6e 1 "IPv6 with extensions";
|
||||
pt_tcp 1 "TCP header present";
|
||||
pt_udp 1 "UDP header present";
|
||||
pt_sctp 1 "SCTP header";
|
||||
pt_nfs 1 "NFS header";
|
||||
pt_isesp 1 "IPSec ESP - IPSec encapsulation";
|
||||
pt_isah 1 "IPSec AH - IPSec encapsulation";
|
||||
pt_linksec 1 "LinkSec encapsulation";
|
||||
pt_l2packet 1 "L2 packet";
|
||||
_ 1;
|
||||
|
||||
rsccnt 4 "RSC Packet Count";
|
||||
hdr_len 10 "Packet header length";
|
||||
sph 1 "Split Header";
|
||||
param 32 "RSS Hash/Fragement CS/Fdir Flt ID/...";
|
||||
|
||||
// Extended status
|
||||
dd 1 "Descriptor Done Status";
|
||||
eop 1 "End of Packet";
|
||||
flm 1 "Flow director filter match";
|
||||
vp 1 "VLAN Packet";
|
||||
udpcs 1 "UDP Checksum";
|
||||
l4i 1 "L4 Integrity";
|
||||
ipcs 1 "IPv4 Checksum";
|
||||
pif 1 "Non Unicast Address";
|
||||
_ 1;
|
||||
vext 1 "Outer-VLAN found in double VLAN packet";
|
||||
udpv 1 "UDP Checksum Valid";
|
||||
llint 1 "Low Latency Interrupt";
|
||||
_ 4;
|
||||
ts 1 "Time Stamp";
|
||||
secp 1 "Security Processing bit";
|
||||
lb 1 "Loopback status indication";
|
||||
_ 1;
|
||||
|
||||
// Extended error
|
||||
fdirerr_len 3 "FDIRErr/FCERR";
|
||||
hbo 1 "Header Buffer Overflow";
|
||||
_ 3;
|
||||
secerr 2 "Security error indication (LinkSec, IPSec)";
|
||||
rxe 1 "MAC error";
|
||||
l4e 1 "L4 integrity error";
|
||||
ipe 1 "IPv4 checksum error";
|
||||
|
||||
pkt_len 16 "Number of bytes posted to packet buffer";
|
||||
vlan_tag 16 "VLAN Tag";
|
||||
};
|
||||
|
||||
datatype rdesc_adv_wb_nl "Advanced Receive Descriptor (write-back) for non-last" {
|
||||
_ 17;
|
||||
rsccnt 4 "RSC Packet Count";
|
||||
_ 43;
|
||||
|
||||
// Extended status
|
||||
dd 1 "Descriptor Done Status";
|
||||
eop 1 "End of Packet";
|
||||
_ 2;
|
||||
nextp 16 "Next Descriptor Pointer";
|
||||
|
||||
// Extended error
|
||||
_ 12;
|
||||
|
||||
pkt_len 16 "Number of bytes posted to packet buffer";
|
||||
_ 16;
|
||||
};
|
||||
|
||||
/************************************
|
||||
* 7.2.3 Transmit Descriptors
|
||||
***********************************/
|
||||
|
||||
// 7.2.3.2.2
|
||||
datatype tdesc_legacy "Legacy Transmit Descriptor Format" {
|
||||
buffer 64 "Buffer Address";
|
||||
length 16 "Length";
|
||||
cso 8 "Checksum Offset";
|
||||
|
||||
// Command Byte
|
||||
eop 1 "End of Packet";
|
||||
ifcs 1 "Insert FCS";
|
||||
ic 1 "Insert Checksum";
|
||||
rs 1 "Report Status";
|
||||
_ 1 rsvd;
|
||||
dext 1 "Descriptor extension";
|
||||
vle 1 "VLAN Packet Enable";
|
||||
_ 1 rsvd;
|
||||
|
||||
// Status
|
||||
dd 1 " Descriptor Done Status";
|
||||
_ 3 rsvd;
|
||||
|
||||
_ 4 rsvd;
|
||||
css 8 "Checksum Start";
|
||||
vlan 16 "VLAN Field";
|
||||
};
|
||||
|
||||
// 7.2.3.2.3
|
||||
constants l4_type "L4 Packet type" {
|
||||
udp = 0b00 "UDP";
|
||||
tcp = 0b01 "TCP";
|
||||
sctp = 0b10 "SCTP";
|
||||
};
|
||||
datatype tdesc_adv_ctx "Advanced Transmit Context Descriptor (write-back)" {
|
||||
iplen 9 "IP header length";
|
||||
maclen 7 "MAC header length";
|
||||
vlan 16 "VLAN tag to be inserted";
|
||||
ipsec_saidx 10 "Ipsec SA IDX";
|
||||
fcoef 6 "FCoEF";
|
||||
_ 16;
|
||||
ips_esp_len 9 "Size of ESP trailer and ESP ICV (ipsec)";
|
||||
|
||||
// TUCMD
|
||||
snap 1 "SNAP indication";
|
||||
ipv4 1 "IPv4 Packet type (1=ipv4, 0=ipv6)";
|
||||
l4t 2 type(l4_type) "L4 Packet type";
|
||||
ipsec_type 1 "IPSEC_TYPE";
|
||||
encryption 1 "ESP encryption offload";
|
||||
fcoe 1 "FCoE";
|
||||
_ 4;
|
||||
|
||||
dtyp 4 type(tdesc_dtyp) "Descriptor type: adv_ctx";
|
||||
_ 5;
|
||||
dext 1 "Descriptor Extension (must be 1)";
|
||||
bcntlen 6 "Must be 0x3F for rate limited queues";
|
||||
idx 1 "Index into the hardware context table";
|
||||
_ 3;
|
||||
l4len 8 "L4 header length";
|
||||
mss 16 "Maximum Segment Size";
|
||||
};
|
||||
|
||||
// 7.2.3.2.4
|
||||
datatype tdesc_adv_rd "Advanced Transmit Data Descriptor (read)" {
|
||||
buffer 64 "Buffer Address";
|
||||
dtalen 16 "Bytes to be fetched for this descriptor";
|
||||
|
||||
_ 2;
|
||||
mac_ilsec 1 "Apply LinkSec on packet";
|
||||
mac_1588 1 "IEEE1588 time stamp packet";
|
||||
dtyp 4 type(tdesc_dtyp) "Descriptor type: adv_data";
|
||||
|
||||
// DCMD
|
||||
eop 1 "End of Packet";
|
||||
ifcs 1 "Insert FCS";
|
||||
_ 1;
|
||||
rs 1 "Report Status";
|
||||
_ 1;
|
||||
dext 1 "Descriptor Extension (must be 1)";
|
||||
vle 1 "VLAN Packet Enable";
|
||||
tse 1 "Transmit Segmentation Enable";
|
||||
|
||||
// Status
|
||||
dd 1 "Descriptor Done";
|
||||
_ 3;
|
||||
|
||||
idx 3 "Index into the hardware context table";
|
||||
cc 1 "Check Context bit";
|
||||
|
||||
// POPTS
|
||||
ixsm 1 "Insert IP Checksum";
|
||||
txsm 1 "Insert TCP/UDP Checksum";
|
||||
ipsec 1 "Ipsec offload request";
|
||||
_ 3;
|
||||
|
||||
paylen 18 "Size in bytes of whole packet (only first descriptor)";
|
||||
};
|
||||
|
||||
datatype tdesc_adv_wb "Advanced Transmit Data Descriptor (write-back)" {
|
||||
_ 64;
|
||||
_ 32;
|
||||
|
||||
// Status
|
||||
dd 1;
|
||||
_ 3;
|
||||
|
||||
_ 28;
|
||||
};
|
||||
|
||||
constants tdesc_dtyp "TX Descriptor Type" {
|
||||
adv_ctx = 0b0010 "Advanced context descriptor";
|
||||
adv_data = 0b0011 "Advanced data descriptor";
|
||||
};
|
||||
|
||||
};
|
||||
430
devices/e10k_vf.dev
Normal file
430
devices/e10k_vf.dev
Normal file
@ -0,0 +1,430 @@
|
||||
/*
|
||||
* Copyright (c) 2013, University of Washington. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* e10k_vf.dev
|
||||
*
|
||||
* DESCRIPTION: Intel 82599 10 GbE Controller Virtual Function
|
||||
*
|
||||
* Numbers in comments refer to the Intel 82599 10 GbE Controller Datasheet,
|
||||
* Revison 2.76, September 2012
|
||||
*/
|
||||
|
||||
device e10k_vf lsbfirst ( addr base ) "Intel 82599 10 GbE Controller Virtual Function" {
|
||||
|
||||
/************************************
|
||||
* 8.3.5.1 General control registers--VF
|
||||
***********************************/
|
||||
|
||||
// 8.3.5.1.1
|
||||
register vfctrl wo addr(base, 0x00000) "VF control" {
|
||||
_ 26 rsvd;
|
||||
rst 1 "Device reset";
|
||||
_ 5 rsvd;
|
||||
};
|
||||
|
||||
constants lanid "LAN ID" {
|
||||
lan_0 = 0b00 "LAN 0";
|
||||
lan_1 = 0b01 "LAN 1";
|
||||
lan_not_u1 = 0b10 "LAN ID not used";
|
||||
lan_not_u2 = 0b11 "LAN ID not used";
|
||||
};
|
||||
|
||||
// 8.3.5.1.2
|
||||
register vfstatus ro addr(base, 0x00008) "VF status" {
|
||||
_ 2;
|
||||
lan_id 2 type(lanid) "LAN ID";
|
||||
_ 3;
|
||||
link_up 1 "Linkup Status Indication";
|
||||
_ 2;
|
||||
num_vfs 8 "Num VFs";
|
||||
iov_active 1 "IOV Active";
|
||||
pcie_mes 1 "PCIe Master Enable Status";
|
||||
_ 12;
|
||||
};
|
||||
|
||||
// 8.3.5.1.3
|
||||
constants mac_lnkmode "MAC link mode status" {
|
||||
lms_1g = 0b00 "1 GbE";
|
||||
lms_10g_par = 0b01 "10 GbE parallel";
|
||||
lms_10g_ser = 0b10 "10 GbE serial";
|
||||
lms_aneg = 0b11 "auto-negotiation";
|
||||
};
|
||||
|
||||
constants link_speed "MAC link speed status" {
|
||||
ls_100m = 0b01 "100 Mb/s";
|
||||
ls_1g = 0b10 "1 GbE";
|
||||
ls_10g = 0b11 "10 GbE";
|
||||
};
|
||||
|
||||
register vflinks ro addr(base, 0x00010) "VF Link Status Register" {
|
||||
kxsig_det 1 "A signal is present";
|
||||
fecsig_det 1 "FEC reports signal detected";
|
||||
fecblk_lck 1 "FEC reached block lock";
|
||||
krhberr 1 "10GbE serial KR_PCS high error rate";
|
||||
krpcsbl 1 "10 GbE serial PCS block lock";
|
||||
kxr_annprcv 1 "KX/KX4/KR AN Next Page Received";
|
||||
kxr_anprcv 1 "KX/KX4/KR Backplane Auto Negotiation Page Received";
|
||||
lnk_stat 1 "Link Up and there was no link down from last time read";
|
||||
kx4sig_det 4 "Signal Detect of 10 GbE Parallel (KX4, CX4 or XAUI) (1bit per lane)";
|
||||
krsig_det 1 "Signal Detect of 10 GbE serial (KR or SFI)";
|
||||
l10g_syncst 4 "10G Parallel lane sync status (1bit per lane)";
|
||||
l10g_algst 1 "10 GbE align_status";
|
||||
l1g_syncst 1 "1G sync_status";
|
||||
kxr_anrxid 1 "KX/KX4/KR Backplane Auto Negotiation Rx Idle";
|
||||
l1g_anen 1 "PCS_1 GbE auto-negotiation is enabled";
|
||||
l1g_lnken 1 "1 GbE PCS enabled for 1 GbE and SGMII operation";
|
||||
l10g_lnken 1 "XGXS Enabled for 10 GbE operation";
|
||||
fec_en 1 "Status of forwarderrorcorrection in 10 GbE serial link";
|
||||
l10g_seren 1 "Status of 10 GbE serial PCS (KR PCS) for KR or SFI operation";
|
||||
sgmii_en 1 "Status of SGMII operation";
|
||||
mlink_mode 2 type (mac_lnkmode) "MAC link mode status";
|
||||
lnk_speed 2 type (link_speed) "MAC link speed status";
|
||||
lnk_up 1 "Link is up";
|
||||
kxr_ancomp 1 "KX/KX4/KR backplane auto-negotiation has completed successfully";
|
||||
};
|
||||
|
||||
// NYI:
|
||||
// 8.3.5.1.4 VF Free Running Timer (VFFRTIMER)
|
||||
// 8.3.5.1.5 VF Mailbox (VFMailbox)
|
||||
// 8.3.5.1.6 VF Mailbox Memory (VFMBMEM)
|
||||
|
||||
// 8.3.5.1.7
|
||||
register vfrxmemwrap ro addr(base, 0x03190) "VF Rx Packet Buffer Flush Detect" {
|
||||
tc0_wrap 3 "Packet Buffer 0 Wrap Around Counter";
|
||||
tc0_empty 1 "Packet Buffer 0 Empty";
|
||||
tc1_wrap 3 "Packet Buffer 1 Wrap Around Counter";
|
||||
tc1_empty 1 "Packet Buffer 1 Empty";
|
||||
tc2_wrap 3 "Packet Buffer 2 Wrap Around Counter";
|
||||
tc2_empty 1 "Packet Buffer 2 Empty";
|
||||
tc3_wrap 3 "Packet Buffer 3 Wrap Around Counter";
|
||||
tc3_empty 1 "Packet Buffer 3 Empty";
|
||||
tc4_wrap 3 "Packet Buffer 4 Wrap Around Counter";
|
||||
tc4_empty 1 "Packet Buffer 4 Empty";
|
||||
tc5_wrap 3 "Packet Buffer 5 Wrap Around Counter";
|
||||
tc5_empty 1 "Packet Buffer 5 Empty";
|
||||
tc6_wrap 3 "Packet Buffer 6 Wrap Around Counter";
|
||||
tc6_empty 1 "Packet Buffer 6 Empty";
|
||||
tc7_wrap 3 "Packet Buffer 7 Wrap Around Counter";
|
||||
tc7_empty 1 "Packet Buffer 7 Empty";
|
||||
};
|
||||
|
||||
/************************************
|
||||
* 8.3.5.2 Interrupt Registers--VF
|
||||
***********************************/
|
||||
|
||||
// 8.3.5.2.1
|
||||
register vfeicr rw1c addr(base, 0x00100) "VF Extended Interrupt Cause" {
|
||||
msix 3 "Indicates an interrupt cause mapped to MSI-X vectors 2:0";
|
||||
_ 29 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.2.2
|
||||
register vfeics wo addr(base, 0x00104) "VF Extended Interrupt Cause Set" {
|
||||
msix 3 "Sets to corresponding EICR bit of MSI-X vectors 2:0";
|
||||
_ 29 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.2.3
|
||||
register vfeims rw addr(base, 0x00108) "VF Extended Interrupt Mask Set/Read" {
|
||||
msix 3 "Set mask bit for the corresponding EICR bit of MSI-X vectors 2:0";
|
||||
_ 29 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.2.4
|
||||
register vfeimc wo addr(base, 0x0010c) "VF Extended Interrupt Mask Clear" {
|
||||
msix 3 "Clear mask bit for the corresponding EICR bit of MSI-X vectors 2:0";
|
||||
_ 29 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.2.5
|
||||
register vfeiam rw addr(base, 0x00114) "VF Extended Interrupt Auto Mask Enable" {
|
||||
msix 3 "Auto mask bit for the corresponding EICR bit of MSI-X vectors 2:0";
|
||||
_ 29 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.2.6
|
||||
/*
|
||||
regtype vfeitrn "VF Extended Interrupt Throttle Register Type" {
|
||||
_ 3 rsvd;
|
||||
itr_int 9 "Minimum inter-interrupt interval";
|
||||
_ 3 rsvd;
|
||||
lli_mod 1 "LLI Moderation";
|
||||
lli_credit 5 "LLI Credit";
|
||||
itr_count 7 "ITR Counter";
|
||||
_ 3 rsvd;
|
||||
cnt_wdis 1 "CNT_WDIS";
|
||||
};
|
||||
*/
|
||||
// XXX: Not sure if this is correct...
|
||||
regarray vfeitr rw addr(base, 0x00820) [2]
|
||||
"VF Extended Interrupt Mask Set/Read #0-#1"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.2.7
|
||||
regarray vfivar rw addr(base, 0x00120) [4] "VF Interrupt Vector Allocation Registers" {
|
||||
i_alloc0 1 "Defines the MSI-X vector (0 or 1) assigned to Rx queue 2*N for IVAR N register (N = 0..3)";
|
||||
_ 6 rsvd;
|
||||
i_allocval0 1 "Interrupt allocation 0 valid";
|
||||
i_alloc1 1 "The interrupt allocation for Tx queue 2n";
|
||||
_ 6 rsvd;
|
||||
i_allocval1 1 "Interrupt allocation 1 valid";
|
||||
i_alloc2 1 "The interrupt allocation for Rx queue 2n+1";
|
||||
_ 6 rsvd;
|
||||
i_allocval2 1 "Interrupt allocation 2 valid";
|
||||
i_alloc3 1 "The interrupt allocation for Tx queue 2n+1";
|
||||
_ 6 rsvd;
|
||||
i_allocval3 1 "Interrupt allocation 3 valid";
|
||||
};
|
||||
|
||||
// 8.3.5.2.8
|
||||
register vfivar_misc rw addr(base, 0x00140) "VF Miscellaneous Interrupt Vector Allocation" {
|
||||
i_alloc0 2 "MSI-X vector assigned to the mailbox interrupt";
|
||||
_ 5 rsvd;
|
||||
i_allocval0 1 "Interrupt allocation 0 valid";
|
||||
_ 24 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.2.9
|
||||
// XXX: Not sure if this is correct...
|
||||
regarray vfrscint rw addr(base, 0x00180) [2] "VF RSC Enable Interrupt" type(uint32);
|
||||
|
||||
// 8.3.5.2.10
|
||||
register vfpbacl rw1c addr(base, 0x00148) "VF MSI-X PBA Clear" {
|
||||
penbit 3 "MSI-X Pending Bits Clear. Reading returns PBA vector.";
|
||||
_ 29 rsvd;
|
||||
};
|
||||
|
||||
/************************************
|
||||
* 8.3.5.3 Receive DMA Registers -- VF
|
||||
***********************************/
|
||||
|
||||
// 8.3.5.3.1
|
||||
regarray vfrdbal rw addr(base, 0x01000) [8; 0x40]
|
||||
"VF Receive Descriptor Base Address Low (#0-#7)"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.3.2
|
||||
regarray vfrdbah rw addr(base, 0x01004) [8; 0x40]
|
||||
"VF Receive Descriptor Base Address High (#0-#7)"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.3.3
|
||||
regarray vfrdlen rw addr(base, 0x01008) [8; 0x40]
|
||||
"VF Receive Descriptor Length (#0-#7)"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.3.4
|
||||
regarray vfrdh rw addr(base, 0x01010) [8; 0x40]
|
||||
"VF Receive Descriptor Head (#0-#7)"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.3.5
|
||||
regarray vfrdt rw addr(base, 0x01018) [8; 0x40]
|
||||
"VF Receive Descriptor Tail (#0-#7)"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.3.6
|
||||
regtype rxdctl "Receive Descriptor Control" {
|
||||
_ 25 rsvd;
|
||||
enable 1 "Receive Queue Enable";
|
||||
_ 4 rsvd;
|
||||
vme 1 "VLAN Mode Enable";
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
regarray vfrxdctl rw addr(base, 0x01028) [8; 0x40]
|
||||
"VF Receive Descriptor Control (#0-#7)"
|
||||
type(rxdctl);
|
||||
|
||||
// 8.3.5.3.7
|
||||
constants rx_desctype "RX Descriptor Type" {
|
||||
legacy = 0b000 "Legacy";
|
||||
adv_1buf = 0b001 "Advanced descriptor one buffer";
|
||||
adv_hdrsp = 0b010 "Advanced descriptor header splitting";
|
||||
adv_usehb = 0b101 "Advanced descriptor header splitting always use header buffer";
|
||||
};
|
||||
|
||||
regtype srrctl "Split Receive Control Registers" {
|
||||
bsz_pkt 5 "Receive Buffer Size for Packet Buffer";
|
||||
_ 3 mbz;
|
||||
bsz_hdr 6 "Receive Buffer Size for Header Buffer";
|
||||
_ 8 rsvd;
|
||||
rdmts 3 "Receive Descriptor Minimum Threshold Size";
|
||||
desctype 3 type(rx_desctype) "Define the descriptor type";
|
||||
drop_en 1 "Drop Enabled";
|
||||
_ 3 rsvd;
|
||||
};
|
||||
|
||||
regarray vfsrrctl rw addr(base, 0x01014) [8; 0x40]
|
||||
"VF Split Receive Control Registers (#0-#7)"
|
||||
type(srrctl);
|
||||
|
||||
// 8.3.5.3.8
|
||||
register vfpsrtype rw addr(base, 0x00300) "VF Replication Packet Split Receive Type" {
|
||||
_ 1 mbz;
|
||||
split_nfs 1 "Split received NFS packets after NFS header";
|
||||
_ 2 mbz;
|
||||
split_tcp 1 "Split received TCP packets after TCP header";
|
||||
split_udp 1 "Split received UDP packets after UDP header";
|
||||
_ 2 mbz;
|
||||
split_ip4 1 "Split received IPv4 packets after IPv4 header";
|
||||
split_ip6 1 "Split received IPv6 packets after IPv6 header";
|
||||
_ 2 mbz;
|
||||
split_l2 1 "Split received L2 packets after L2 header";
|
||||
_ 16 mbz;
|
||||
rqpl 3 "Number of bits to use for RSS redirection";
|
||||
};
|
||||
|
||||
// 8.3.5.3.9
|
||||
constants rsc_maxdesc "Maximum descriptors per Large receive" {
|
||||
max_1desc = 0b00 "Maximum of 1 descriptor per large receive";
|
||||
max_4desc = 0b01 "Maximum of 4 descriptors per large receive";
|
||||
max_8desc = 0b10 "Maximum of 8 descriptors per large receive";
|
||||
max_16desc = 0b11 "Maximum of 16 descriptors per large receive";
|
||||
};
|
||||
|
||||
regtype rscctl "RSC Control" {
|
||||
rsc_en 1 "RSC Enable";
|
||||
_ 1 rsvd;
|
||||
maxdesc 2 type(rsc_maxdesc) "Maximum descriptors per Large receive";
|
||||
_ 28 rsvd;
|
||||
};
|
||||
|
||||
regarray vfrscctl rw addr(base, 0x0102c) [8; 0x40]
|
||||
"RSC Control (#0-#7)"
|
||||
type(rscctl);
|
||||
|
||||
/************************************
|
||||
* 8.3.5.4 Transmit Registers -- VF
|
||||
***********************************/
|
||||
|
||||
// 8.3.5.4.1
|
||||
regarray vftdbal rw addr(base, 0x02000) [4; 0x40]
|
||||
"VF Transmit Descriptor Base Address Low"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.4.2
|
||||
regarray vftdbah rw addr(base, 0x02004) [4; 0x40]
|
||||
"VF Transmit Descriptor Base Address High"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.4.3
|
||||
regarray vftdlen rw addr(base, 0x02008) [4; 0x40]
|
||||
"VF Transmit Descriptor Length"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.4.4
|
||||
// rw is only partially accurate here. This register must only be written
|
||||
// directly after reset.
|
||||
regarray vftdh rw addr(base, 0x02010) [4; 0x40]
|
||||
"VF Transmit Descriptor Head"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.4.5
|
||||
regarray vftdt rw addr(base, 0x02018) [4; 0x40]
|
||||
"VF Transmit Descriptor Tail"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.4.6
|
||||
regarray vftxdctl rw addr(base, 0x02028) [4; 0x40] "VF Transmit Descriptor Control" {
|
||||
pthresh 7 "Pre-Fetch Threshold";
|
||||
_ 1 rsvd;
|
||||
hthresh 7 "Host Threshold";
|
||||
_ 1 rsvd;
|
||||
wthresh 7 "Write-Back Threshold";
|
||||
_ 2 rsvd;
|
||||
enable 1 "Transmit Queue Enable";
|
||||
swflsh 1 "Transmit Software Flush";
|
||||
_ 5 rsvd;
|
||||
};
|
||||
|
||||
// 8.3.5.4.7
|
||||
regarray vftdwbal rw addr(base, 0x02038) [4; 0x40] "VF Tx Descriptor Completion Write Back Address Low" {
|
||||
headwb_en 1 "Head Write-Back Enable";
|
||||
_ 1 rsvd;
|
||||
headwb_low 30 "Lowest 32 bits of the head write-back memory location";
|
||||
};
|
||||
|
||||
// 8.3.5.4.8
|
||||
regarray vftdwbah rw addr(base, 0x0203c) [4; 0x40] "VF Tx Descriptor Completion Write Back Address High" {
|
||||
headwb_high 32 "Highest 32 bits of the head write-back memory location";
|
||||
};
|
||||
|
||||
/************************************
|
||||
* 8.3.5.5 DCA Registers -- VF
|
||||
***********************************/
|
||||
|
||||
// 8.3.5.5.1
|
||||
regtype dca_rxctrl "Rx DCA Control Register" {
|
||||
_ 5 rsvd;
|
||||
rxdca_desc 1 "Descriptor DCA EN";
|
||||
rxdca_hdr 1 "Rx Header DCA EN";
|
||||
rxdca_payl 1 "Payload DCA EN";
|
||||
_ 1 rsvd;
|
||||
rxdesc_rdro 1 "Rx Descriptor Read Relax Order Enable";
|
||||
_ 1 rsvd;
|
||||
rxdesc_wbro 1 mbz "Rx Descriptor Write Back Relax Order Enable";
|
||||
_ 1 rsvd;
|
||||
rxdata_wrro 1 "Rx data Write Relax Order Enable";
|
||||
_ 1 rsvd;
|
||||
rxhdr_ro 1 "Rx Split Header Relax Order Enable";
|
||||
_ 8 rsvd;
|
||||
cpuid 8 "Physical ID";
|
||||
};
|
||||
|
||||
regarray vfdca_rxctrl rw addr(base, 0x0100c) [8; 0x40]
|
||||
"VF Rx DCA Control Register (#0-#7)"
|
||||
type(dca_rxctrl);
|
||||
|
||||
// 8.3.5.5.2
|
||||
regarray vfdca_txctrl rw addr(base, 0x0200c) [8; 0x40] "VF Tx DCA Control Registers" {
|
||||
_ 5 rsvd;
|
||||
txdesc_dca 1 "Descriptor DCA Enable";
|
||||
_ 3 rsvd;
|
||||
txdesc_rdro 1 "Tx Descriptor Read Relax Order Enable";
|
||||
_ 1 rsvd;
|
||||
txdesc_wbro 1 "Relax Order Enable of Tx Descriptor well as head pointer write back";
|
||||
_ 1 rsvd;
|
||||
txdata_rdro 1 "Tx Data Read Relax Order Enable";
|
||||
_ 10 rsvd;
|
||||
cpuid 8 "Physical ID";
|
||||
};
|
||||
|
||||
/************************************
|
||||
* 8.3.5.6 Statistics -- VF
|
||||
***********************************/
|
||||
|
||||
// 8.3.5.6.1
|
||||
register vfgprc ro addr(base, 0x0101c) "VF Good packets received count"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.6.2
|
||||
register vfgptc ro addr(base, 0x0201c) "VF Good packets trasmitted count"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.6.3
|
||||
register vfgorc_lsb ro addr(base, 0x01020) "VF Good Octets Received Count Low"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.6.4
|
||||
register vfgorc_msb ro addr(base, 0x01024) "VF Good Octets Received Count High"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.6.5
|
||||
register vfgotc_lsb ro addr(base, 0x02020) "VF Good Octets Transmitted Count Low"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.6.6
|
||||
register vfgotc_msb ro addr(base, 0x02024) "VF Good Octets Transmitted Count High"
|
||||
type(uint32);
|
||||
|
||||
// 8.3.5.6.7
|
||||
register vfmprc ro addr(base, 0x01034) "VF Multicast Packets Received Count"
|
||||
type(uint32);
|
||||
};
|
||||
469
devices/ehci.dev
Normal file
469
devices/ehci.dev
Normal file
@ -0,0 +1,469 @@
|
||||
/*
|
||||
* Copyright (c) 2009, 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ehci.dev
|
||||
*
|
||||
* DESCRIPTION: Enhanced Host Controller Interface description
|
||||
*
|
||||
* Numbers in comments refer to the Intel Enhanced Host Controller
|
||||
* Interface Specification for Universal Serial Bus, March 12, 2002,
|
||||
* Revision: 1.0
|
||||
*/
|
||||
|
||||
device ehci msbfirst (addr cap, addr op) "EHCI USB Controller" {
|
||||
|
||||
/*
|
||||
* Section 2.2
|
||||
* Host controller capabilty registers
|
||||
*/
|
||||
|
||||
// 2.2.1
|
||||
// The correct value for 'op' is actually 'cap' plus this number.
|
||||
register caplength ro addr(cap, 0x00) "Capability Registers Length"
|
||||
type(uint8);
|
||||
|
||||
// 2.2.2
|
||||
register hciversion ro addr(cap, 0x02) "Host Controller Interface Version Number"
|
||||
type(uint16);
|
||||
|
||||
// 2.2.3
|
||||
register hcsparams ro addr(cap, 0x04) "Structural parameters" {
|
||||
_ 8;
|
||||
dpn 4 "Debug port number";
|
||||
_ 3;
|
||||
p_indicator 1 "Port indicator";
|
||||
n_cc 4 "Number of campanion controller";
|
||||
n_pcc 4 "Number of ports per companion controller";
|
||||
prr 1 "Port routing rules";
|
||||
_ 2;
|
||||
ppc 1 "Port power control";
|
||||
n_ports 4 "Num. physical downstream ports on this controller";
|
||||
};
|
||||
|
||||
// 2.2.4
|
||||
register hccparams ro addr(cap, 0x08) "Capability parameters" {
|
||||
_ 16;
|
||||
eecp 8 "EHCI extended capabilities pointer";
|
||||
ist 4 "Isochronous scheduling threshold";
|
||||
_ 1;
|
||||
aspc 1 "Asynchronous sechedule park capability";
|
||||
pflf 1 "Programmable frame list flag";
|
||||
bit64ac 1 "Extended 64 bit addressing capability";
|
||||
};
|
||||
|
||||
// section 2.2.5 Companion port route descriptor
|
||||
register hcspportroute ro addr(cap, 0x0C) "Companion port route descr." {
|
||||
attr 60 "Port array";
|
||||
_ 4;
|
||||
};
|
||||
|
||||
/*
|
||||
* Section 2.3
|
||||
* Host controller operational registers
|
||||
*/
|
||||
|
||||
constants itc_val "Interrupt threshold control" {
|
||||
itc_val_rsvd = 0x00 "Reserved";
|
||||
uframe_1 = 0x01 "1 Micro frame";
|
||||
uframes_2 = 0x02 "2 Micro frames";
|
||||
uframes_4 = 0x04 "4 Micro frames";
|
||||
uframes_8 = 0x08 "8 Micro frames (default, equates to 1 ms)";
|
||||
uframes_16 = 0x10 "16 Micro frames (2 ms)";
|
||||
uframes_32 = 0x20 "32 Micro frames (4 ms)";
|
||||
uframes_64 = 0x40 "64 Micro frames (8 ms)";
|
||||
};
|
||||
|
||||
constants frame_val "Frame list size" {
|
||||
elem_1024 = 0b00 "1024 Elements (4096 bytes, default)";
|
||||
elem_512 = 0b01 "512 Elements (2048 bytes)";
|
||||
elem_256 = 0b10 "256 Elements (1024 bytes)";
|
||||
frame_rsvd = 0b11 "Reserved";
|
||||
};
|
||||
|
||||
// 2.3.1
|
||||
register usbcmd rw addr(op, 0x00) "USB command" {
|
||||
_ 8 mbz;
|
||||
itc 8 type(itc_val) "Interrupt threshold control";
|
||||
_ 4 mbz;
|
||||
aspme 1 rw "Asynchronous schedule park mode enable";
|
||||
_ 1 mbz;
|
||||
aspmc 2 rw "Asynchronous schedule park mode count";
|
||||
lhcr 1 rw "Light host controller reset";
|
||||
iaad 1 rw "Interrupt on async advance doorbell";
|
||||
ase 1 rw "Asynchronous schedule enable";
|
||||
pse 1 rw "Periodic schedule enable";
|
||||
fls 2 type(frame_val) "Frame list size";
|
||||
hcr 1 rw "Host controller reset";
|
||||
rs 1 rw "Run stop for scheduling";
|
||||
};
|
||||
|
||||
// 2.3.2
|
||||
register usbsts rw addr(op, 0x04) "USB status" {
|
||||
_ 16 mbz;
|
||||
ass 1 ro "Asynchronous schedule status";
|
||||
pss 1 ro "Periodic schedule status";
|
||||
rec 1 ro "Reclamation";
|
||||
hch 1 ro "Host controller halted see Run/Stop";
|
||||
_ 6 mbz;
|
||||
iaa 1 rwc "Interrupt on Async advance";
|
||||
hse 1 rwc "Host system error";
|
||||
flr 1 rwc "Frame list rollover";
|
||||
pcd 1 rwc "Port change detect";
|
||||
usbei 1 rwc "USB error interrupt";
|
||||
usbi 1 rwc "USB interrupt";
|
||||
};
|
||||
|
||||
// 2.3.3
|
||||
register usbintr rw addr(op, 0x08) "USB interrupt enable" {
|
||||
_ 26 mbz;
|
||||
iaae 1 "Interrupt on async advance enable";
|
||||
hsee 1 "Host system error enable";
|
||||
flre 1 "Frame list rollover enable";
|
||||
pcie 1 "Port change interrupt enable";
|
||||
usbeie 1 "USB error interrupt enable";
|
||||
usbie 1 "USB interrupt enable";
|
||||
};
|
||||
|
||||
// 2.3.4
|
||||
register frindex rw addr(op, 0x0C) "Frame index" {
|
||||
_ 18 mbz;
|
||||
fi 14 "Frame index";
|
||||
};
|
||||
|
||||
// 2.3.5
|
||||
// NOTE: Only enabled if 64 bit address capability is enabled
|
||||
register ctrldssegment rw addr(op, 0x10) "Control data structure segment" {
|
||||
data 32 rw "MSB [63:32] bits of EHCI data strctures";
|
||||
};
|
||||
|
||||
// 2.3.6
|
||||
register periodiclistbase rw addr(op, 0x14) "Periodic frame list base addr" {
|
||||
addr 20 rw "Base address (must be 4k aligned)";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
// 2.3.7
|
||||
register asynclistaddr rw addr(op, 0x18) "Current async. list addr." {
|
||||
lpl 27 rw "Link pointer low";
|
||||
_ 5 mbz;
|
||||
};
|
||||
|
||||
// 2.3.8
|
||||
register configflag rw addr(op, 0x40) "Configure flag" {
|
||||
_ 31 mbz;
|
||||
cf 1 rw "Configure flag";
|
||||
};
|
||||
|
||||
// 2.3.9
|
||||
constants test_mode_val "Test modes" {
|
||||
disabled = 0b0000 "Test mode not enabled";
|
||||
test_j_st = 0b0001 "Test J_STATE";
|
||||
test_k_st = 0b0010 "Test K_STATE";
|
||||
se0_nak = 0b0011 "Test SE0_NAK";
|
||||
test_pack = 0b0100 "Test packet";
|
||||
force_ena = 0b0101 "Force enable";
|
||||
};
|
||||
|
||||
constants indi_val "Port indicator values" {
|
||||
off = 0b00 "Port indicators are off";
|
||||
amber = 0b01 "Amber";
|
||||
green = 0b10 "Green";
|
||||
indi_val_undef = 0b11 "Undefined";
|
||||
};
|
||||
|
||||
constants lstatus_val "USB line status" {
|
||||
se0 = 0b00 "Not low speed device, perform EHCI reset";
|
||||
j_state = 0b10 "Not low speed device, perform EHCI reset";
|
||||
k_state = 0b01 "Low speed device, release ownership of port";
|
||||
lstatus_undef = 0b11 "Not low speed device, perform EHCI reset";
|
||||
};
|
||||
|
||||
regarray portsc rw addr(op, 0x44)[16] "Port status and control" {
|
||||
_ 9 mbz;
|
||||
wkoc_e 1 "Wake on over-current enable";
|
||||
wkdscnnt_e 1 "Wake on disconnect enable";
|
||||
wkcnnt_e 1 "Wake on connect enable";
|
||||
ptc 4 type(test_mode_val) "Port test control";
|
||||
pic 2 type(indi_val) "Port indicator control";
|
||||
po 1 "Port owner";
|
||||
pp 1 "Port power";
|
||||
ls 2 type(lstatus_val) "Line status value";
|
||||
_ 1 mbz;
|
||||
pr 1 "Port reset";
|
||||
sus 1 "Port suspend";
|
||||
fpr 1 "Force port resume";
|
||||
occ 1 rwc "Over current change";
|
||||
oca 1 ro "Over current active";
|
||||
pec 1 rwc "Port enable/disbale change";
|
||||
ped 1 "Port enabled/disabled";
|
||||
csc 1 rwc "Connect status change";
|
||||
ccs 1 ro "Current connect status";
|
||||
};
|
||||
/*
|
||||
//
|
||||
// In-memory data structures
|
||||
//
|
||||
|
||||
// 3.1
|
||||
constants lptype width(2) "Link pointer type" {
|
||||
lp_itd = 0b00 "Isochronous transfer descriptor";
|
||||
lp_qh = 0b01 "Queue head";
|
||||
lp_sitd = 0b10 "Split transaction isochronous trans. desc.";
|
||||
lp_fstn = 0b11 "Frame span traversal node";
|
||||
};
|
||||
|
||||
datatype lp msbfirst(32) "Link pointer" {
|
||||
p 27 "Frame list link pointer";
|
||||
_ 2 mbz;
|
||||
typ 2 type(lptype) "Pointer type";
|
||||
t 1 "Pointer value invalid";
|
||||
};
|
||||
|
||||
// 3.3
|
||||
datatype itd msbfirst(32) "Isochronous transfer descriptor" {
|
||||
next 32 type(lp) "Next descriptor";
|
||||
sc0 32 type(itsc) "Transaction 0 Status/control";
|
||||
sc1 32 type(itsc) "Transaction 1 Status/control";
|
||||
sc2 32 type(itsc) "Transaction 2 Status/control";
|
||||
sc3 32 type(itsc) "Transaction 3 Status/control";
|
||||
sc4 32 type(itsc) "Transaction 4 Status/control";
|
||||
sc5 32 type(itsc) "Transaction 5 Status/control";
|
||||
sc6 32 type(itsc) "Transaction 6 Status/control";
|
||||
sc7 32 type(itsc) "Transaction 7 Status/control";
|
||||
bp0 32 type(itbp0) "Buffer pointer 0";
|
||||
bp1 32 type(itbp1) "Buffer pointer 1";
|
||||
bp2 32 type(itbp2) "Buffer pointer 2";
|
||||
bp3 32 type(itbp3) "Buffer pointer 3";
|
||||
bp4 32 type(itbp3) "Buffer pointer 4";
|
||||
bp5 32 type(itbp3) "Buffer pointer 5";
|
||||
bp6 32 type(itbp3) "Buffer pointer 6";
|
||||
};
|
||||
|
||||
// 3.3.2
|
||||
datatype itsc msbfirst(32) "Isochronous transaction status/control" {
|
||||
// Status
|
||||
active 1 "Active";
|
||||
dbe 1 "Data buffer error";
|
||||
bd 1 "Babble detected";
|
||||
xacterr 1 "Transaction error";
|
||||
// Control
|
||||
length 12 "Transaction length";
|
||||
ioc 1 "Interrupt on complete";
|
||||
pg 3 "Page select (0-6)";
|
||||
offset 12 "Offset from state of buffer";
|
||||
};
|
||||
|
||||
// 3.3.3
|
||||
datatype itbp0 msbfirst(32) "iTD buffer pointer page 0" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
epn 4 "Endpoint number";
|
||||
_ 1 mbz;
|
||||
da 7 "Device address";
|
||||
};
|
||||
datatype itdp1 msbfirst(32) "iTD buffer pointer page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
dir 1 "In (1) or out (0) PID";
|
||||
mps 11 "Maximum packet size";
|
||||
};
|
||||
datatype itdp2 msbfirst(32) "iTD buffer pointer page 2" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 10 mbz;
|
||||
multi 2 "Num. transactions/micro-frame + 1 (0=rsvd)";
|
||||
};
|
||||
datatype itdp3 msbfirst(32) "iTD buffer pointer page 3" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
// 3.4
|
||||
datatype sitd msbfirst(32) "Split isochronous transfer descriptor" {
|
||||
next 32 type(lp) "Next descriptor";
|
||||
cap 32 type(sitcap) "Endpoint capabilities/characteristics";
|
||||
msc 32 type(sitmsc) "Micro-frame schedule control";
|
||||
tsc 32 type(sittsc) "Transfer status and control";
|
||||
bpl0 32 type(sitbpl0) "Buffer page pointer 0";
|
||||
bpl1 32 type(sitbpl1) "Buffer page pointer 1";
|
||||
bp 32 type(sitblp) "Back link";
|
||||
};
|
||||
|
||||
// 3.4.2
|
||||
datatype sitcap msbfirst(32) "siTD endpoint capabilities/characteristics" {
|
||||
dir 1 "In (1) or out (0) PID";
|
||||
port 7 "Port number";
|
||||
_ 1 mbz;
|
||||
hub 7 "Hub address";
|
||||
_ 4 mbz;
|
||||
epn 4 "Endpoint number";
|
||||
_ 1 mbz;
|
||||
da 7 "Device address";
|
||||
};
|
||||
datatype sitmsc msbfirst(32) "siTD micro-frame schedule control" {
|
||||
_ 16 mbz;
|
||||
scm 8 "Split completion mask";
|
||||
ssm 8 "Split start mask";
|
||||
};
|
||||
|
||||
// 3.4.3
|
||||
datatype sittsc msbfirst(32) "siTD transfer status and control" {
|
||||
ioc 1 "Interrupt on complete";
|
||||
p 1 "Page select";
|
||||
_ 4 mbz;
|
||||
total 10 "Total bytes to transfer";
|
||||
cpm 8 "Microframe complete-split progress mask";
|
||||
active 1 "Status active";
|
||||
err 1 "ERR response rcvd from transaction translator";
|
||||
dbe 1 "Data buffer error";
|
||||
babble 1 "Babble detected";
|
||||
xacterr 1 "Transaction error";
|
||||
mmf 1 "Missed micro-frame";
|
||||
sts 1 "Split transaction state";
|
||||
_ 1 mbz;
|
||||
};
|
||||
|
||||
// 3.4.4
|
||||
constants xpos width(2) "Transaction position" {
|
||||
tp_all = 0b00 "Entire payload";
|
||||
tp_begin = 0b01 "First data payload";
|
||||
tp_mid = 0b10 "Middle payload";
|
||||
tp_end = 0b11 "Final payload";
|
||||
};
|
||||
datatype sitbpl0 msbfirst(32) "siTD buffer page pointer list page 0" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
offset 12 "Current offset";
|
||||
};
|
||||
datatype sitbpl1 msbfirst(32) "siTD buffer page pointer list page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 7 mbz;
|
||||
tp 2 type(xpos) "Transaction position";
|
||||
tc 3 "Transaction count";
|
||||
};
|
||||
|
||||
// 3.4.5
|
||||
datatype sitblp msbfirst(32) "siTD back link pointer" {
|
||||
bp 27 "Back pointer";
|
||||
_ 4 mbz;
|
||||
t 1 "Terminate (0 -> bp is valid)";
|
||||
};
|
||||
|
||||
// 3.5
|
||||
datatype qtd msbfirst(32) "Queue element transfer descriptor" {
|
||||
next 32 type(lp) "Next element";
|
||||
altnext 32 type(lp) "Alternate next pointer";
|
||||
token 32 type(qttok) "Token";
|
||||
bp0 32 type(qtbp0) "Buffer pointer 0";
|
||||
bp1 32 type(qtbp1) "Buffer pointer 1";
|
||||
bp2 32 type(qtbp1) "Buffer pointer 2";
|
||||
bp3 32 type(qtbp1) "Buffer pointer 3";
|
||||
bp4 32 type(qtbp1) "Buffer pointer 4";
|
||||
};
|
||||
|
||||
// 3.5.3
|
||||
constants pid "PID token encoding" {
|
||||
pid_out = 0b00 "Generates OUT token (E1H)";
|
||||
pid_in = 0b01 "Generates IN token (69H)";
|
||||
pid_setup = 0b10 "Generates SETUP token (2DH)";
|
||||
pid_rsvd = 0b11 "Reserved";
|
||||
};
|
||||
|
||||
datatype qttok msbfirst(32) "qTD Token" {
|
||||
toggle 1 "Data toggle";
|
||||
tbt 15 "Total bytes to transfer";
|
||||
ioc 1 "Interrupt on complete";
|
||||
cp 3 "Current page";
|
||||
cerr 2 "Error counter";
|
||||
pidc 2 type(pid) "PID code token";
|
||||
active 1 "Status active";
|
||||
halted 1 "Serious error at endpoint";
|
||||
dbe 1 "Data buffer error";
|
||||
babble 1 "Babble detected";
|
||||
xacterr 1 "Transaction error";
|
||||
mmf 1 "Missed micro-frame";
|
||||
sts 1 "Split transaction state";
|
||||
ping 1 "Ping state";
|
||||
};
|
||||
|
||||
// 3.5.4
|
||||
datatype qtbp0 msbfirst(32) "Queue element buffer pointer page 0" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
offset 12 "Current offset";
|
||||
};
|
||||
datatype qtbp1 msbfirst(32) "Queue element buffer pointer page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
// 3.6
|
||||
datatype qh msbfirst(32) "Queue head" {
|
||||
hlp 32 type(lp) "Horizontal link pointer";
|
||||
cap1 32 type(qhcap1) "Endpoint capabilities/characteristics 1";
|
||||
cap2 32 type(qhcap2) "Endpoint capabilities/characteristics 2";
|
||||
current 32 type(lp) "Current element";
|
||||
next 32 type(lp) "Next element";
|
||||
altnext 32 type(qhlp) "Alternate next pointer";
|
||||
token 32 type(qttok) "Token";
|
||||
bp0 32 type(qtbp0) "Buffer pointer 0";
|
||||
bp1 32 type(qhbp1) "Buffer pointer 1";
|
||||
bp2 32 type(qhbp2) "Buffer pointer 2";
|
||||
bp3 32 type(qtbp1) "Buffer pointer 3";
|
||||
bp4 32 type(qtbp1) "Buffer pointer 4";
|
||||
};
|
||||
|
||||
// 3.6.2
|
||||
constants speed width(2) "Endpoint speed" {
|
||||
fullspeed = 0b00 "Full-speed (12Mbs)";
|
||||
lowspeed = 0b01 "Low-speed (1.5Mbs)";
|
||||
highspeed = 0b10 "High-speed (480 Mb/s)";
|
||||
};
|
||||
|
||||
datatype qhcap1 msbfirst(32) "Endpoint capabilities: queue head word 1"{
|
||||
rl 4 "NAK count reload";
|
||||
c 1 "Control endpoint flag";
|
||||
mpl 11 "Maximum packet length";
|
||||
h 1 "Head of reclamation list flag";
|
||||
dtc 1 "Data toggle control";
|
||||
eps 2 type(speed) "Endpoint speed";
|
||||
epn 4 "Endpoint number";
|
||||
i 1 "Inactivate on next transaction";
|
||||
da 7 "Device address";
|
||||
};
|
||||
|
||||
datatype qhcap2 msbfirst(32) "Endpoint capabilities: queue head word 2"{
|
||||
mult 2 "High-bandwidth pipe multiplier";
|
||||
port 7 "Port number";
|
||||
hub 7 "Hub address";
|
||||
scm 8 "Split completion mask";
|
||||
ism 8 "Interrupt schedule mask";
|
||||
};
|
||||
|
||||
// 3.6.3
|
||||
datatype qhlpa msbfirst(32) "Alternate queue head link pointer" {
|
||||
p 27 "Frame list link pointer";
|
||||
nakcnt 4 "NACK counter";
|
||||
t 1 "Pointer value invalid";
|
||||
};
|
||||
|
||||
datatype qhbp1 msbfirst(32) "Queue head buffer pointer page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 4 mbz;
|
||||
cpm 8 "Split-transaction complete-split progress";
|
||||
};
|
||||
|
||||
datatype qhbp2 msbfirst(32) "Queue head buffer pointer page 2" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
sb 7 "S-bytes";
|
||||
ft 5 "Split-transaction frame tag";
|
||||
};
|
||||
|
||||
// 3.7
|
||||
datatype fstm msbfirst(32) "Periodic Frame Span Traversal Node" {
|
||||
normal 32 type(lp) "Normal path link pointer";
|
||||
back 32 type(lp) "Back path link pointer";
|
||||
};*/
|
||||
};
|
||||
|
||||
38
devices/fat16_ebpb.dev
Normal file
38
devices/fat16_ebpb.dev
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* fat16_ebpb.dev
|
||||
*
|
||||
* DESCRIPTION: FAT16 file system extended BIOS parameter block.
|
||||
*
|
||||
*/
|
||||
|
||||
device fat16_ebpb msbfirst (addr b) "FAT16 Extended BIOS Parameter Block (EBPB)" {
|
||||
|
||||
register drv rw addr(b,0x24) "Drive number" type(uint8);
|
||||
|
||||
// In [1], this is described as "current head". The same document says that
|
||||
// because it is not used as such, Windows NT uses it as follows instead (lsbfirst):
|
||||
// - bit 0: need disk check
|
||||
// - bit 1: need surface scan
|
||||
// [1] http://support.microsoft.com/kb/140418
|
||||
register rsv rw addr(b,0x25) "Reserved" type(uint8);
|
||||
|
||||
// Should be 0x29 to indicate this is an EBPB. 0x28 Also possible, in which
|
||||
// only the serial number follows.
|
||||
register ebs rw addr(b,0x26) "Extended boot signature" type(uint8);
|
||||
|
||||
register vsn rw addr(b,0x27) "Volume serial number" type(uint32);
|
||||
|
||||
regarray vlb rw addr(b,0x2b) [11] "Volume label" type(uint8);
|
||||
|
||||
// Should be "FAT16 "
|
||||
regarray fst rw addr(b,0x36) [8] "File system type, informative" type(uint8);
|
||||
|
||||
};
|
||||
51
devices/fat32_ebpb.dev
Normal file
51
devices/fat32_ebpb.dev
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright (c) 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* fat32_ebpb.dev
|
||||
*
|
||||
* DESCRIPTION: FAT32 file system extended BIOS parameter block.
|
||||
*
|
||||
*/
|
||||
|
||||
device fat32_ebpb lsbfirst (addr b) "FAT32 Extended BIOS Parameter Block (EBPB)" {
|
||||
|
||||
register spf rw addr(b,0x24) "Sectors per FAT" type(uint32);
|
||||
|
||||
register flgs rw addr(b,0x28) "Flags" {
|
||||
afc 5 "Active FAT Copy";
|
||||
_ 1 rsvd;
|
||||
fme 1 "FAT Mirror Enabled";
|
||||
_ 9 rsvd;
|
||||
};
|
||||
|
||||
register vrsn rw addr(b,0x2a) "Version" type(uint16);
|
||||
|
||||
register rtst rw addr(b,0x2c) "Start cluster of root directory" type(uint32);
|
||||
|
||||
register fsis rw addr(b,0x30) "Sector of the File System Information Sector" type(uint16);
|
||||
|
||||
register bbss rw addr(b,0x32) "Sector of backup boot sector, 0 implies no backup" type(uint16);
|
||||
|
||||
// 0x34: rsvd, 12 bytes
|
||||
|
||||
// See fat16_ebpb bytes 0x24-0x26 for descriptions the following three bytes
|
||||
register ldn rw addr(b,0x40) "Logical Drive Number of partition" type(uint8);
|
||||
|
||||
register rsv rw addr(b,0x41) "Reserved" type(uint8);
|
||||
|
||||
register ebs rw addr(b,0x42) "Extended boot signature" type(uint8);
|
||||
|
||||
register vsn rw addr(b,0x43) "Volume serial number" type(uint32);
|
||||
|
||||
regarray vlb rw addr(b,0x47) [11] "Volume label" type(uint8);
|
||||
|
||||
// Should be "FAT32 ";
|
||||
regarray fst rw addr(b,0x52) [8] "File system type, informative" type(uint8);
|
||||
|
||||
};
|
||||
47
devices/fat_bpb.dev
Normal file
47
devices/fat_bpb.dev
Normal file
@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (c) 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* fat16_bootsector.dev
|
||||
*
|
||||
* DESCRIPTION: FAT16 file system boot sector.
|
||||
*
|
||||
* This always starts at offset 0xb and is documented as such in Microsoft
|
||||
* documentation [1], so put the first entry at offset 0xb too, allowing the
|
||||
* initialize function to be called with the regular base address.
|
||||
*
|
||||
* [1] http://support.microsoft.com/kb/140418
|
||||
*/
|
||||
|
||||
device fat_bpb msbfirst (addr b) "FAT BIOS Parameter Block (BPB)" {
|
||||
|
||||
register bps rw addr(b,0x0b) "Bytes per sector (must be 512, 1024, 2048 or 4096)" type(uint16);
|
||||
|
||||
register spc rw addr(b,0x0d) "Sectors per cluster, must be power of 2" type(uint8);
|
||||
|
||||
register rsvs rw addr(b,0x0e) "Reserved sectors from the start of the volume" type(uint16);
|
||||
|
||||
register fatc rw addr(b,0x10) "Number of FAT copies" type(uint8);
|
||||
|
||||
register rtc rw addr(b,0x11) "Maximum number of root entries" type(uint16);
|
||||
|
||||
register ssc rw addr(b,0x13) "Small sector count, used when volume is smaller than 32 MB" type(uint16);
|
||||
|
||||
register mdes rw addr(b,0x15) "Media descriptor" type(uint8);
|
||||
|
||||
register spf rw addr(b,0x16) "Sectors per FAT" type(uint16);
|
||||
|
||||
register spt rw addr(b,0x18) "Sectors per track" type(uint16);
|
||||
|
||||
register heds rw addr(b,0x1a) "Number of heads" type(uint16);
|
||||
|
||||
register hids rw addr(b,0x1c) "Hidden sectors (preceding volume start)" type(uint32);
|
||||
|
||||
register lsc rw addr(b,0x20) "Large sector count, when volume is larger than 32 MB" type(uint32);
|
||||
|
||||
};
|
||||
76
devices/fat_direntry.dev
Normal file
76
devices/fat_direntry.dev
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* fat16_direntry.dev
|
||||
*
|
||||
* DESCRIPTION: FAT16 file system directory entry.
|
||||
*
|
||||
*/
|
||||
|
||||
device fat_direntry msbfirst (addr b) "FAT 16 Directory Entry" {
|
||||
|
||||
constants attribute "directory entry attribute" {
|
||||
attr_read_only = 0x01 "read only";
|
||||
attr_hidden = 0x02 "hidden";
|
||||
attr_system = 0x04 "system";
|
||||
attr_volume_id = 0x08 "Volume ID";
|
||||
attr_directory = 0x10 "Directory";
|
||||
attr_archive = 0x20 "Archive";
|
||||
attr_long_name = 0x0f "Long name";
|
||||
};
|
||||
|
||||
regarray fn rw addr(b,0x00) [8] "Filename" type(uint8);
|
||||
|
||||
regarray ext rw addr(b,0x08) [3] "Filename extension" type(uint8);
|
||||
|
||||
register attr rw addr(b,0x0b) "File Attributes" {
|
||||
_ 2 rsvd;
|
||||
ar 1 "Archive";
|
||||
dir 1 "Directory";
|
||||
vlb 1 "Volume label";
|
||||
sys 1 "System file";
|
||||
hid 1 "Hidden";
|
||||
ro 1 "Read only";
|
||||
};
|
||||
|
||||
register lwr rw addr(b,0x0c) "Base and extension case" {
|
||||
_ 3 rsvd;
|
||||
el 1 "Extension is lowercase";
|
||||
bl 1 "Base is lowercase";
|
||||
_ 3 rsvd;
|
||||
};
|
||||
|
||||
regtype time "Time" {
|
||||
hour 5 "Hour";
|
||||
min 6 "Minutes";
|
||||
dsec 5 "Double seconds (0-29)";
|
||||
};
|
||||
|
||||
regtype date "Date" {
|
||||
yr 7 "Years from 1980";
|
||||
mnth 4 "Month of year";
|
||||
day 5 "Day of month";
|
||||
};
|
||||
|
||||
register ctms rw addr(b,0x0d) "Creation deca-milliseconds (0-199)" type(uint8);
|
||||
register ctime rw addr(b,0x0e) "Creation time" type(time);
|
||||
register cdate rw addr(b,0x10) "Create date" type(date);
|
||||
|
||||
register adate rw addr(b,0x12) "Last access date" type(date);
|
||||
|
||||
// register eaind rw addr(b,0x14) "EA-Index (?)" type(uint16);
|
||||
register starth rw addr(b,0x14) "Start cluster high bits (FAT32)" type(uint16);
|
||||
|
||||
register wtime rw addr(b,0x16) "Last write time" type(time);
|
||||
register wdate rw addr(b,0x18) "Last write date" type(date);
|
||||
|
||||
register start rw addr(b,0x1a) "Starting cluster" type(uint16);
|
||||
register size rw addr(b,0x1c) "File size" type(uint32);
|
||||
|
||||
};
|
||||
33
devices/fat_long_direntry.dev
Normal file
33
devices/fat_long_direntry.dev
Normal file
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* fat_long_direntry.dev
|
||||
*
|
||||
* DESCRIPTION: FAT16 file system directory entry.
|
||||
*
|
||||
*/
|
||||
|
||||
device fat_long_direntry msbfirst (addr b) "FAT 32 Long Directory Entry" {
|
||||
|
||||
register ord rw addr(b, 0x00) "The order of this entry" type(uint8);
|
||||
|
||||
regarray name1 rw addr(b,0x01) [5] "Characters 1-5 of the long name" type(uint16);
|
||||
|
||||
register attr rw addr(b, 0x0b) "Attributes" type(uint8);
|
||||
|
||||
register etype rw addr(b, 0x0c) "If zero, indicates a directory entry" type(uint8);
|
||||
|
||||
register checksum rw addr(b, 0x0d) "Checksum" type(uint8);
|
||||
|
||||
regarray name2 rw addr(b, 0x0e) [6] "Character 6-11 of the longname" type(uint16);
|
||||
|
||||
register fstclu rw addr(b, 0x1a) "Must be zero" type(uint16);
|
||||
|
||||
regarray name3 rw addr(b, 0x1c) [2] "Character 6-11 of the longname" type(uint16);
|
||||
};
|
||||
140
devices/gic_v2_cpu.dev
Normal file
140
devices/gic_v2_cpu.dev
Normal file
@ -0,0 +1,140 @@
|
||||
/*
|
||||
* Memory mapped GIC v2 CPU Interface. sysreg mapped (GICv3) CPU interfaces
|
||||
* should use definitions in armv8.dev.
|
||||
* Source: ARM IHI 0069B, page 8-560
|
||||
*/
|
||||
device gic_v2_cpu msbfirst (addr cpuif) "MMIO mapped GIC CPU interface" {
|
||||
|
||||
register CTLR rw addr(cpuif, 0x0) "CPU Interface Control Register - secure" {
|
||||
_ 21 mbz;
|
||||
EOImodeNS 1;
|
||||
EOImodeS 1;
|
||||
IRQBypDisGrp1 1;
|
||||
FIQBypDisGrp1 1;
|
||||
IRQBypDisGrp0 1;
|
||||
FIQBypDisGrp0 1;
|
||||
CBPR 1;
|
||||
FIQEn 1;
|
||||
_ 1 mbz;
|
||||
EnableGrp1 1;
|
||||
EnableGrp0 1;
|
||||
};
|
||||
|
||||
register CTLR_NS rw also addr(cpuif, 0x0) "CPU Interface Control Register - Non-secure" {
|
||||
_ 22 mbz;
|
||||
EOImodeNS 1;
|
||||
RES0 2;
|
||||
IRQBypDisGrp1 1;
|
||||
FIQBypDisGrp1 1;
|
||||
_ 4 mbz;
|
||||
EnableGrp1 1;
|
||||
};
|
||||
|
||||
register PMR rw addr(cpuif, 0x0004) "Interrupt Controller Interrupt Priority Mask Register" {
|
||||
_ 24;
|
||||
priority 8 "Priority mask level";
|
||||
};
|
||||
|
||||
register BPR rw addr(cpuif, 0x0008) "Interrupt Controller Binray Point Register" {
|
||||
_ 29;
|
||||
binary_point 3;
|
||||
};
|
||||
|
||||
register IAR rw addr(cpuif, 0x000C) "Interrupt Controller Interrupt Acknowledge Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID of the signaled interrupt";
|
||||
};
|
||||
|
||||
register EOIR wo addr(cpuif, 0x0010) "Interrupt Controller End Of Interrupt Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID from the corresponding ICC_IAR0_EL1 access";
|
||||
};
|
||||
|
||||
|
||||
register RPR ro addr(cpuif, 0x0014) "Running Priority Register" {
|
||||
|
||||
_ 24;
|
||||
priority 8 "Running priority";
|
||||
};
|
||||
|
||||
|
||||
register HPPIR ro addr(cpuif, 0x0018) "Highest Priority Pending Interrupt Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID of the highest priority pending interrupt";
|
||||
};
|
||||
|
||||
register ABPR rw addr(cpuif, 0x001c) "Aliased Binary Point Register" {
|
||||
_ 29;
|
||||
binary_point 3;
|
||||
};
|
||||
|
||||
register AIAR ro addr(cpuif, 0x0020) "Aliased Interrupt Acknowledge Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID of the signaled interrupt";
|
||||
};
|
||||
|
||||
register AEOIR wo addr(cpuif, 0x0024) "Aliased End of Interrupt Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID from the corresponding ICC_IAR0_EL1 access";
|
||||
};
|
||||
|
||||
register AHPPIR ro addr(cpuif, 0x0028) "Aliased Highest Priority Pending Interrupt Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID of the highest priority pending interrupt";
|
||||
};
|
||||
|
||||
register STATUSR rw addr(cpuif, 0x002C) "Error Reporting Status Register" {
|
||||
_ 27;
|
||||
asv 1 "Attempted security violation";
|
||||
wrod 1 "Write to an RO location";
|
||||
rwod 1 "Read of a WO location";
|
||||
wrd 1 "Write to a reserved location";
|
||||
rrd 1 "Read of a reserved location";
|
||||
};
|
||||
|
||||
register APR1 rw addr(cpuif, 0x00D0) "CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register APR2 rw addr(cpuif, 0x00D4) "CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register APR3 rw addr(cpuif, 0x00D8) "CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register APR4 rw addr(cpuif, 0x00DC) "CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register NSAPR1 rw addr(cpuif, 0x00E0) "Non-secure CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register NSAPR2 rw addr(cpuif, 0x00E4) "Non-secure CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register NSAPR3 rw addr(cpuif, 0x00E8) "Non-secure CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register NSAPR4 rw addr(cpuif, 0x00EC) "Non-secure CPU Interface Active Priorities Registers" {
|
||||
impl 32;
|
||||
};
|
||||
|
||||
register IIDR ro addr(cpuif, 0x00FC) "CPU Interface Identification Register" {
|
||||
ProductID 8 "Product identifier";
|
||||
_ 4 mbz;
|
||||
Variant 4 "Variant number";
|
||||
Revision 4 "Revision number";
|
||||
Implementer 12 "JEP106 code of implementing company";
|
||||
};
|
||||
|
||||
register DIR wo addr(cpuif, 0x1000) "Deactivate Interrupt Register" {
|
||||
_ 8;
|
||||
intid 24 "INTID of the highest priority pending interrupt";
|
||||
};
|
||||
|
||||
};
|
||||
159
devices/gic_v3_dist.dev
Normal file
159
devices/gic_v3_dist.dev
Normal file
@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* gic_v3.dev
|
||||
*
|
||||
* DESCRIPTION: GIC v3 architecture definitions
|
||||
*
|
||||
* See:
|
||||
* GIC v3 Architecture Specification
|
||||
*/
|
||||
|
||||
device gic_v3_dist msbfirst (addr dist) "GIC v3 Distributor" {
|
||||
|
||||
register GICD_CTLR_secure addr(dist, 0x0) "Distributor Control Register" {
|
||||
RWP 1 ro "Register Write Pending";
|
||||
_ 23;
|
||||
E1NWF 1 "Enable 1 of N Wakeup Functionality";
|
||||
DS 1 "Disable Security";
|
||||
ARE_NS 1 "Affinity Routing Enable, Non-secure state";
|
||||
ARE_S 1 "Affinity Routing Enable, Secure state";
|
||||
_ 1 mbz;
|
||||
EnableGrp1S 1 "Enable Secure Group 1 interrupts";
|
||||
EnableGrp1NS 1 "Enable Non-secure Group 1 interrupts";
|
||||
EnableGrp0 1 "Enable Group 0 interrupts";
|
||||
};
|
||||
|
||||
|
||||
register GICD_CTLR also addr(dist, 0x0) "Distributor Control Register" {
|
||||
RWP 1 ro "Register Write Pending";
|
||||
_ 26;
|
||||
ARE_NS 1 "Affinity Routing Enable, Non-secure state";
|
||||
_ 2 mbz;
|
||||
EnableGrp1A 1 "ARE_NS=1 -> Enable Secure Group 1 interrupts";
|
||||
EnableGrp1 1 "ARE_NS=1 -> Enable Non-secure Group 1 interrupts";
|
||||
};
|
||||
|
||||
register GICD_TYPER rw addr(dist, 0x4) "Interrupt Controller Type Register" {
|
||||
_ 6 mbz;
|
||||
No1N 1 "1 of N SPI interrupts not supported";
|
||||
A3V 1 "Affinity 3 valid";
|
||||
IDbits 5 "The number of interrupt identifier bits supported, minus one";
|
||||
DVIS 1 "Implementation supports Direct Virtual LPI injection";
|
||||
LPIS 1 "Implementation supports LPIs";
|
||||
MBIS 1 "Implementation supports message-based interrupts";
|
||||
LSPI 5 "maximum number of implemented lockable SPI";
|
||||
SecurityExtn 1 "Indicates whether the GIC implementation supports two Security states";
|
||||
_ 2 mbz;
|
||||
CPUNumber 3 "Number of PEs that can be used with affinity routing not enabled, minus one";
|
||||
ITLinesNumber 5 "Maximum SPI INTID supported";
|
||||
};
|
||||
|
||||
register GICD_IIDR ro addr(dist, 0x8) "Distributor Implementer Identification Register" {
|
||||
ProductID 8 "Product identifier";
|
||||
_ 4 mbz;
|
||||
Variant 4 "Variant number";
|
||||
Revision 4 "Revision number";
|
||||
Implementer 12 "JEP106 code of implementing company";
|
||||
};
|
||||
|
||||
register GICD_STATUSR rw addr(dist, 0x10) "Error Reporting Status Register" {
|
||||
_ 28 mbz;
|
||||
WROD 1 "Write to RO location has been detected";
|
||||
RWOD 1 "Read of WO location has been detected";
|
||||
WRD 1 "Write to reserved location has been detected";
|
||||
RRD 1 "Read to reserved location has been detected";
|
||||
};
|
||||
|
||||
register GICD_SETSPI_NSR wo addr(dist, 0x40) "Set Non-secure SPI Pending Register" {
|
||||
_ 22 mbz;
|
||||
INTID 10 "The INTID of the SPI";
|
||||
};
|
||||
|
||||
register GICD_CLRSPI_NSR wo addr(dist, 0x48) "Clear Non-secure SPI Pending Register" {
|
||||
_ 22 mbz;
|
||||
INTID 10 "The INTID of the SPI";
|
||||
};
|
||||
|
||||
register GICD_SETSPI_SR wo addr(dist, 0x50) "Set Secure SPI Pending Register" {
|
||||
_ 22 mbz;
|
||||
INTID 10 "The INTID of the SPI";
|
||||
};
|
||||
|
||||
register GICD_CLRSPI_SR wo addr(dist, 0x58) "Clear Secure SPI Pending Register" {
|
||||
_ 22 mbz;
|
||||
INTID 10 "The INTID of the SPI";
|
||||
};
|
||||
|
||||
regarray GICD_IGROUPR addr(dist, 0x80)[32] "Interrupt Group Registers" type(uint32);
|
||||
|
||||
regarray GICD_ISENABLER addr(dist, 0x100)[32] "Interrupt Set-Enable Registers" type(uint32);
|
||||
|
||||
regarray GICD_ICENABLER addr(dist, 0x180)[32] "Interrupt Clear-Enable Registers" type(uint32);
|
||||
|
||||
regarray GICD_ISPENDR addr(dist, 0x200)[32] "Interrupt Set-Pending Registers" type(uint32);
|
||||
|
||||
regarray GICD_ICPENDR addr(dist, 0x280)[32] "Interrupt Clear-Pending Registers" type(uint32);
|
||||
|
||||
regarray GICD_ISACTIVER addr(dist, 0x300)[32] "Interrupt Set-Active Registers" type(uint32);
|
||||
|
||||
regarray GICD_ICACTIVER addr(dist, 0x380)[32] "Interrupt Clear-Active Registers" type(uint32);
|
||||
|
||||
regarray GICD_IPRIORITYR addr(dist, 0x400)[1020] "Interrupt Priority Registers" type(uint8);
|
||||
|
||||
regarray GICD_ITARGETSR addr(dist, 0x800)[255] "Interrupt Processor Targets Registers" type(uint32);
|
||||
|
||||
regarray GICD_ICFGR addr(dist, 0xC00)[64] "Interrupt Configuration Registers" type(uint32);
|
||||
|
||||
regarray GICD_IGRPMODR addr(dist, 0xD00)[32] "Interrupt Group Modifier Registers" type(uint32);
|
||||
|
||||
regarray GICD_NSACR addr(dist, 0xe00)[64] "Non-secure Access Control Registers" type(uint32);
|
||||
|
||||
|
||||
constants TargetFilterList width(2) "SGI forwarding" {
|
||||
CPUTargetList = 0b00 "Forward the interrupt to the CPU interfaces specified by GICD_SGIR.CPUTargetList.";
|
||||
PEAllTarget = 0b01 "Forward the interrupt to all CPU interfaces except that of the PE that requested the interrupt.";
|
||||
PEOnlyTarget = 0b10 "Forward the interrupt only to the CPU interface of the PE that requested the interrupt.";
|
||||
};
|
||||
|
||||
register GICD_SGIR wo addr(dist, 0xF00) "Software Generated Interrupt Register" {
|
||||
_ 6 mbz;
|
||||
TargetFilterList 2 type(TargetFilterList);
|
||||
CPUTargetList 8 "Forward to CPU interface bit N (only if TargetFilterList==CPUTargetList)";
|
||||
NSATT 1 "Required group of the SGI";
|
||||
_ 11 mbz;
|
||||
INTID 4 "INTID of the SGI to forward to the specified CPU interfaces";
|
||||
};
|
||||
|
||||
regarray GICD_CPENDSGIR addr(dist, 0xF10)[4] "SGI Clear-Pending Registers" type(uint32);
|
||||
|
||||
regarray GICD_SPENDSGIR addr(dist, 0xF20)[4] "SGI Set-Pending Registers" type(uint32);
|
||||
|
||||
register ICPIDR2 ro addr(dist, 0x0fe8) "Peripheral ID2 Register" {
|
||||
_ 24;
|
||||
ArchRev 4 "GIC architecture revision";
|
||||
_ 4;
|
||||
};
|
||||
|
||||
regarray GICD_IROUTER addr(dist, 0x6100)[1020] "Interrupt Routing Registers" {
|
||||
_ 24 mbz;
|
||||
Aff3 8 "Affinity level 3, least significant level field";
|
||||
Interrupt_Rouing_Mode 1 "Interrupt Routing Mode";
|
||||
_ 7 mbz;
|
||||
Aff2 8 "Affinity level 2";
|
||||
Aff1 8 "Affinity level 1";
|
||||
Aff0 8 "Affinity level 0, most significant level field";
|
||||
};
|
||||
|
||||
register GICD_PIDR2 ro addr(dist, 0xffe8) "Peripheral ID2 Register" {
|
||||
_ 24;
|
||||
ArchRev 4 "GIC architecture revision";
|
||||
_ 4;
|
||||
};
|
||||
};
|
||||
91
devices/gic_v3_redist.dev
Normal file
91
devices/gic_v3_redist.dev
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* gic_v3.dev
|
||||
*
|
||||
* DESCRIPTION: GIC v3 architecture definitions
|
||||
*
|
||||
* See:
|
||||
* GIC v3 Architecture Specification
|
||||
*/
|
||||
|
||||
device gic_v3_redist msbfirst (addr redist) "GIC v3 Redistributor" {
|
||||
register GICR_CTLR also addr(redist, 0x0000) "Redistributor Control Register" {
|
||||
UWP 1 ro "Upstream Write Pending";
|
||||
_ 4 mbz;
|
||||
DPG1S 1 "Disable Processor selection for Group 1 Secure interrupts";
|
||||
DPG1NS 1 "Disable Processor selection for Group 1 Non-secure interrupts";
|
||||
DPG0 1 "Disable Processor selection for Group 0 interrupts";
|
||||
_ 20 mbz;
|
||||
RWP 1 "Register Write Pending";
|
||||
_ 2 mbz;
|
||||
Enable_LPIs 1 "LPI support is enabled";
|
||||
};
|
||||
|
||||
register GICR_IIDR ro addr(redist, 0x0004) "Redistributor Implementer Identification Register" {
|
||||
ProductID 8 "Product identifier";
|
||||
_ 4 mbz;
|
||||
Variant 4 "Variant number";
|
||||
Revision 4 "Revision number";
|
||||
Implementer 12 "JEP106 code of implementing company";
|
||||
};
|
||||
|
||||
register GICR_TYPER ro addr(redist, 0x0008) "Redistributor Type Register" {
|
||||
Affinity_Value 32 "The identity of the PE associated with this Redistributor";
|
||||
_ 6 mbz;
|
||||
CommonLPIAff 2 "The affinity level at which Redistributors share a LPI Configuration table";
|
||||
Processor_Number 16 "A unique identifier for the PE";
|
||||
_ 2 mbz;
|
||||
DPGS 1 "Implementation supports LPIs";
|
||||
Last 1 "Implementation supports LPIs";
|
||||
DirectLPI 1 "Implementation supports LPIs";
|
||||
_ 1 mbz;
|
||||
VLPIS 1 "Implementation supports LPIs";
|
||||
PLPIS 1 "Implementation supports LPIs";
|
||||
};
|
||||
|
||||
register GICR_STATUSR addr(redist, 0x0010) "Error Reporting Status Register" {
|
||||
_ 28 mbz;
|
||||
WROD 1 "Write to RO location has been detected";
|
||||
RWOD 1 "Read of WO location has been detected";
|
||||
WRD 1 "Write to reserved location has been detected";
|
||||
RRD 1 "Read to reserved location has been detected";
|
||||
};
|
||||
|
||||
register GICR_WAKER addr(redist, 0x0014) "Redistributor Wake Register" {
|
||||
IMP_DEF2 1 "Implementation Defined";
|
||||
_ 28 mbz;
|
||||
ChildrenAsleep 1 ro "Indicates whether the connected PE is quiescent";
|
||||
ProcessorSleep 1 "Indicates whether the Redistributor can assert the WakeRequest signal";
|
||||
IMP_DEF1 1 "Implementation Defined";
|
||||
};
|
||||
|
||||
register GICR_IGROUPR0 addr(redist, 0x10080) "Interrupt Group Register 0" type(uint32);
|
||||
|
||||
register GICR_ISENABLER0 addr(redist, 0x10100) "Interrupt Set-Enable Register 0" type(uint32);
|
||||
|
||||
register GICR_ICENABLER0 addr(redist, 0x10180) "Interrupt Clear-Enable Register 0" type(uint32);
|
||||
|
||||
register GICR_ISPENDR0 addr(redist, 0x10200) "Interrupt Set-Pending Register 0" type(uint32);
|
||||
|
||||
register GICR_ICPENDR0 addr(redist, 0x10280) "Interrupt Clear-Pending Register 0" type(uint32);
|
||||
|
||||
register GICR_ISACTIVER0 addr(redist, 0x10300) "Interrupt Set-Active Register 0" type(uint32);
|
||||
|
||||
register GICR_ICACTIVER0 addr(redist, 0x10380) "Interrupt Clear-Active Register 0" type(uint32);
|
||||
|
||||
regarray GICR_IPRIORITYR0 addr(redist, 0x10400)[8] "Interrupt Priority Registers" type(uint32);
|
||||
|
||||
register GICR_ICFGR0 addr(redist, 0x10c00) "SGI Configuration Register" type(uint32);
|
||||
register GICR_ICFGR1 addr(redist, 0x10c04) "PPI Configuration Register" type(uint32);
|
||||
|
||||
register GICR_IGRPMODR0 addr(redist, 0x10d00) "Interrupt Group Modifier Register 0" type(uint32);
|
||||
|
||||
register GICR_NSACR0 addr(redist, 0x10e00) "Non-secure Access Control Register" type(uint32);
|
||||
};
|
||||
85
devices/hpet.dev
Normal file
85
devices/hpet.dev
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2007 - 2018, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* hpet.dev
|
||||
*
|
||||
* DESCRIPTION: Intel 631xESB/632xESB I/O Controller Hub --
|
||||
* High-Precision Event Timer Registers
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 26, "High-Precision Event Timer Registers".
|
||||
* See also, Intel's "IA-PC HPET (High Precision Event Timers)
|
||||
* Specification", Revision 1.0a, October 2004.
|
||||
*/
|
||||
|
||||
// device device_name leastSignBitFirst
|
||||
device hpet lsbfirst ( addr base ) "High-Precision Event Timer" {
|
||||
// 26.1.1
|
||||
register gcap_id ro addr(base, 0x0) "General Capabilities and Identification" {
|
||||
rev_id 8 "Revision Identification";
|
||||
num_tim_cap 5 "Number of Timers";
|
||||
count_size_cap 1 "Counter Size";
|
||||
_ 1 mbz;
|
||||
leg_rt_cap 1 "Legacy Replacement Rout Capable";
|
||||
vendor_id_cap 16 "Vendor ID";
|
||||
counter_clk_per_cap 32 "Main Counter Tick Period";
|
||||
};
|
||||
|
||||
// 26.1.2 register name attribute space(, ) "description"
|
||||
|
||||
register gen_conf rw addr(base, 0x10) "General Configuration" {
|
||||
enable_cnf 1 "Overall Enable";
|
||||
leg_rt_cnf 1 "Legacy Replacement Rout";
|
||||
_ 62 mbz;
|
||||
};
|
||||
|
||||
// 26.1.3
|
||||
register gintr_sta rw addr(base, 0x20) "General Interrupt Status" {
|
||||
t00_int_sts 1 "Timer 0 interrupt active";
|
||||
t01_int_sts 1 "Timer 1 interrupt active";
|
||||
t02_int_sts 1 "Timer 2 interrupt active";
|
||||
_ 61 mbz;
|
||||
};
|
||||
|
||||
// 26.1.4
|
||||
register main_cnt rw addr(base, 0xf0) "Main Counter Value" type(uint64);
|
||||
|
||||
// 26.1.5
|
||||
regtype tim_conf "Timer Configuration and Capabilities" {
|
||||
_ 1 mbz;
|
||||
timer_int_type_cnf 1 "Timer Interrupt Type (0:edge-triggered , 1:level-triggered)";
|
||||
timer_int_enb_cnf 1 "Timer Interrupt Enable";
|
||||
timer_type_cnf 1 "Timer Type (0: non-periodic , 1:periodic)";
|
||||
timer_per_int_cap 1 "Periodic Interrupt Capability";
|
||||
timer_size_cap 1 "Timer Size (0:32 bits , 1:64 bits)";
|
||||
timer_val_set_cnf 1 "Timer Value Set (for periodic mode)";
|
||||
_ 1 mbz;
|
||||
timer_32mode_cnf 1 "Timer 32-bit mode (1 so that 64 behaves as 32)";
|
||||
timer_int_rout_cnf 5 "Interrupt Route (indicates routing to I/O apic)";
|
||||
timer_fsb_enb_cnf 1 "FSB Interrupt Enable";
|
||||
timer_fsb_int_delv_cap 1 "FSB Interrupt Delivery (1: FSB is supported)";
|
||||
_ 16 mbz;
|
||||
timer_int_rout_cap 32 "Interrupt Routing Capability (To which interrupts can the I/O Apic be routed)";
|
||||
};
|
||||
|
||||
|
||||
regtype tim_fsb_int_route "Timer FSB Interrupt Route"{
|
||||
timer_fsb_int_val 32 "Timer FSB Interrupt Value";
|
||||
timer_fsb_int_addr 32 "Timer FSB Interrupt Address";
|
||||
};
|
||||
|
||||
regarray timers_config_reg rw addr(base,0x100) [32 ; 0x20]
|
||||
"Timer N Configuration Register" type(tim_conf);
|
||||
|
||||
regarray timers_comparator_reg rw addr(base,0x108) [32 ; 0x20]
|
||||
"Timer N Comparator Value Register" type(uint64);
|
||||
|
||||
regarray timers_fsb_int_route_reg rw addr(base,0x110) [32 ; 0x20]
|
||||
"Timer N FSB Interrupt Route" type(tim_fsb_int_route);
|
||||
};
|
||||
69
devices/ht_config.dev
Normal file
69
devices/ht_config.dev
Normal file
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2008, 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ht_config.dev
|
||||
*
|
||||
* DESCRIPTION: HyperTransport Configuration
|
||||
*
|
||||
* This is derived from the "BIOS and Kernel Developer's Guide (BKDG)
|
||||
* for AMD Family 10h Processors", Chapter 3, "Registers".
|
||||
*/
|
||||
|
||||
device ht_config lsbfirst ( pci base ) "HyperTransport Configuration" {
|
||||
//
|
||||
// Section 3.3: Function 0 HyperTransport Technology Configuration
|
||||
// Registers
|
||||
//
|
||||
|
||||
constants rtdest "Routing Destination" {
|
||||
self = 0b1 "Route to this node";
|
||||
link0_0 = 0b10 "Route to link 0, sublink 0";
|
||||
link1_0 = 0b100 "Route to link 1, sublink 0";
|
||||
link2_0 = 0b1000 "Route to link 2, sublink 0";
|
||||
link3_0 = 0b10000 "Route to link 3, sublink 0";
|
||||
link0_1 = 0b100000 "Route to link 0, sublink 1";
|
||||
link1_1 = 0b1000000 "Route to link 1, sublink 1";
|
||||
link2_1 = 0b10000000 "Route to link 2, sublink 1";
|
||||
link3_1 = 0b100000000 "Route to link 3, sublink 1";
|
||||
};
|
||||
|
||||
regtype rtnode "Routing Table" {
|
||||
rqrte 9 type(rtdest) "Request Route";
|
||||
rprte 9 type(rtdest) "Response Route";
|
||||
bcrte 9 type(rtdest) "Broadcast Route";
|
||||
_ 5;
|
||||
};
|
||||
|
||||
regarray rtnodes rw pci( base, 0x40 ) [8] "Routing Table Nodes" type(rtnode);
|
||||
|
||||
register nodeid rw pci( base, 0x60 ) "Node ID" {
|
||||
nodeid 3 "This Node ID";
|
||||
_ 1;
|
||||
nodecnt 3 "Node Count";
|
||||
_ 1;
|
||||
sbnode 3 "HyperTransport I/O Hub Node ID";
|
||||
_ 1;
|
||||
lknode 3 "Lock Controller Node ID";
|
||||
_ 1;
|
||||
cpucnt 5 "CPU Count";
|
||||
_ 3 mbz;
|
||||
_ 8;
|
||||
};
|
||||
|
||||
register unitid rw pci( base, 0x64 ) "Unit ID" {
|
||||
cpuunit 2 "CPU Unit ID";
|
||||
_ 2;
|
||||
mctunit 2 "Memory Controller Unit ID";
|
||||
hbunit 2 "Host Bridge Unit ID";
|
||||
sblink 3 "Southbridge I/O Hub Link ID";
|
||||
_ 21;
|
||||
};
|
||||
|
||||
// ...
|
||||
};
|
||||
698
devices/ia32.dev
Normal file
698
devices/ia32.dev
Normal file
@ -0,0 +1,698 @@
|
||||
/*
|
||||
* Copyright (c) 2008, 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ia32.dev
|
||||
*
|
||||
* DESCRIPTION: ia32 Architectural definitions, including Architectural MSRs
|
||||
*
|
||||
* Numbers in comments refer to the Intel Architecture Manual, August 2007
|
||||
*/
|
||||
|
||||
device ia32 lsbfirst () "ia32 / Intel64 core architecture" {
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Exception vectors
|
||||
* ***********************
|
||||
*/
|
||||
constants exc_vec width(8) "Exception vectors" {
|
||||
vec_de = 0 "divide error";
|
||||
vec_db = 1 "debug exception";
|
||||
vec_nmi = 2 "non-maskable interrupt";
|
||||
vec_bp = 3 "breakpoint";
|
||||
vec_of = 4 "overflow";
|
||||
vec_br = 5 "BOUND range exceeded";
|
||||
vec_ud = 6 "invalid opcode";
|
||||
vec_nm = 7 "device not available";
|
||||
|
||||
vec_df = 8 "double fault";
|
||||
vec_cso = 9 "coprocessor segment overrun";
|
||||
vec_ts = 10 "invalid TSS";
|
||||
vec_np = 11 "segment not present";
|
||||
vec_ss = 12 "stack fault";
|
||||
vec_gp = 13 "general protection fault";
|
||||
vec_pf = 14 "page fault";
|
||||
// 15 reserved to intel
|
||||
|
||||
vec_mf = 16 "x87 FPU floating-point error";
|
||||
vec_ac = 17 "alignment check";
|
||||
vec_mc = 18 "machine check";
|
||||
vec_xf = 19 "SIMD floating-point exception";
|
||||
};
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Address space for model-Specific registers
|
||||
* ***********************
|
||||
*/
|
||||
space msr(index) valuewise "Model-specific Registers";
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Architectural MSRs
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 7.11.5
|
||||
register mon_filter_size msr(0x06) "Monitor/Mwait filter size" type(uint64);
|
||||
|
||||
// Appendix B.1
|
||||
register platform_id ro msr(0x17) "Platform ID" {
|
||||
_ 50;
|
||||
id 3 "platform id";
|
||||
_ 11;
|
||||
};
|
||||
|
||||
register apic_base msr(0x1b) "APIC base" {
|
||||
_ 8;
|
||||
bsp 1 ro "BSP flag";
|
||||
_ 2;
|
||||
global 1 rw "APIC global enable";
|
||||
base 52 rw "APIC base";
|
||||
};
|
||||
|
||||
register feature_cntl rw msr(0x3a) "Feature control" {
|
||||
lock 1 rwo "lock";
|
||||
vmxinsmx 1 rwl "enable VMX inside SMX";
|
||||
vmxoutsmx 1 rwl "enable VMX outside SMX";
|
||||
_ 5;
|
||||
senter_loc 7 rwl "SENTER local function";
|
||||
senter_glob 1 rwl "SENTER global enable";
|
||||
_ 48;
|
||||
};
|
||||
|
||||
register vmx_basic ro msr(0x480) "Basic VMX Capabilities" {
|
||||
vmcs_rev_id 31 "VMCS Revision Identifier";
|
||||
_ 1 mbz;
|
||||
region_size 13 "Bytes that should be allocated for VMXON and VMCS regions";
|
||||
_ 3;
|
||||
paddr_width 1 "Physical address width Limited to 32 Bits";
|
||||
dual_mon 1 "Dual-monitor treatment supported";
|
||||
mem_type 4 "Memory tpe used to access VMCS with VMREAD/VMWRITE";
|
||||
instr_info_io 1 "INS/OUTS info is reported in VM-exit instruction-information";
|
||||
ctls_clear 1 "Controls that default to 1 may be cleared to 0";
|
||||
_ 8;
|
||||
};
|
||||
|
||||
// Capability Reporting Registers for VMX Controls
|
||||
register vmx_pinbased_ctls ro msr(0x481) "Pin-based Controls" type(uint64);
|
||||
register vmx_ppbased_ctls ro msr(0x482) "Primary Processor-based Controls" type(uint64);
|
||||
register vmx_exit_ctls ro msr(0x483) "VM-exit Controls" type(uint64);
|
||||
register vmx_entry_ctls ro msr(0x484) "VM-entry Controls" type(uint64);
|
||||
register vmx_spbased_ctls ro msr(0x48b) "Secondary Processor-based Controls" type(uint64);
|
||||
|
||||
// Capability Reporting Registers for VMX Flex Controls
|
||||
register vmx_true_pinbased_ctls ro msr(0x48d) "Pin-based Flex Controls" type(uint64);
|
||||
register vmx_true_ppbased_ctls ro msr(0x48e) "Primary Processor-based Flex Controls" type(uint64);
|
||||
register vmx_true_exit_ctls ro msr(0x48f) "VM-exit Flex Controls" type(uint64);
|
||||
register vmx_true_entry_ctls ro msr(0x490) "VM-entry Flex Controls" type(uint64);
|
||||
|
||||
// Capability Reporting Registers of CR0 and CR4 bits
|
||||
register vmx_cr0_fixed0 ro msr(0x486) "CR0 Bits Fixed to 0" type(uint64);
|
||||
register vmx_cr0_fixed1 ro msr(0x487) "CR0 Bits Fixed to 1" type(uint64);
|
||||
register vmx_cr4_fixed0 ro msr(0x488) "CR4 Bits Fixed to 0" type(uint64);
|
||||
register vmx_cr4_fixed1 ro msr(0x489) "CR4 Bits Fixed to 1" type(uint64);
|
||||
|
||||
register vmx_ept_vpid ro msr(0x48c) "EPT and VPID Capabilities" {
|
||||
eot 1 "Support execute-only translation";
|
||||
_ 5;
|
||||
pwl4 1 "Support page-walk length of 4";
|
||||
_ 1;
|
||||
ucmt 1 "Support uncacheable memory type";
|
||||
_ 5;
|
||||
wbmt 1 "Support write-back memory type";
|
||||
_ 1;
|
||||
ps21 1 "Support EPT PDE mapping to 2MB page";
|
||||
ps30 1 "Support EPT PDE mapping to 1GB page";
|
||||
_ 2;
|
||||
invept_instr 1 "Support the instruction INVEPT";
|
||||
ept_adf 1 "Support EPT accessed and dirty flags";
|
||||
_ 3;
|
||||
invept_sct 1 "Support single-context INVEPT type";
|
||||
invept_act 1 "Support all-context INVEPT type";
|
||||
_ 5;
|
||||
invvpid_instr 1 "Support the instruction INVVPID";
|
||||
_ 7;
|
||||
invvpid_iat 1 "Support individual-address INVVPID type";
|
||||
invvpid_sct 1 "Support single-context INVVPID type";
|
||||
invvpid_act 1 "Support all-context INVVPID type";
|
||||
invvpid_scrgt 1 "Support single-context-retaining-globals INVVPID type";
|
||||
_ 20;
|
||||
};
|
||||
|
||||
register bios_updt_trig rw msr(0x79) "BIOS update trigger" type(uint64);
|
||||
register bios_sign_id rw msr(0x8b) "BIOS update signature" type(uint64);
|
||||
register smm_monitor_ctl rw msr(0x9b) "SMM Monitor config" type(uint64);
|
||||
|
||||
register misc_enable rw msr(0x1a0) "Enable misc. features" {
|
||||
fse 1 rw "Fast-Strings enable";
|
||||
_ 2;
|
||||
atcce 1 rw "Automatic thermal control circuit enable";
|
||||
_ 3;
|
||||
pma 1 ro "Performance monitoring available";
|
||||
_ 1;
|
||||
hpd 1 rw "Hardware prefetcher disable";
|
||||
feme 1 rw "FERR# multiplexing enable";
|
||||
btsu 1 ro "Branch trace storage unavailable";
|
||||
pebsu 1 ro "Precise event-based sampling unavailable";
|
||||
tm2e 1 rw "Thermal monitor 2 enable";
|
||||
_ 2;
|
||||
eiste 1 rw "Enhanced Intel SpeedStep tech enable";
|
||||
_ 1;
|
||||
emfsm 1 rw "Enable monitor FSM";
|
||||
aclpd 1 rw "Adjacent cache line prefetch disable";
|
||||
eistsl 1 rwo "Enhanced SpeedStep select lock";
|
||||
_ 1;
|
||||
lcmax 1 rw "Limit CPUID max val";
|
||||
xmd 1 rw "xTPR message disable";
|
||||
_ 10;
|
||||
xdbd 1 rw "XD bit disable";
|
||||
_ 2;
|
||||
dcupd 1 rw "DCU prefetcher disable";
|
||||
idad 1 rw "IDA disable";
|
||||
ippd 1 rw "IP prefetcher disable";
|
||||
_ 24;
|
||||
};
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Machine check MSRs
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 14.8.3
|
||||
register p5_mc_addr msr(0x0) "P5 MC ADDR" type(uint64);
|
||||
register p5_mc_type msr(0x1) "P5 MC Type" type(uint64);
|
||||
|
||||
// 14.3.1.1
|
||||
register mcg_cap ro msr(0x179) "Global machine check capabilities" {
|
||||
count 8 "Num. reporting banks available";
|
||||
ctl_p 1 "Implements MCG_CTL MSR";
|
||||
exp_p 1 "Implements extended MC regs";
|
||||
_ 1;
|
||||
tes_p 1 "Threshold-based error status present";
|
||||
_ 4;
|
||||
ext_cnt 8 "Num. extended MC regs present";
|
||||
_ 40;
|
||||
};
|
||||
|
||||
// 14.3.1.2
|
||||
register mcg_status msr(0x17a) "Global machine check status" {
|
||||
ripv 1 ro "Restart IP valid";
|
||||
eipv 1 ro "Error IP valid";
|
||||
mcip 1 rw "Machine check in progress";
|
||||
_ 61;
|
||||
};
|
||||
|
||||
// 14.3.1.3
|
||||
constants mcg_ctl_val width(64) "Global MC control values" {
|
||||
mc_enable = 1s;
|
||||
mc_disable = 0x0;
|
||||
};
|
||||
register mcg_ctl rw msr(0x17b) "Global machine check control"
|
||||
type(mcg_ctl_val);
|
||||
|
||||
// 14.3.2.5
|
||||
register mcg_rax rwzc msr(0x180) "State of RAX at MC" type(uint64);
|
||||
register mcg_rbx rwzc msr(0x181) "State of RBX at MC" type(uint64);
|
||||
register mcg_rcx rwzc msr(0x182) "State of RCX at MC" type(uint64);
|
||||
register mcg_rdx rwzc msr(0x183) "State of RDX at MC" type(uint64);
|
||||
register mcg_rsi rwzc msr(0x184) "State of RSI at MC" type(uint64);
|
||||
register mcg_rdi rwzc msr(0x185) "State of RDI at MC" type(uint64);
|
||||
register mcg_rbp rwzc msr(0x186) "State of RBP at MC" type(uint64);
|
||||
register mcg_rsp rwzc msr(0x187) "State of RSP at MC" type(uint64);
|
||||
register mcg_rflags rwzc msr(0x188) "State of RFLAGS at MC" type(uint64);
|
||||
register mcg_rip rwzc msr(0x189) "State of RIP at MC" type(uint64);
|
||||
register mcg_misc rwzc msr(0x18a) "Page fault/assist during DS" type(uint64);
|
||||
register mcg_r8 rwzc msr(0x190) "State of R8 at MC" type(uint64);
|
||||
register mcg_r9 rwzc msr(0x191) "State of R9 at MC" type(uint64);
|
||||
register mcg_r10 rwzc msr(0x192) "State of R10 at MC" type(uint64);
|
||||
register mcg_r11 rwzc msr(0x193) "State of R11 at MC" type(uint64);
|
||||
register mcg_r12 rwzc msr(0x194) "State of R12 at MC" type(uint64);
|
||||
register mcg_r13 rwzc msr(0x195) "State of R13 at MC" type(uint64);
|
||||
register mcg_r14 rwzc msr(0x196) "State of R14 at MC" type(uint64);
|
||||
register mcg_r15 rwzc msr(0x197) "State of R15 at MC" type(uint64);
|
||||
|
||||
// 14.3.2
|
||||
constants tbtrk "Threshold-based error status" {
|
||||
notrack = 0b00 "No hw status tracking";
|
||||
green = 0b01 "current status green";
|
||||
yellow = 0b10 "current status yellow";
|
||||
};
|
||||
|
||||
regarray mc_ctl rw msr(0x400)[5; 4] "Machine check control" type(uint64);
|
||||
regarray mc_status rwzc msr(0x401)[5; 4] "Machine check unit status" {
|
||||
mca_ec 16 "MCA error code";
|
||||
ms_ec 16 "Model-specific error code";
|
||||
other 21 "Other information";
|
||||
tbes 2 type(tbtrk) "Threshold-based error status";
|
||||
_ 2 mbz; // Seems to need to be written zero to
|
||||
// work (otherwise a GPF) but doesn't
|
||||
// always read as zero on
|
||||
// some AMD-based processors.
|
||||
pcc 1 "Processor context corrupt";
|
||||
addrv 1 "MCi_ADDR register valid";
|
||||
miscv 1 "MCi_MISC register valid";
|
||||
en 1 "Error enabled";
|
||||
uc 1 "Error uncorrected";
|
||||
over 1 "Error overflow";
|
||||
val 1 "MCi_STATUS register valid";
|
||||
};
|
||||
regarray mc_addr rwzc msr(0x402)[5; 4] "Machine check addr" type(uint64);
|
||||
regarray mc_misc rwzc msr(0x403)[5; 4] "Machine check misc" type(uint64);
|
||||
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Debugging and performance
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 18.5.1
|
||||
register debugctl rw msr(0x1d9) "Debug control" {
|
||||
lbr 1 "Last branch/int/exception";
|
||||
btf 1 "Single-step on branches";
|
||||
_ 4;
|
||||
tr 1 "Trace messages enable";
|
||||
bts 1 "Branch trace store";
|
||||
btint 1 "Branch trace interrupt";
|
||||
bts_off_os 1 "BTS off in OS";
|
||||
bts_off_usr 1 "BTS off in user code";
|
||||
freeze_lbrs_on_pmi 1;
|
||||
freeze_perfmon_on_pmi 1;
|
||||
_ 19;
|
||||
};
|
||||
|
||||
// 18.10
|
||||
register tsc msr(0x10) "Time stamp counter" type(uint64);
|
||||
|
||||
// 18.12.1.1
|
||||
regtype perfevtsel "Perfmon event select" {
|
||||
evsel 8 "Event select";
|
||||
umask 8 "Unit mask";
|
||||
usr 1 "User mode";
|
||||
os 1 "OS mode";
|
||||
e 1 "Edge detect";
|
||||
pc 1 "Pin control";
|
||||
intr 1 "APIC interrupt enable";
|
||||
_ 1;
|
||||
en 1 "Enable counters";
|
||||
inv 1 "Invert counter mask";
|
||||
cmask 8 "Counter mask";
|
||||
_ 32;
|
||||
};
|
||||
register pmc0 msr(0xc1) "Perfmon counter 0" type(uint64);
|
||||
register pmc1 msr(0xc2) "Perfmon counter 1" type(uint64);
|
||||
register perfevtsel0 also msr(0x186) "Perfmon event select 0" type(perfevtsel);
|
||||
register perfevtsel1 also msr(0x187) "Perfmon event select 1" type(perfevtsel);
|
||||
|
||||
// 18.14.1
|
||||
regtype fixed_ctr "Fixed counter" {
|
||||
v 40 "Value";
|
||||
_ 24;
|
||||
};
|
||||
register fixed_ctr0 rw msr(0x309) "Fixed-funct. counter 0" type(fixed_ctr);
|
||||
register fixed_ctr1 rw msr(0x30a) "Fixed-funct. counter 1" type(fixed_ctr);
|
||||
register fixed_ctr2 rw msr(0x30b) "Fixed-funct. counter 2" type(fixed_ctr);
|
||||
|
||||
//345 perf_capabilities
|
||||
|
||||
//18.12.2.1
|
||||
register fixed_ctr_ctl msr(0x38d) "Fixed counter control" {
|
||||
enos0 1 "Enable 0 for OS";
|
||||
enusrs0 1 "Enable 0 for user";
|
||||
_ 1;
|
||||
pmi0 1 "Enable PMI on overflow 0";
|
||||
enos1 1 "Enable 1 for OS";
|
||||
enusrs1 1 "Enable 1 for user";
|
||||
_ 1;
|
||||
pmi1 1 "Enable PMI on overflow 1";
|
||||
enos2 1 "Enable 2 for OS";
|
||||
enusrs2 1 "Enable 2 for user";
|
||||
_ 1;
|
||||
pmi2 1 "Enable PMI on overflow 2";
|
||||
_ 52;
|
||||
};
|
||||
|
||||
regtype perf_global "Perfmon global status/overflow" {
|
||||
pmc0 1 "PMC0 overflow";
|
||||
pmc1 1 "PMC1 overflow";
|
||||
_ 30;
|
||||
ctr0 1 "Fixed CTR0 overflow";
|
||||
ctr1 1 "Fixed CTR1 overflow";
|
||||
ctr2 1 "Fixed CTR2 overflow";
|
||||
_ 27;
|
||||
ovfbuf 1 "Overflow buffer";
|
||||
condchgd 1 "Condition changed";
|
||||
};
|
||||
|
||||
register perf_global_status ro msr(0x38e) "Perfmon global status"
|
||||
type(perf_global);
|
||||
register perf_global_over rwzc msr(0x390) "Perfmon global overlflow control"
|
||||
type(perf_global);
|
||||
|
||||
register perf_global_ctrl msr(0x38f) "Perfmon global control" {
|
||||
pmc0 1 "PMC0 enable";
|
||||
pmc1 1 "PMC1 enable";
|
||||
_ 30;
|
||||
ctr0 1 "Fixed CTR0 enable";
|
||||
ctr1 1 "Fixed CTR1 enable";
|
||||
ctr2 1 "Fixed CTR2 enable";
|
||||
_ 29;
|
||||
};
|
||||
|
||||
// 18.14.4.1
|
||||
register pebs_enable rw msr(0x3f1) "Precise event-based sampling enable" {
|
||||
en 1 "enable";
|
||||
_ 63;
|
||||
};
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Long mode operation
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 4.13
|
||||
register efer msr(0xc0000080) "Extended features enable" {
|
||||
sce 1 rw "SYSCALL enable";
|
||||
_ 7;
|
||||
lme 1 rw "Long mode enable";
|
||||
_ 1;
|
||||
lma 1 rw "Long mode active"; // Should be rw, but must be
|
||||
// preserved in practice!
|
||||
nxe 1 rw "No-execute enable";
|
||||
_ 52;
|
||||
};
|
||||
|
||||
// 4.8.8
|
||||
register star msr(0xc0000081) "Syscall target address" {
|
||||
_ 32;
|
||||
call 16 "SYSCALL CS and SS";
|
||||
ret 16 "SYSRET CS and SS";
|
||||
};
|
||||
|
||||
register lstar msr(0xc0000082) "Long mode Syscall target address"
|
||||
type(uint64);
|
||||
|
||||
register cstar msr(0xc0000083) "Compatibility mode Syscall target address"
|
||||
type(uint64);
|
||||
|
||||
register fmask msr(0xc0000084) "SYSCALL EFLAGS mask" {
|
||||
v 32 "Value";
|
||||
_ 32;
|
||||
};
|
||||
register fs_base msr(0xc0000100) "FS base" type(uint64);
|
||||
register gs_base msr(0xc0000101) "GS base" type(uint64);
|
||||
register kernel_gs_base msr(0xc0000102) "Swap target of GS base" type(uint64);
|
||||
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Memory type range registers
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 10.11.1
|
||||
register mtrrcap ro msr(0xfe) "MTRR Capabilities" {
|
||||
vcnt 8 "Number of variable range registers";
|
||||
fix 1 "Fixed range registers supported";
|
||||
_ 1;
|
||||
wc 1 "Write-combining memory type supported";
|
||||
_ 53;
|
||||
};
|
||||
|
||||
// 10.11.2
|
||||
register mtrr_def_type rw msr(0x2ff) "MTRR type definition" {
|
||||
tpe 8 "Default memory type";
|
||||
_ 2;
|
||||
fe 1 "Fixed-range MTRRs enable/disable";
|
||||
e 1 "MTRR enable/disable";
|
||||
_ 52;
|
||||
};
|
||||
|
||||
regarray mtrr_physbase rw msr(0x200)[8;2] "MTRR physical base" {
|
||||
tpe 8 "Type";
|
||||
_ 4;
|
||||
base 52 "Physical base address";
|
||||
};
|
||||
|
||||
regarray mtrr_physmask rw msr(0x201)[8;2] "MTRR physical mask" {
|
||||
_ 11;
|
||||
v 1 "Valid";
|
||||
mask 52 "Physical mask";
|
||||
};
|
||||
|
||||
register mtrr_fix64k_00000 rw msr(0x250) "MTRR fix64k_00000" type(uint64);
|
||||
register mtrr_fix16k_80000 rw msr(0x258) "MTRR fix16k_80000" type(uint64);
|
||||
register mtrr_fix16k_a0000 rw msr(0x259) "MTRR fix16k_a0000" type(uint64);
|
||||
register mtrr_fix4k_c0000 rw msr(0x268) "MTRR fix4k_c0000" type(uint64);
|
||||
register mtrr_fix4k_c8000 rw msr(0x269) "MTRR fix4k_c8000" type(uint64);
|
||||
register mtrr_fix4k_d0000 rw msr(0x26a) "MTRR fix4k_d0000" type(uint64);
|
||||
register mtrr_fix4k_d8000 rw msr(0x26b) "MTRR fix4k_d8000" type(uint64);
|
||||
register mtrr_fix4k_e0000 rw msr(0x26c) "MTRR fix4k_e0000" type(uint64);
|
||||
register mtrr_fix4k_e8000 rw msr(0x26d) "MTRR fix4k_e8000" type(uint64);
|
||||
register mtrr_fix4k_f0000 rw msr(0x26e) "MTRR fix4k_f0000" type(uint64);
|
||||
register mtrr_fix4k_f8000 rw msr(0x26f) "MTRR fix4k_f8000" type(uint64);
|
||||
|
||||
// 10.12
|
||||
constants pat_val "Page attribute table values" {
|
||||
uc = 0x00 "Uncacheable";
|
||||
wc = 0x01 "Write combining";
|
||||
wt = 0x04 "Write through";
|
||||
wp = 0x05 "Write protected";
|
||||
wb = 0x06 "Write back";
|
||||
ucd = 0x07 "Uncached";
|
||||
};
|
||||
register cr_pat rw msr(0x277) "Page attribute table control" {
|
||||
pa0 8 type(pat_val);
|
||||
pa1 8 type(pat_val);
|
||||
pa2 8 type(pat_val);
|
||||
pa3 8 type(pat_val);
|
||||
pa4 8 type(pat_val);
|
||||
pa5 8 type(pat_val);
|
||||
pa6 8 type(pat_val);
|
||||
pa7 8 type(pat_val);
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Power and thermal
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 13.2
|
||||
register mperf rw msr(0xe7) "Measured performance" type(uint64);
|
||||
register aperf rw msr(0xe8) "Actual performance" type(uint64);
|
||||
|
||||
// 13.3
|
||||
regtype perf_pnt "Performance point" {
|
||||
eist 16 "EIST transition target";
|
||||
_ 16;
|
||||
ida 1 "IDA disengage";
|
||||
_ 31;
|
||||
};
|
||||
register perf_ctl rw msr(0x198) "Performance control" type(perf_pnt);
|
||||
register perf_status ro msr(0x199) "Performance status" type(perf_pnt);
|
||||
|
||||
// 13.5.3
|
||||
register clock_modulation rw msr(0x19a) "Clock modulation" {
|
||||
_ 1;
|
||||
dc 2 "On-Demand clock modulation duty cycle (x12.5%)";
|
||||
en 1 "Enable";
|
||||
_ 60;
|
||||
};
|
||||
|
||||
// 13.5.5.2
|
||||
register therm_interrupt rw msr(0x19b) "Thermal monitor interrupt" {
|
||||
ht 1 "High-temperature enable";
|
||||
lt 1 "Low-temperature enable";
|
||||
prochot 1 "PROCHOT# enable";
|
||||
forcpr 1 "FORCEPR# enable";
|
||||
over 1 "Overheat enable";
|
||||
_ 3;
|
||||
tt1 7 "Thermal threshold 1 value";
|
||||
tt1int 1 "Thermal threshold 1 enable";
|
||||
tt2 7 "Thermal threshold 2 value";
|
||||
tt2int 1 "Thermal threshold 2 enable";
|
||||
_ 40;
|
||||
};
|
||||
register therm_status msr(0x19c) "Thermal status" {
|
||||
therm 1 ro "Status flag";
|
||||
thermlg 1 rwzc "Log flag";
|
||||
porf 1 ro "PROCHOT# or FORCEPR# asserted";
|
||||
porflg 1 rwzc "PROCHOT# or FORCEPR# log";
|
||||
cts 1 ro "Critical temperature status";
|
||||
ctslg 1 rwzc "Critical temperature log";
|
||||
tt1 1 ro "Thermal threshold status 1";
|
||||
tt1lg 1 rwzc "Thermal threshold log 1";
|
||||
tt2 1 ro "Thermal threshold status 2";
|
||||
tt2lg 1 rwzc "Thermal threshold log 2";
|
||||
_ 6;
|
||||
dig 7 ro "Digital readout in Celsius";
|
||||
_ 4;
|
||||
res 4 ro "Resolution in degrees Celsius";
|
||||
rv 1 ro "Reading valid";
|
||||
_ 32;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* AMD Performance Monitoring (Family 10h CPUs)
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
// 3.12
|
||||
regtype amd_perfevtsel "Perfmon event select" {
|
||||
evsel 8 "Event select";
|
||||
umask 8 "Unit mask";
|
||||
usr 1 "User mode";
|
||||
os 1 "OS mode";
|
||||
e 1 "Edge detect";
|
||||
_ 1;
|
||||
intr 1 "APIC interrupt enable";
|
||||
_ 1;
|
||||
en 1 "Enable counters";
|
||||
inv 1 "Invert counter mask";
|
||||
cmask 8 "Counter mask";
|
||||
evsel_hi 4 "Event select Hi";
|
||||
_ 4;
|
||||
guestonly 1 "Guest only counter";
|
||||
hostonly 1 "Host only counter";
|
||||
_ 22;
|
||||
};
|
||||
|
||||
// 10.1
|
||||
register perfctr0 msr(0xc0010004) "Performance Counter 0" type(uint64);
|
||||
register perfctr1 msr(0xc0010005) "Performance Counter 1" type(uint64);
|
||||
register perfctr2 msr(0xc0010006) "Performance Counter 2" type(uint64);
|
||||
register perfctr3 msr(0xc0010007) "Performance Counter 3" type(uint64);
|
||||
|
||||
// 10.2
|
||||
register amd_perfevtsel0 msr(0xc0010000) "Performance Event Select 0" type(amd_perfevtsel);
|
||||
register amd_perfevtsel1 msr(0xc0010001) "Performance Event Select 1" type(amd_perfevtsel);
|
||||
register amd_perfevtsel2 msr(0xc0010002) "Performance Event Select 2" type(amd_perfevtsel);
|
||||
register amd_perfevtsel3 msr(0xc0010003) "Performance Event Select 3" type(amd_perfevtsel);
|
||||
|
||||
/*
|
||||
* AMD Hardware Configuration (Athlon XP and Opteron)
|
||||
*
|
||||
* BIOS and Kernel Developer's Guide for AMD NPT Family 0fh Processors
|
||||
* BIOS and Kernel Developer's Guide for AMD NPT Family 10h Processors
|
||||
*/
|
||||
|
||||
// 14.2.1.3
|
||||
register amd_hwcr msr(0xc0010015) "Hardware Configuration" {
|
||||
smmlock 1 "SMM code lock";
|
||||
slowfence 1 "Slow SFENCE Enable";
|
||||
_ 1 mbz;
|
||||
tlbcachedis 1 "Cacheable Memory Disable";
|
||||
invd_wbinvd 1 "INVD to WBINVD conversion";
|
||||
_ 1;
|
||||
ffdis 1 "TLB flush filter disable";
|
||||
dislock 1 "Disable x86 LOCK prefix functionality";
|
||||
ignneem 1 "IGNNE port emulation enable";
|
||||
monmwaitdis 1 "MONITOR and MWAIT disable";
|
||||
monmwaituseren 1 "MONITOR/MWAIT user mode enable";
|
||||
limitcpuidstdmaxval 1 "Limit CPUID standard maximum value";
|
||||
hltxspcycen 1 "Halt-exit special bus cycle enable";
|
||||
smispcycdis 1 "SMI special bus cycle disable";
|
||||
rsmspcycdis 1 "RSM special bus cycle disable";
|
||||
ssedis 1 "SSE instructions disable";
|
||||
_ 1;
|
||||
wrap32dis 1 "32-bit address wrap disable";
|
||||
mcstatuswren 1 "Machine check status write enable";
|
||||
_ 1;
|
||||
iocfggpfault 1 "IO-space configuration cause GP fault";
|
||||
misalignssedis 1 "Misaligned SSE mode disable";
|
||||
_ 1;
|
||||
forceusrdwrszprb 1 "Force probes for upstream RdSized/WrSized";
|
||||
tscfreqsel 1 "TSC frequency select";
|
||||
_ 39;
|
||||
};
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Not yet typed in!
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
//600 ds_area
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* AND64/Intel64 paged virtual memory
|
||||
* ***********************
|
||||
*/
|
||||
|
||||
datatype vaddr_4k "4kB virtual address (long mode)" {
|
||||
ppo 12 "Physical page offset";
|
||||
pto 9 "Page-table offset";
|
||||
pdo 9 "Page-directory offset";
|
||||
pdpo 9 "Page-directory-pointer offset";
|
||||
pml4o 9 "Page-map-level-4 offset";
|
||||
se 16 "Sign extend";
|
||||
};
|
||||
|
||||
datatype pte_4k "Any-level page table entry, 4kB mapping" {
|
||||
p 1 "Present";
|
||||
rw 1 "Read/write";
|
||||
us 1 "User/Supervisor";
|
||||
pwt 1 "Page-level writethrough";
|
||||
pcd 1 "Page-level cache disable";
|
||||
a 1 "Accessed";
|
||||
d 1 "Dirty";
|
||||
ps 1 "Page size";
|
||||
g 1 "Global page";
|
||||
base 42 "Base address of next level";
|
||||
avail 12 "Available";
|
||||
nx 1 "Np execute";
|
||||
};
|
||||
|
||||
datatype pde_2M "Page directory entry, 2MB mapping" {
|
||||
p 1 "Present";
|
||||
rw 1 "Read/write";
|
||||
us 1 "User/Supervisor";
|
||||
pwt 1 "Page-level writethrough";
|
||||
pcd 1 "Page-level cache disable";
|
||||
a 1 "Accessed";
|
||||
d 1 "Dirty";
|
||||
ps 1 "Page size (must be 1)";
|
||||
g 1 "Global page";
|
||||
_ 3;
|
||||
pat 1 "Page-attribute table";
|
||||
_ 8;
|
||||
base 30 "Physical page base address";
|
||||
avail 12 "Available";
|
||||
nx 1 "Np execute";
|
||||
};
|
||||
|
||||
datatype pdpe_1G "Page directory ptr entry, 1GB mapping" {
|
||||
p 1 "Present";
|
||||
rw 1 "Read/write";
|
||||
us 1 "User/Supervisor";
|
||||
pwt 1 "Page-level writethrough";
|
||||
pcd 1 "Page-level cache disable";
|
||||
a 1 "Accessed";
|
||||
d 1 "Dirty";
|
||||
ps 1 "Page size (must be 1)";
|
||||
g 1 "Global page";
|
||||
_ 3;
|
||||
pat 1 "Page-attribute table";
|
||||
_ 16;
|
||||
base 22 "Physical page base address";
|
||||
avail 12 "Available";
|
||||
nx 1 "Np execute";
|
||||
};
|
||||
|
||||
register tsc_deadline rw msr(0x6e0) "TSC deadline" type(uint64);
|
||||
|
||||
};
|
||||
466
devices/imx8x/enet.dev
Normal file
466
devices/imx8x/enet.dev
Normal file
@ -0,0 +1,466 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* enet.dev
|
||||
*
|
||||
* DESCRIPTION: imx8x network device
|
||||
*
|
||||
* Number refer to i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual
|
||||
*/
|
||||
|
||||
device enet lsbfirst ( addr base ) "Imx8x enet controller" {
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.1/3630 Interrupt Event Register
|
||||
***************************************************************************/
|
||||
|
||||
register eir rw addr(base, 0x0004) "Interrupt Event Register" {
|
||||
rxb1 1 rw1c "Receive buffer interrupt class 1";
|
||||
rxf1 1 rw1c "Receive frame interrupt class 1";
|
||||
txb1 1 rw1c "Transmit buffer interrupt class 1";
|
||||
txf1 1 rw1c "Transmit frame interrupt class 1";
|
||||
rxb2 1 rw1c "Receive buffer interrupt class 2";
|
||||
rxf2 1 rw1c "Receive frame interrupt class 2";
|
||||
txb2 1 rw1c "Transmit buffer interrupt class 2";
|
||||
txf2 1 rw1c "Transmit frame interrupt class 2";
|
||||
_ 1 rsvd;
|
||||
parsrf 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRF].";
|
||||
parsrr 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRR].";
|
||||
_ 1 rsvd;
|
||||
rxflush0 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_0]";
|
||||
rxflush1 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_1]";
|
||||
rxflush2 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_2]";
|
||||
ts_timer 1 rw1c "TS_TIMER interrupt mask";
|
||||
ts_avail 1 rw1c "TS_AVAIL interrupt mask";
|
||||
wakeup 1 rw1c "WAKEUP interrupt mask";
|
||||
plr 1 rw1c "PLR interrupt mask";
|
||||
un 1 rw1c "UN interrupt mask";
|
||||
rl 1 rw1c "RL interrupt mask";
|
||||
lc 1 rw1c "LC interrupt mask";
|
||||
eberr 1 rw1c "EBERR interrupt mask";
|
||||
mii 1 rw1c "MII interrupt mask";
|
||||
rxb 1 rw1c "RXB interrupt mask";
|
||||
rxf 1 rw1c "RXF interrupt mask";
|
||||
txb 1 rw1c "TXB interrupt mask";
|
||||
txf 1 rw1c "TXF interrupt mask";
|
||||
gra 1 rw1c "GRA interrupt mask";
|
||||
babt 1 rw1c "BABT interrupt mask";
|
||||
babr 1 rw1c "BABR interrupt mask";
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.2/3634 Interrupt Mask Register
|
||||
***************************************************************************/
|
||||
|
||||
register eimr rw addr(base, 0x0008) "Interrupt Mask Register" {
|
||||
rxb1 1 "Receive buffer interrupt class 1";
|
||||
rxf1 1 "Receive frame interrupt class 1";
|
||||
txb1 1 "Transmit buffer interrupt class 1";
|
||||
txf1 1 "Transmit frame interrupt class 1";
|
||||
rxb2 1 "Receive buffer interrupt class 2";
|
||||
rxf2 1 "Receive frame interrupt class 2";
|
||||
txb2 1 "Transmit buffer interrupt class 2";
|
||||
txf2 1 "Transmit frame interrupt class 2";
|
||||
_ 1 rsvd;
|
||||
parsrf 1 "Interrupt mask bit corresponding to EIR[PARSRF].";
|
||||
parsrr 1 "Interrupt mask bit corresponding to EIR[PARSRR].";
|
||||
_ 1 rsvd;
|
||||
rxflush0 1 "Corresponds to interrupt source EIR[RXFLUSH_0]";
|
||||
rxflush1 1 "Corresponds to interrupt source EIR[RXFLUSH_1]";
|
||||
rxflush2 1 "Corresponds to interrupt source EIR[RXFLUSH_2]";
|
||||
ts_timer 1 "TS_TIMER interrupt mask";
|
||||
ts_avail 1 "TS_AVAIL interrupt mask";
|
||||
wakeup 1 "WAKEUP interrupt mask";
|
||||
plr 1 "PLR interrupt mask";
|
||||
un 1 "UN interrupt mask";
|
||||
rl 1 "RL interrupt mask";
|
||||
lc 1 "LC interrupt mask";
|
||||
eberr 1 "EBERR interrupt mask";
|
||||
mii 1 "MII interrupt mask";
|
||||
rxb 1 "RXB interrupt mask";
|
||||
rxf 1 "RXF interrupt mask";
|
||||
txb 1 "TXB interrupt mask";
|
||||
txf 1 "TXF interrupt mask";
|
||||
gra 1 "GRA interrupt mask";
|
||||
babt 1 "BABT interrupt mask";
|
||||
babr 1 "BABR interrupt mask";
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.3/3638
|
||||
***************************************************************************/
|
||||
|
||||
register rdar rw addr(base, 0x0010) "Receive Descriptor Active Register ring0" {
|
||||
_ 24 rsvd;
|
||||
rdar 1 "Receive Descriptor Active";
|
||||
_ 7 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.3/3638
|
||||
***************************************************************************/
|
||||
|
||||
register tdar rw addr(base, 0x0014) "Transmit Descriptor Active Register ring0" {
|
||||
_ 24 rsvd;
|
||||
tdar 1 "Transmit Descriptor Active";
|
||||
_ 7 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.5/3640 Ethernet control register
|
||||
***************************************************************************/
|
||||
|
||||
register ecr rw addr(base, 0x0024) "Control register" {
|
||||
reset 1 "Ethernet MAC Reset";
|
||||
etheren 1 "Ethernet enable";
|
||||
magicen 1 "Magic packet detection enable";
|
||||
sleep 1 "Sleep Mode enable";
|
||||
en1588 1 "EN1588 Enable";
|
||||
speed 1 "Select between 10/100 Mbit (0) and 1000 Mbit (1)";
|
||||
dbgen 1 "Debug enable";
|
||||
_ 1 rsvd;
|
||||
dbswp 1 "Descriptor Byte Swapping Enable";
|
||||
svlanen 1 "S-VLAN enable";
|
||||
vlanuse2nd 1 "VLAN use second tag";
|
||||
svlandbl 1 "S-VLAN double tag";
|
||||
_ 4 rsvd;
|
||||
txc_dly 1 "Transmit clock delay";
|
||||
rxc_dly 1 "Receive clock delay";
|
||||
_ 14 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.6/3643 MII Management Frame Register
|
||||
***************************************************************************/
|
||||
|
||||
register mmfr rw addr(base, 0x0040) "MII Management Frame Register" {
|
||||
data 16 "Data written to or read from PHY register";
|
||||
ta 2 "Turn Around: needs to be programmed to 10 to be valid";
|
||||
ra 5 "Register Address";
|
||||
pa 5 "Phy address";
|
||||
op 2 "Operation Code";
|
||||
st 2 "Start of Frame Delimeter";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.6/3643 MII Speed Control Register
|
||||
***************************************************************************/
|
||||
|
||||
register mscr rw addr(base, 0x0044) "MII Speed Control Register" {
|
||||
_ 1 rsvd;
|
||||
mii_speed 6 "MII Speed";
|
||||
dis_pre 1 "Disable preamble";
|
||||
hold_time 3 "Hold time on MDIO Output";
|
||||
_ 21 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.9/3646 Receive Control Register
|
||||
***************************************************************************/
|
||||
|
||||
register rcr rw addr(base, 0x0084) "Receive Control Register" {
|
||||
loop 1 "Internal Loopback";
|
||||
drt 1 "Disable Receive on Transmit";
|
||||
mii_mode 1 "Media Independant Interface Mode";
|
||||
prom 1 "Promiscuous Mode";
|
||||
bc_rej 1 "Broadcast Frame Reject";
|
||||
fce 1 "Flow Control Enable";
|
||||
rgmii_en 1 "RGMII Mode Enable";
|
||||
_ 1 rsvd;
|
||||
rmii_mode 1 "RMII Mode Enable";
|
||||
rmii_10t 1 "Enable 10-Mbits/mode of the RMII or RGMII";
|
||||
_ 2 rsvd;
|
||||
paden 1 "Enable Frame Padding Remove On Receive";
|
||||
paufwd 1 "Terminate/Forward Pause Frames";
|
||||
crcfwd 1 "Terminate/Forward Receive CRC";
|
||||
cfen 1 "MAC Control Frame Enable";
|
||||
max_fl 14 "Maximum Frame Length";
|
||||
nlc 1 "Payload Length Check Disable";
|
||||
grs 1 "Graceful Receive Stop";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.11/3649 Transmit Control Register
|
||||
***************************************************************************/
|
||||
|
||||
// 14.6.5.10
|
||||
register tcr rw addr(base, 0x000C4) "Transmit Control Register" {
|
||||
gts 1 "Graceful Transmit Stop";
|
||||
_ 1 rsvd;
|
||||
fden 1 "Full-Duplex Enable";
|
||||
tfc_pause 1 "Transmit Frame Control Pause";
|
||||
rfc_pause 1 "Receive Frame Control Pause";
|
||||
addsel 3 "Source MAC Address Select on Transmit";
|
||||
addins 1 "Set MAC Address on Transmit";
|
||||
crcfwd 1 "Forward Frame From Application With CRC";
|
||||
_ 1 rsvd;
|
||||
_ 21 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.11/3651 Physical Address Lower Register
|
||||
***************************************************************************/
|
||||
|
||||
// 14.6.5.11
|
||||
register palr rw addr(base, 0x000E4) "Physical Address Lower Register" {
|
||||
paddr1 32 "Pause Address";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.12/3651 Physical Address Upper Register
|
||||
***************************************************************************/
|
||||
|
||||
register paur rw addr(base, 0x000E8) "Physical Address Upper Register" {
|
||||
typ 16 "Always contains 0x8808";
|
||||
paddr2 16 "Pause Address";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.12/3651 Opcode/Pause Duration Register
|
||||
***************************************************************************/
|
||||
|
||||
register opd rw addr(base, 0x000EC) "Opcode/Pause Duration Register" {
|
||||
pause_dur 16 "Pause duration";
|
||||
opcode 16 "Opcode Field in Pause Frames";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.16/3654 Descriptor Individual Upper Address
|
||||
***************************************************************************/
|
||||
|
||||
register iaur rw addr(base, 0x00118) "Descriptor Individual Upper Address Reg" {
|
||||
iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.17/3655 Descriptor Individual Lower Address
|
||||
***************************************************************************/
|
||||
|
||||
register ialr rw addr(base, 0x0011C) "Descriptor Individual Lower Address Reg" {
|
||||
iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.18/3656 Descriptor Group Upper Address
|
||||
***************************************************************************/
|
||||
|
||||
register gaur rw addr(base, 0x00120) "Descriptor Individual Upper Address Reg" {
|
||||
iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.19/3656 Descriptor Group Lower Address
|
||||
***************************************************************************/
|
||||
|
||||
register galr rw addr(base, 0x00124) "Descriptor Individual Lower Address Reg" {
|
||||
iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion";
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.20/3657 Transmit FIFO Watermark Register
|
||||
***************************************************************************/
|
||||
register tfwr rw addr(base, 0x00144) "Transmit FIFO Watermark Register " {
|
||||
tfwr 6 "Transmit FIFO Write";
|
||||
_ 2 rsvd;
|
||||
strfwd 1 "Store and Forward Enable";
|
||||
_ 23 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.27/3662 Receive Descriptor Ring 0 Start Register
|
||||
***************************************************************************/
|
||||
register rdsr rw addr(base, 0x00180) "Receive Descriptor Ring 0 Start Register" {
|
||||
_ 3 rsvd;
|
||||
start 29 "Pointer to the beginning of receive descriptor queue";
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.28/3663 Transmit Descriptor Ring 0 Start Register
|
||||
***************************************************************************/
|
||||
register tdsr rw addr(base, 0x00184) "Transmit Descriptor Ring 0 Start Register" {
|
||||
_ 3 rsvd;
|
||||
start 29 "Pointer to the beginning of transmit descriptor queue";
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.29/3663 Maximum Receive Buffer Size Register ring 0
|
||||
***************************************************************************/
|
||||
register mrbr rw addr(base, 0x00188) "Receive Descriptor Ring 0 Start Register" {
|
||||
_ 4 rsvd;
|
||||
start 10 "Receive buffer size in bytes";
|
||||
_ 18 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.30/3664 Receive FIFO Section Full Threshold
|
||||
***************************************************************************/
|
||||
register rsfl rw addr(base, 0x00190) "Receive FIFO Section Full Threshold" {
|
||||
rx_section_full 10 "Value of Receive FIFO Sectoin Full Threshold";
|
||||
_ 22 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.31/3665 Receive FIFO Section Empty Threshold
|
||||
***************************************************************************/
|
||||
register rsem rw addr(base, 0x00194) "Receive FIFO Section Empty Threshold" {
|
||||
rx_section_empty 10 "Value of Receive FIFO Sectoin Empty Threshold";
|
||||
_ 6 rsvd;
|
||||
stat_section_empty 5 "RX Status Section Empty Threshold";
|
||||
_ 11 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.32/3665 Receive FIFO Almost Empty Threshold
|
||||
***************************************************************************/
|
||||
register raem rw addr(base, 0x00198) "Receive FIFO Almost Empty Threshold" {
|
||||
rx_almost_full 10 "Value of Receive FIFO Almost Empty Threshold";
|
||||
_ 22 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.33/3666 Receive FIFO Almost Empty Threshold
|
||||
***************************************************************************/
|
||||
register rafl rw addr(base, 0x0019C) "Receive FIFO Almost Full Threshold" {
|
||||
rx_almost_empty 10 "Value of Receive FIFO Almost Full Threshold";
|
||||
_ 22 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.49/3679 Tx Packet Count Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_t_packets rw addr(base, 0x00204) "Tx Packet Count Statistic Register" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.50/3680 Tx Broadcast Packet Count Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_t_bc_pkt rw addr(base, 0x00208) "Tx Broadcast Packet Count Statistic Register" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.51/3680 Tx Multicast Packet Count Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_t_mc_pkt rw addr(base, 0x0020C) "Tx Multicast Packet Count Statistic Register" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.52/3681 Tx Packets with CRC/Align Error Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_t_crc_align rw addr(base, 0x00210) "Tx Packets with CRC/Align Error Statistic Register" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.53/3681 Tx Packets Less Than Bytes and Good CRC Statistics
|
||||
***************************************************************************/
|
||||
register rmon_t_undersize rw addr(base, 0x00214) "Tx Packets Less Than Bytes and Good CRC Statistics" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.54/3681 Tx Packets GT MAX_FL bytes and Good CRC Statistics
|
||||
***************************************************************************/
|
||||
register rmon_t_oversize rw addr(base, 0x00218) "Tx Packets GT MAX_FL bytes and Good CRC Statistics" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.55/3681 Tx Packets Less Than Bytes and bad CRC Statistics
|
||||
***************************************************************************/
|
||||
register rmon_t_frag rw addr(base, 0x0021C) "Tx Packets Less Than Bytes and bad CRC Statistics" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.54/3682 Tx Packets GT MAX_FL bytes and bad CRC Statistics
|
||||
***************************************************************************/
|
||||
register rmon_t_jab rw addr(base, 0x00220) "Tx Packets GT MAX_FL bytes and bad CRC Statistics" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.55/3683 Tx Collision Count Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_t_col rw addr(base, 0x00224) "Tx Collision Count Statistic Register" {
|
||||
count 16 "Number of packets sent";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.79/3766 Rx Packet Count Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_r_packets rw addr(base, 0x00284) "Rx Packet Count Statistic Register" {
|
||||
count 16 "Number of packets received";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.81/3767 Rx Packets with CRC/Align Error Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_r_packets_crc_align rw addr(base, 0x00290) "Rx Packets with CRC/Align Error Statistic Register" {
|
||||
count 16 "Number of packets received with CRC or align error";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.94/3767 Rx Octets Statistic Register
|
||||
***************************************************************************/
|
||||
register rmon_r_octets rw addr(base, 0x002C4) "Rx Packets with CRC/Align Error Statistic Register" {
|
||||
count 32 "Number of received octets";
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* 14.6.5.95/3773 Frame not Counted Correctly Statistic Register
|
||||
***************************************************************************/
|
||||
register iee_r_drop rw addr(base, 0x002C8) "Frame not Counted Correctly Statistic Register" {
|
||||
count 16 "Frame count";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
datatype bufdesc "Legacy descriptor" {
|
||||
len 16 "Data length";
|
||||
sc 16 "Control and status info";
|
||||
addr 32 "Buffer address";
|
||||
};
|
||||
|
||||
/*
|
||||
datatype bufdesc_ex "Enhanced descriptor" {
|
||||
sc 16 "Control and status info";
|
||||
len 16 "Data length";
|
||||
addr 32 "Buffer address";
|
||||
esc 32 "";
|
||||
prot 32 "";
|
||||
ts 32 "";
|
||||
res0 64 "";
|
||||
};
|
||||
*/
|
||||
|
||||
};
|
||||
391
devices/imx8x/imx8x_gpio.dev
Normal file
391
devices/imx8x/imx8x_gpio.dev
Normal file
@ -0,0 +1,391 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpuart.dev
|
||||
*
|
||||
* DESCRIPTION: iMX8X GPIO
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* i.MX 8DualXPlus Appliacations Processor Reference Manual, revision D, NXP
|
||||
* Pages 7950 - 7968
|
||||
* (IMX8DQXPRM.pdf)
|
||||
*
|
||||
*/
|
||||
|
||||
device imx8x_gpio msbfirst (addr base) "IMX8X GPIO" {
|
||||
|
||||
constants direction "GPIO directon" {
|
||||
input = 0b0 "GPIO is configured as input.";
|
||||
output = 0b1 "GPIO is configured as output.";
|
||||
};
|
||||
|
||||
constants ic "Interrupt condition" {
|
||||
ll = 0b00 "Low-level sensitive";
|
||||
hl = 0b01 "High-level sensitive";
|
||||
re = 0b10 "Rising-edge sensitive";
|
||||
fe = 0b11 "Falling-edge sensitive";
|
||||
};
|
||||
|
||||
register DR rw addr(base, 0x0) "GPIO Data Register" {
|
||||
pin31 1 "Pin 31 data";
|
||||
pin30 1 "Pin 30 data";
|
||||
pin29 1 "Pin 29 data";
|
||||
pin28 1 "Pin 28 data";
|
||||
pin27 1 "Pin 27 data";
|
||||
pin26 1 "Pin 26 data";
|
||||
pin25 1 "Pin 25 data";
|
||||
pin24 1 "Pin 24 data";
|
||||
pin23 1 "Pin 23 data";
|
||||
pin22 1 "Pin 22 data";
|
||||
pin21 1 "Pin 21 data";
|
||||
pin20 1 "Pin 20 data";
|
||||
pin19 1 "Pin 19 data";
|
||||
pin18 1 "Pin 18 data";
|
||||
pin17 1 "Pin 17 data";
|
||||
pin16 1 "Pin 16 data";
|
||||
pin15 1 "Pin 15 data";
|
||||
pin14 1 "Pin 14 data";
|
||||
pin13 1 "Pin 13 data";
|
||||
pin12 1 "Pin 12 data";
|
||||
pin11 1 "Pin 11 data";
|
||||
pin10 1 "Pin 10 data";
|
||||
pin9 1 "Pin 9 data";
|
||||
pin8 1 "Pin 8 data";
|
||||
pin7 1 "Pin 7 data";
|
||||
pin6 1 "Pin 6 data";
|
||||
pin5 1 "Pin 5 data";
|
||||
pin4 1 "Pin 4 data";
|
||||
pin3 1 "Pin 3 data";
|
||||
pin2 1 "Pin 2 data";
|
||||
pin1 1 "Pin 1 data";
|
||||
pin0 1 "Pin 0 data";
|
||||
};
|
||||
|
||||
register GDIR rw addr(base, 0x4) "GPIO direction register" {
|
||||
pin31 1 type(direction) "Pin 31 direction";
|
||||
pin30 1 type(direction) "Pin 30 direction";
|
||||
pin29 1 type(direction) "Pin 29 direction";
|
||||
pin28 1 type(direction) "Pin 28 direction";
|
||||
pin27 1 type(direction) "Pin 27 direction";
|
||||
pin26 1 type(direction) "Pin 26 direction";
|
||||
pin25 1 type(direction) "Pin 25 direction";
|
||||
pin24 1 type(direction) "Pin 24 direction";
|
||||
pin23 1 type(direction) "Pin 23 direction";
|
||||
pin22 1 type(direction) "Pin 22 direction";
|
||||
pin21 1 type(direction) "Pin 21 direction";
|
||||
pin20 1 type(direction) "Pin 20 direction";
|
||||
pin19 1 type(direction) "Pin 19 direction";
|
||||
pin18 1 type(direction) "Pin 18 direction";
|
||||
pin17 1 type(direction) "Pin 17 direction";
|
||||
pin16 1 type(direction) "Pin 16 direction";
|
||||
pin15 1 type(direction) "Pin 15 direction";
|
||||
pin14 1 type(direction) "Pin 14 direction";
|
||||
pin13 1 type(direction) "Pin 13 direction";
|
||||
pin12 1 type(direction) "Pin 12 direction";
|
||||
pin11 1 type(direction) "Pin 11 direction";
|
||||
pin10 1 type(direction) "Pin 10 direction";
|
||||
pin9 1 type(direction) "Pin 9 direction";
|
||||
pin8 1 type(direction) "Pin 8 direction";
|
||||
pin7 1 type(direction) "Pin 7 direction";
|
||||
pin6 1 type(direction) "Pin 6 direction";
|
||||
pin5 1 type(direction) "Pin 5 direction";
|
||||
pin4 1 type(direction) "Pin 4 direction";
|
||||
pin3 1 type(direction) "Pin 3 direction";
|
||||
pin2 1 type(direction) "Pin 2 direction";
|
||||
pin1 1 type(direction) "Pin 1 direction";
|
||||
pin0 1 type(direction) "Pin 0 direction";
|
||||
};
|
||||
|
||||
register PSR ro addr(base, 0x8) "GPIO pad status register" {
|
||||
pin31 1 "Pin 31 pad status";
|
||||
pin30 1 "Pin 30 pad status";
|
||||
pin29 1 "Pin 29 pad status";
|
||||
pin28 1 "Pin 28 pad status";
|
||||
pin27 1 "Pin 27 pad status";
|
||||
pin26 1 "Pin 26 pad status";
|
||||
pin25 1 "Pin 25 pad status";
|
||||
pin24 1 "Pin 24 pad status";
|
||||
pin23 1 "Pin 23 pad status";
|
||||
pin22 1 "Pin 22 pad status";
|
||||
pin21 1 "Pin 21 pad status";
|
||||
pin20 1 "Pin 20 pad status";
|
||||
pin19 1 "Pin 19 pad status";
|
||||
pin18 1 "Pin 18 pad status";
|
||||
pin17 1 "Pin 17 pad status";
|
||||
pin16 1 "Pin 16 pad status";
|
||||
pin15 1 "Pin 15 pad status";
|
||||
pin14 1 "Pin 14 pad status";
|
||||
pin13 1 "Pin 13 pad status";
|
||||
pin12 1 "Pin 12 pad status";
|
||||
pin11 1 "Pin 11 pad status";
|
||||
pin10 1 "Pin 10 pad status";
|
||||
pin9 1 "Pin 9 pad status";
|
||||
pin8 1 "Pin 8 pad status";
|
||||
pin7 1 "Pin 7 pad status";
|
||||
pin6 1 "Pin 6 pad status";
|
||||
pin5 1 "Pin 5 pad status";
|
||||
pin4 1 "Pin 4 pad status";
|
||||
pin3 1 "Pin 3 pad status";
|
||||
pin2 1 "Pin 2 pad status";
|
||||
pin1 1 "Pin 1 pad status";
|
||||
pin0 1 "Pin 0 pad status";
|
||||
};
|
||||
|
||||
register ICR1 rw addr(base, 0xc) "GPIO interrupt configuration register1" {
|
||||
icr15 2 type(ic) "Pin 15 interrupt configuration";
|
||||
icr14 2 type(ic) "Pin 14 interrupt configuration";
|
||||
icr13 2 type(ic) "Pin 13 interrupt configuration";
|
||||
icr12 2 type(ic) "Pin 12 interrupt configuration";
|
||||
icr11 2 type(ic) "Pin 11 interrupt configuration";
|
||||
icr10 2 type(ic) "Pin 10 interrupt configuration";
|
||||
icr9 2 type(ic) "Pin 9 interrupt configuration";
|
||||
icr8 2 type(ic) "Pin 8 interrupt configuration";
|
||||
icr7 2 type(ic) "Pin 7 interrupt configuration";
|
||||
icr6 2 type(ic) "Pin 6 interrupt configuration";
|
||||
icr5 2 type(ic) "Pin 5 interrupt configuration";
|
||||
icr4 2 type(ic) "Pin 4 interrupt configuration";
|
||||
icr3 2 type(ic) "Pin 3 interrupt configuration";
|
||||
icr2 2 type(ic) "Pin 2 interrupt configuration";
|
||||
icr1 2 type(ic) "Pin 1 interrupt configuration";
|
||||
icr0 2 type(ic) "Pin 0 interrupt configuration";
|
||||
};
|
||||
|
||||
register ICR2 rw addr(base, 0x10) "GPIO interrupt configuration register2" {
|
||||
icr31 2 type(ic) "Pin 31 interrupt configuration";
|
||||
icr30 2 type(ic) "Pin 30 interrupt configuration";
|
||||
icr29 2 type(ic) "Pin 29 interrupt configuration";
|
||||
icr28 2 type(ic) "Pin 28 interrupt configuration";
|
||||
icr27 2 type(ic) "Pin 27 interrupt configuration";
|
||||
icr26 2 type(ic) "Pin 26 interrupt configuration";
|
||||
icr25 2 type(ic) "Pin 25 interrupt configuration";
|
||||
icr24 2 type(ic) "Pin 24 interrupt configuration";
|
||||
icr23 2 type(ic) "Pin 23 interrupt configuration";
|
||||
icr22 2 type(ic) "Pin 22 interrupt configuration";
|
||||
icr21 2 type(ic) "Pin 21 interrupt configuration";
|
||||
icr20 2 type(ic) "Pin 20 interrupt configuration";
|
||||
icr19 2 type(ic) "Pin 19 interrupt configuration";
|
||||
icr18 2 type(ic) "Pin 18 interrupt configuration";
|
||||
icr17 2 type(ic) "Pin 17 interrupt configuration";
|
||||
icr16 2 type(ic) "Pin 16 interrupt configuration";
|
||||
};
|
||||
|
||||
register IMR rw addr(base, 0x14) "GPIO interrupt mask register" {
|
||||
pin31 1 "Pin 31 interrupt mask";
|
||||
pin30 1 "Pin 30 interrupt mask";
|
||||
pin29 1 "Pin 29 interrupt mask";
|
||||
pin28 1 "Pin 28 interrupt mask";
|
||||
pin27 1 "Pin 27 interrupt mask";
|
||||
pin26 1 "Pin 26 interrupt mask";
|
||||
pin25 1 "Pin 25 interrupt mask";
|
||||
pin24 1 "Pin 24 interrupt mask";
|
||||
pin23 1 "Pin 23 interrupt mask";
|
||||
pin22 1 "Pin 22 interrupt mask";
|
||||
pin21 1 "Pin 21 interrupt mask";
|
||||
pin20 1 "Pin 20 interrupt mask";
|
||||
pin19 1 "Pin 19 interrupt mask";
|
||||
pin18 1 "Pin 18 interrupt mask";
|
||||
pin17 1 "Pin 17 interrupt mask";
|
||||
pin16 1 "Pin 16 interrupt mask";
|
||||
pin15 1 "Pin 15 interrupt mask";
|
||||
pin14 1 "Pin 14 interrupt mask";
|
||||
pin13 1 "Pin 13 interrupt mask";
|
||||
pin12 1 "Pin 12 interrupt mask";
|
||||
pin11 1 "Pin 11 interrupt mask";
|
||||
pin10 1 "Pin 10 interrupt mask";
|
||||
pin9 1 "Pin 9 interrupt mask";
|
||||
pin8 1 "Pin 8 interrupt mask";
|
||||
pin7 1 "Pin 7 interrupt mask";
|
||||
pin6 1 "Pin 6 interrupt mask";
|
||||
pin5 1 "Pin 5 interrupt mask";
|
||||
pin4 1 "Pin 4 interrupt mask";
|
||||
pin3 1 "Pin 3 interrupt mask";
|
||||
pin2 1 "Pin 2 interrupt mask";
|
||||
pin1 1 "Pin 1 interrupt mask";
|
||||
pin0 1 "Pin 0 interrupt mask";
|
||||
};
|
||||
|
||||
register ISR rw1c addr(base, 0x18) "GPIO interrupt status regsiter" {
|
||||
pin31 1 "Pin 31 interrupt status";
|
||||
pin30 1 "Pin 30 interrupt status";
|
||||
pin29 1 "Pin 29 interrupt status";
|
||||
pin28 1 "Pin 28 interrupt status";
|
||||
pin27 1 "Pin 27 interrupt status";
|
||||
pin26 1 "Pin 26 interrupt status";
|
||||
pin25 1 "Pin 25 interrupt status";
|
||||
pin24 1 "Pin 24 interrupt status";
|
||||
pin23 1 "Pin 23 interrupt status";
|
||||
pin22 1 "Pin 22 interrupt status";
|
||||
pin21 1 "Pin 21 interrupt status";
|
||||
pin20 1 "Pin 20 interrupt status";
|
||||
pin19 1 "Pin 19 interrupt status";
|
||||
pin18 1 "Pin 18 interrupt status";
|
||||
pin17 1 "Pin 17 interrupt status";
|
||||
pin16 1 "Pin 16 interrupt status";
|
||||
pin15 1 "Pin 15 interrupt status";
|
||||
pin14 1 "Pin 14 interrupt status";
|
||||
pin13 1 "Pin 13 interrupt status";
|
||||
pin12 1 "Pin 12 interrupt status";
|
||||
pin11 1 "Pin 11 interrupt status";
|
||||
pin10 1 "Pin 10 interrupt status";
|
||||
pin9 1 "Pin 9 interrupt status";
|
||||
pin8 1 "Pin 8 interrupt status";
|
||||
pin7 1 "Pin 7 interrupt status";
|
||||
pin6 1 "Pin 6 interrupt status";
|
||||
pin5 1 "Pin 5 interrupt status";
|
||||
pin4 1 "Pin 4 interrupt status";
|
||||
pin3 1 "Pin 3 interrupt status";
|
||||
pin2 1 "Pin 2 interrupt status";
|
||||
pin1 1 "Pin 1 interrupt status";
|
||||
pin0 1 "Pin 0 interrupt status";
|
||||
};
|
||||
|
||||
register EDGE_SEL rw addr(base, 0x1c) "GPIO edge select register" {
|
||||
pin31 1 "Pin 31 edge select";
|
||||
pin30 1 "Pin 30 edge select";
|
||||
pin29 1 "Pin 29 edge select";
|
||||
pin28 1 "Pin 28 edge select";
|
||||
pin27 1 "Pin 27 edge select";
|
||||
pin26 1 "Pin 26 edge select";
|
||||
pin25 1 "Pin 25 edge select";
|
||||
pin24 1 "Pin 24 edge select";
|
||||
pin23 1 "Pin 23 edge select";
|
||||
pin22 1 "Pin 22 edge select";
|
||||
pin21 1 "Pin 21 edge select";
|
||||
pin20 1 "Pin 20 edge select";
|
||||
pin19 1 "Pin 19 edge select";
|
||||
pin18 1 "Pin 18 edge select";
|
||||
pin17 1 "Pin 17 edge select";
|
||||
pin16 1 "Pin 16 edge select";
|
||||
pin15 1 "Pin 15 edge select";
|
||||
pin14 1 "Pin 14 edge select";
|
||||
pin13 1 "Pin 13 edge select";
|
||||
pin12 1 "Pin 12 edge select";
|
||||
pin11 1 "Pin 11 edge select";
|
||||
pin10 1 "Pin 10 edge select";
|
||||
pin9 1 "Pin 9 edge select";
|
||||
pin8 1 "Pin 8 edge select";
|
||||
pin7 1 "Pin 7 edge select";
|
||||
pin6 1 "Pin 6 edge select";
|
||||
pin5 1 "Pin 5 edge select";
|
||||
pin4 1 "Pin 4 edge select";
|
||||
pin3 1 "Pin 3 edge select";
|
||||
pin2 1 "Pin 2 edge select";
|
||||
pin1 1 "Pin 1 edge select";
|
||||
pin0 1 "Pin 0 edge select";
|
||||
};
|
||||
|
||||
/* The following 3 registers seem not to work... */
|
||||
|
||||
register DR_SET wo addr(base, 0x84) "GPIO data register set" {
|
||||
pin31 1 "Set pin 31";
|
||||
pin30 1 "Set pin 30";
|
||||
pin29 1 "Set pin 29";
|
||||
pin28 1 "Set pin 28";
|
||||
pin27 1 "Set pin 27";
|
||||
pin26 1 "Set pin 26";
|
||||
pin25 1 "Set pin 25";
|
||||
pin24 1 "Set pin 24";
|
||||
pin23 1 "Set pin 23";
|
||||
pin22 1 "Set pin 22";
|
||||
pin21 1 "Set pin 21";
|
||||
pin20 1 "Set pin 20";
|
||||
pin19 1 "Set pin 19";
|
||||
pin18 1 "Set pin 18";
|
||||
pin17 1 "Set pin 17";
|
||||
pin16 1 "Set pin 16";
|
||||
pin15 1 "Set pin 15";
|
||||
pin14 1 "Set pin 14";
|
||||
pin13 1 "Set pin 13";
|
||||
pin12 1 "Set pin 12";
|
||||
pin11 1 "Set pin 11";
|
||||
pin10 1 "Set pin 10";
|
||||
pin9 1 "Set pin 9";
|
||||
pin8 1 "Set pin 8";
|
||||
pin7 1 "Set pin 7";
|
||||
pin6 1 "Set pin 6";
|
||||
pin5 1 "Set pin 5";
|
||||
pin4 1 "Set pin 4";
|
||||
pin3 1 "Set pin 3";
|
||||
pin2 1 "Set pin 2";
|
||||
pin1 1 "Set pin 1";
|
||||
pin0 1 "Set pin 0";
|
||||
};
|
||||
|
||||
register DR_CLEAR wo addr(base, 0x88) "GPIO data register clear" {
|
||||
pin31 1 "Clear pin 31";
|
||||
pin30 1 "Clear pin 30";
|
||||
pin29 1 "Clear pin 29";
|
||||
pin28 1 "Clear pin 28";
|
||||
pin27 1 "Clear pin 27";
|
||||
pin26 1 "Clear pin 26";
|
||||
pin25 1 "Clear pin 25";
|
||||
pin24 1 "Clear pin 24";
|
||||
pin23 1 "Clear pin 23";
|
||||
pin22 1 "Clear pin 22";
|
||||
pin21 1 "Clear pin 21";
|
||||
pin20 1 "Clear pin 20";
|
||||
pin19 1 "Clear pin 19";
|
||||
pin18 1 "Clear pin 18";
|
||||
pin17 1 "Clear pin 17";
|
||||
pin16 1 "Clear pin 16";
|
||||
pin15 1 "Clear pin 15";
|
||||
pin14 1 "Clear pin 14";
|
||||
pin13 1 "Clear pin 13";
|
||||
pin12 1 "Clear pin 12";
|
||||
pin11 1 "Clear pin 11";
|
||||
pin10 1 "Clear pin 10";
|
||||
pin9 1 "Clear pin 9";
|
||||
pin8 1 "Clear pin 8";
|
||||
pin7 1 "Clear pin 7";
|
||||
pin6 1 "Clear pin 6";
|
||||
pin5 1 "Clear pin 5";
|
||||
pin4 1 "Clear pin 4";
|
||||
pin3 1 "Clear pin 3";
|
||||
pin2 1 "Clear pin 2";
|
||||
pin1 1 "Clear pin 1";
|
||||
pin0 1 "Clear pin 0";
|
||||
};
|
||||
|
||||
register DR_TOGGLE wo addr(base, 0x8c) "GPIO data register toggle" {
|
||||
pin31 1 "Toggle pin 31";
|
||||
pin30 1 "Toggle pin 30";
|
||||
pin29 1 "Toggle pin 29";
|
||||
pin28 1 "Toggle pin 28";
|
||||
pin27 1 "Toggle pin 27";
|
||||
pin26 1 "Toggle pin 26";
|
||||
pin25 1 "Toggle pin 25";
|
||||
pin24 1 "Toggle pin 24";
|
||||
pin23 1 "Toggle pin 23";
|
||||
pin22 1 "Toggle pin 22";
|
||||
pin21 1 "Toggle pin 21";
|
||||
pin20 1 "Toggle pin 20";
|
||||
pin19 1 "Toggle pin 19";
|
||||
pin18 1 "Toggle pin 18";
|
||||
pin17 1 "Toggle pin 17";
|
||||
pin16 1 "Toggle pin 16";
|
||||
pin15 1 "Toggle pin 15";
|
||||
pin14 1 "Toggle pin 14";
|
||||
pin13 1 "Toggle pin 13";
|
||||
pin12 1 "Toggle pin 12";
|
||||
pin11 1 "Toggle pin 11";
|
||||
pin10 1 "Toggle pin 10";
|
||||
pin9 1 "Toggle pin 9";
|
||||
pin8 1 "Toggle pin 8";
|
||||
pin7 1 "Toggle pin 7";
|
||||
pin6 1 "Toggle pin 6";
|
||||
pin5 1 "Toggle pin 5";
|
||||
pin4 1 "Toggle pin 4";
|
||||
pin3 1 "Toggle pin 3";
|
||||
pin2 1 "Toggle pin 2";
|
||||
pin1 1 "Toggle pin 1";
|
||||
pin0 1 "Toggle pin 0";
|
||||
};
|
||||
};
|
||||
|
||||
366
devices/imx8x/sdhc.dev
Normal file
366
devices/imx8x/sdhc.dev
Normal file
@ -0,0 +1,366 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* sdhc.dev
|
||||
*
|
||||
* DESCRIPTION: IMX8X SD Host Controller
|
||||
*
|
||||
* See:
|
||||
* SD Specifications Part A2: SD Host Controller Simplified Specification
|
||||
* Version 3.00, February 25, 2011.
|
||||
* Technical Committee, SD Association
|
||||
*
|
||||
*/
|
||||
|
||||
device sdhc msbfirst (addr base) "IMX8X SD Host Controller" {
|
||||
|
||||
// 14.8.8.1.2
|
||||
register ds_addr rw addr(base, 0x00) "DMA system address" type(uint32);
|
||||
register cmd_arg2 rw also addr(base, 0x00) "Argument 2" type(uint32);
|
||||
|
||||
// 14.8.8.1.3
|
||||
register blk_att rw addr(base, 0x04) "Block count" {
|
||||
blkcnt 16 "Block count";
|
||||
_ 3 mbz;
|
||||
blksize 13 "Transfer block size (bytes)";
|
||||
};
|
||||
|
||||
// 14.8.8.1.4
|
||||
register cmd_arg rw addr(base, 0x08) "Argument 1" type(uint32);
|
||||
|
||||
// 14.8.8.1.5
|
||||
constants auto_en "Auto command enable values" {
|
||||
auto_en_dis = 0b00 "Auto Command Disabled";
|
||||
auto_en_12 = 0b01 "Auto CMD12 Enable";
|
||||
auto_en_23 = 0b10 "Auto CMD23 Enable";
|
||||
};
|
||||
constants cmd_tp "Command type" {
|
||||
cmd_tp_abrt = 0b11 "Abort CMD12, CMD52 for writing I/O Abort";
|
||||
cmd_tp_rsme = 0b10 "Resume CMD52 for writing Function Select";
|
||||
cmd_tp_susp = 0b01 "Suspend CMD52 for writing Bus Suspend";
|
||||
cmd_tp_norm = 0b00 "Normal; other commands";
|
||||
};
|
||||
constants rsp_tp "Response type" {
|
||||
rsp_tp_none = 0b00 "No response";
|
||||
rsp_tp_136 = 0b01 "Response length 136";
|
||||
rsp_tp_48 = 0b10 "Response length 48";
|
||||
rsp_tp_48cb = 0b11 "Response length 48 check busy after response";
|
||||
};
|
||||
register cmd_xfr_typ rw addr(base, 0x0C) "Command Transfer Type" {
|
||||
_ 2 mbz;
|
||||
cmdinx 6 "Command index";
|
||||
cmdtyp 2 type(cmd_tp) "Command type";
|
||||
dpsel 1 "Data present select";
|
||||
cicen 1 "Command index check enable";
|
||||
cccen 1 "Command CRC check enable";
|
||||
_ 1 mbz;
|
||||
rsptyp 2 type(rsp_tp) "Response type select";
|
||||
_ 16 mbz;
|
||||
};
|
||||
|
||||
// 14.8.8.1.6-9
|
||||
register cmd_rsp0 rw addr(base, 0x10) "Command Response 0" type(uint32);
|
||||
register cmd_rsp1 rw addr(base, 0x14) "Command Response 1" type(uint32);
|
||||
register cmd_rsp2 rw addr(base, 0x18) "Command Response 2" type(uint32);
|
||||
register cmd_rsp3 rw addr(base, 0x1C) "Command Response 3" type(uint32);
|
||||
|
||||
// 14.8.8.1.10
|
||||
register data_buff_acc_port rw addr(base, 0x20) "Data Buffer Access Port" type(uint32);
|
||||
|
||||
|
||||
// 14.8.8.1.11
|
||||
register pres_state rw addr(base, 0x24) "Present State" {
|
||||
dlsl 8 "Data Line Signal Level";
|
||||
clsl 1 "CMD Line Signal Level";
|
||||
_ 3 mbz;
|
||||
wpspl 1 "Write Protect Switch Pin Level";
|
||||
cdpl 1 "Card Detect Pin Level";
|
||||
_ 1 mbz;
|
||||
cinst 1 "Card inserted";
|
||||
tscd 1 "Tape Select Change Done";
|
||||
_ 2 mbz;
|
||||
rtr 1 "Retuning request";
|
||||
bren 1 "Buffer read enable";
|
||||
bwen 1 "Buffer write enable";
|
||||
rta 1 "Read transfer active";
|
||||
wta 1 "Write transfer active";
|
||||
sdoff 1 "SD Clock Gated Off Internally";
|
||||
peroff 1 "IPG_PERCLK Gated Off Internally";
|
||||
hckoff 1 "HCLK Gated Off Internally";
|
||||
ipgoff 1 "IPG_CLK Gated Off Internally";
|
||||
sdstb 1 "SD Clock Stable";
|
||||
dla 1 "Data Line Active";
|
||||
cdihb 1 "Command Inhibit (DATA)";
|
||||
cihb 1 "Command Inhibit (CMD)";
|
||||
};
|
||||
|
||||
// 14.8.8.1.12
|
||||
register prot_ctrl rw addr(base, 0x28) "Protocol Control" {
|
||||
_ 1 mbz;
|
||||
non_exact_blk_rd 1;
|
||||
_ 3 mbz;
|
||||
wecrm 1;
|
||||
wecins 1;
|
||||
wecint 1;
|
||||
_ 3;
|
||||
rd_done_no_8clk 1;
|
||||
iabg 1;
|
||||
rwctl 1;
|
||||
creq 1;
|
||||
sabgreq 1;
|
||||
_ 6 mbz;
|
||||
dmasel 2;
|
||||
cdss 1;
|
||||
cdtl 1;
|
||||
emode 2;
|
||||
d3cd 1;
|
||||
dtw 2;
|
||||
lctl 1;
|
||||
};
|
||||
|
||||
// 14.8.8.1.13
|
||||
register sys_ctrl rw addr(base, 0x2C) "System control" {
|
||||
_ 3 mbz;
|
||||
rstt 1 "Reset Tuning";
|
||||
inita 1 "initialization activation";
|
||||
rstd 1 "Software reset Data";
|
||||
rstc 1 "Software reset CMD";
|
||||
rsta 1 "Software reset ALL";
|
||||
ipp_rst_n 1 "";
|
||||
_ 3 mbz;
|
||||
dtocv 4 "data timeout counter value";
|
||||
sdclkfs 8 "sdclk frequency select";
|
||||
dvs 4 "divisor";
|
||||
_ 4 mbz;
|
||||
|
||||
};
|
||||
|
||||
// 14.8.8.1.14
|
||||
register int_status rw1c addr(base, 0x30) "Inerrupt Status" {
|
||||
_ 3 mbz;
|
||||
dmae 1 "DMA Error";
|
||||
_ 1 mbz;
|
||||
tne 1 "Tuning Error";
|
||||
_ 1 mbz;
|
||||
ac12e 1 "Auto Cmd 12 Error";
|
||||
_ 1 mbz;
|
||||
debe 1 "Data End Bit Error";
|
||||
dce 1 "Data CRC Error";
|
||||
dtoe 1 "Data Timeout Error";
|
||||
cie 1 "Command Index Error";
|
||||
cebe 1 "Command End Bit error";
|
||||
cce 1 "Command CRC Error";
|
||||
ctoe 1 "Command Timeout Error";
|
||||
|
||||
// 16 bit boundary
|
||||
_ 1 mbz;
|
||||
cqi 1 "Command Queueing Interrupt";
|
||||
tp 1 "Tuning pass";
|
||||
rte 1 "Re-Tuning event";
|
||||
_ 3 mbz;
|
||||
cint 1 "Card interrupt";
|
||||
crm 1 "Card removal";
|
||||
cins 1 "Card insertion";
|
||||
brr 1 "Buffer read ready";
|
||||
bwr 1 "Buffer write ready";
|
||||
dint 1 "DMA interrupt";
|
||||
bge 1 "Block gap event";
|
||||
tc 1 "Transfer complete";
|
||||
cc 1 "Command complete";
|
||||
};
|
||||
|
||||
regtype ir "Interrupt Enable Register" {
|
||||
_ 3 mbz;
|
||||
dmaeen 1 "DMA Error";
|
||||
_ 1 mbz;
|
||||
tneen 1 "Tuning Error";
|
||||
_ 1 mbz;
|
||||
ac12een 1 "Auto Cmd 12 Error";
|
||||
_ 1 mbz;
|
||||
debeen 1 "Data End Bit Error";
|
||||
dceen 1 "Data CRC Error";
|
||||
dtoeen 1 "Data Timeout Error";
|
||||
cieen 1 "Command Index Error";
|
||||
cebeen 1 "Command End Bit error";
|
||||
cceen 1 "Command CRC Error";
|
||||
ctoeen 1 "Command Timeout Error";
|
||||
|
||||
// 16 bit boundary
|
||||
_ 1 mbz;
|
||||
cqien 1 "Command Queueing Interrupt";
|
||||
tpen 1 "Tuning pass";
|
||||
rteen 1 "Re-Tuning event";
|
||||
_ 3 mbz;
|
||||
cinten 1 "Card interrupt";
|
||||
crmen 1 "Card removal";
|
||||
cinsen 1 "Card insertion";
|
||||
brren 1 "Buffer read ready";
|
||||
bwren 1 "Buffer write ready";
|
||||
dinten 1 "DMA interrupt";
|
||||
bgeen 1 "Block gap event";
|
||||
tcen 1 "Transfer complete";
|
||||
ccen 1 "Command complete";
|
||||
};
|
||||
|
||||
register int_status_en addr(base, 0x34) "Interrupt Status enable" type(ir);
|
||||
register int_signal_en addr(base, 0x38) "Interrupt Signal enable" type(ir);
|
||||
|
||||
// 14.8.8.1.17
|
||||
register autocmd12_err_status addr(base, 0x3c) "Auto CMD12 Error Status" {
|
||||
_ 8 mbz;
|
||||
smp_clk_sel 1;
|
||||
execute_tuning 1;
|
||||
_ 14 mbz;
|
||||
cnibac12e 1;
|
||||
_ 2 mbz;
|
||||
ac12ie 1;
|
||||
ac12ce 1;
|
||||
ac12ebe 1;
|
||||
ac12toe 1;
|
||||
ac12ne 1;
|
||||
};
|
||||
|
||||
// 14.8.8.1.18
|
||||
register host_ctrl_cap addr(base, 0x40) "Host Controller Capabilities" {
|
||||
_ 5 mbz;
|
||||
vs_18 1;
|
||||
vs_30 1;
|
||||
vs_33 1;
|
||||
srs 1;
|
||||
dmas 1;
|
||||
hss 1;
|
||||
admas 1;
|
||||
_ 1 mbz;
|
||||
mbl 3;
|
||||
retuning_mode 2;
|
||||
use_tuning_sdr50 1;
|
||||
_ 1 mbz;
|
||||
time_count_retuning 4;
|
||||
_ 5 mbz;
|
||||
ddr50_support 1;
|
||||
sdr104_support 1;
|
||||
sdr50_support 1;
|
||||
};
|
||||
|
||||
// 14.8.8.1.19
|
||||
register wtmk_lvl addr(base, 0x44) "Watermark Level" {
|
||||
_ 8 mbz;
|
||||
wr_wml 8;
|
||||
_ 8 mbz;
|
||||
rd_wml 8;
|
||||
};
|
||||
|
||||
// 14.8.8.1.20
|
||||
register mix_ctrl addr(base, 0x48) "Mix Control" {
|
||||
_ 1 mb1;
|
||||
_ 1 mbz;
|
||||
_ 1 mbz;
|
||||
_ 1;
|
||||
en_hs400_mode 1;
|
||||
hs400_mode 1;
|
||||
fbclk_sel 1;
|
||||
auto_tune_en 1;
|
||||
smp_clk_sel 1;
|
||||
exe_tune 1;
|
||||
_ 14;
|
||||
ac23en 1;
|
||||
nibble_pos 1;
|
||||
msbsel 1;
|
||||
dtdsel 1;
|
||||
ddr_en 1;
|
||||
ac12en 1;
|
||||
bcen 1;
|
||||
dmaen 1;
|
||||
};
|
||||
|
||||
// 14.8.8.1.24
|
||||
register dll rw addr(base, 0x60) "Delay line control" {
|
||||
dll_ctrl_ref_update_int 4;
|
||||
dll_ctrl_slv_update_int 8;
|
||||
_ 1 mbz;
|
||||
dll_ctrl_slv_dly_target1 3;
|
||||
dll_ctrl_slv_override_val 7;
|
||||
dll_ctrl_slv_override 1;
|
||||
dll_ctrl_gate_update 1;
|
||||
dll_ctrl_slv_dly_target0 4;
|
||||
dll_ctrl_slv_force_upd 1;
|
||||
dll_ctrl_reset 1;
|
||||
dll_ctrl_enable 1;
|
||||
};
|
||||
|
||||
// 14.8.8.1.26
|
||||
register clk_tune_ctrl_status rw addr(base, 0x68) "CLK Tuning Control and Status" {
|
||||
pre_err 1;
|
||||
tap_sel_pre 7;
|
||||
tap_sel_out 4;
|
||||
tap_sel_post 4;
|
||||
nxt_err 1;
|
||||
dly_cell_set_pre 7;
|
||||
dly_cell_set_out 4;
|
||||
dly_cell_set_post 4;
|
||||
};
|
||||
|
||||
// 14.8.8.1.29
|
||||
//register vend_spec rw addr(base, 0xC0) "Vendor Specific" {
|
||||
// cmd_byte_en 1 "cmd byte en";
|
||||
// _ 15 mbz;
|
||||
// crc_chk_dis 1 "CRC Check Disable";
|
||||
// _ 6 mbz;
|
||||
// frc_sdclk_on 1 "Force CLK output active";
|
||||
// _ 4 mbz;
|
||||
// ac12_wr_chkbusy_en 1 "Check busy enable";
|
||||
// conflict_chk_en 1 "Conflic check enable";
|
||||
// vselect 1 "Voltage selection";
|
||||
// _ 1 mbz;
|
||||
//};
|
||||
|
||||
// This is vend_spec according to uboot
|
||||
register vend_spec rw addr(base, 0xC0) "Vendor Specific" {
|
||||
_ 17 mbz;
|
||||
cken 1;
|
||||
peren 1;
|
||||
hcken 1;
|
||||
ipgen 1;
|
||||
_ 11 mbz;
|
||||
};
|
||||
|
||||
|
||||
// 14.8.8.1.30
|
||||
register mmc_boot rw addr(base, 0xC4) "MMC Boot Register" {
|
||||
boot_blk_cnt 16;
|
||||
_ 7 mbz;
|
||||
disable_time_out 1;
|
||||
auto_sabg_en 1;
|
||||
boot_en 1;
|
||||
boot_mode 1;
|
||||
boot_ack 1;
|
||||
dtocv_ack 4;
|
||||
};
|
||||
|
||||
// 14.8.8.1.31
|
||||
register vend_spec2 rw addr(base, 0xC8) "Vendor Specific 2" {
|
||||
fbclk_tap_sel 16;
|
||||
en_32k_clk 1;
|
||||
bus_rst 1;
|
||||
part_dll_debug 1;
|
||||
acmd23_argu2_en 1;
|
||||
hs400_rd_clk_stop_en 1;
|
||||
hs400_wr_clk_stop_en 1;
|
||||
_ 3 mbz;
|
||||
tuning_cmd_en 1;
|
||||
tuning_1bit_en 1;
|
||||
tuning_8bit_en 1;
|
||||
card_int_d3_test 1;
|
||||
_ 3 mbz;
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
};
|
||||
1108
devices/ioat_dma.dev
Normal file
1108
devices/ioat_dma.dev
Normal file
File diff suppressed because it is too large
Load Diff
262
devices/ioat_dma_chan.dev
Normal file
262
devices/ioat_dma_chan.dev
Normal file
@ -0,0 +1,262 @@
|
||||
/*
|
||||
* Copyright (c) 2014, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetsstrasse 6 CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ioat_dma.dev
|
||||
*
|
||||
* DESCRIPTION: Crystal Beach DMA Engine register descriptor
|
||||
*
|
||||
* This is derived from the "Intel (R) Xeon (R) Processor E5 v2 Product Family",
|
||||
* chapter 8.4 & 8.5, "Device 4, Function 0-7, Crystal Beach DMA".
|
||||
*
|
||||
*/
|
||||
|
||||
device ioat_dma_chan msbfirst ( addr chan_base ) "IOAT DMA (Crystal Beach) Channel registers" {
|
||||
|
||||
constants cmpl_status_shift "Completion Status Shift Value" {
|
||||
compl_addr_shift = 0x6 "Completion addrss shift";
|
||||
};
|
||||
|
||||
constants cmpl_status_mask width(64) "Completion Status Mask Value" {
|
||||
status_mask = 0x3f "Mask for the status fields";
|
||||
};
|
||||
|
||||
datatype compl_status msbfirst (64) "Completion writeback data area" {
|
||||
compl_desc 58 "Completed Descriptor Address";
|
||||
_ 1 "Reserved";
|
||||
soft_err 1 "Software Error";
|
||||
unaff_err 1 "Unaffiliated error";
|
||||
status 3 "Channel status field";
|
||||
};
|
||||
|
||||
constants chanctrl_snoop "Field values for Snoop Control" {
|
||||
chanctrl_snoop_disabled = 0x1 "Disabled snooping";
|
||||
chanctrl_snoop_enabled = 0x0 "Enable snooping";
|
||||
};
|
||||
|
||||
constants chanctrl_features "Field values for Channel Features" {
|
||||
chanctrl_f_enable = 0x1 "Feature field is enabled";
|
||||
chanctrl_f_disable = 0x0 "Feature field is disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.12 - Channel Control Register
|
||||
*
|
||||
* The Channel Control register controls the behavior of the DMA
|
||||
* channel when specific events occur such as completion or errors.
|
||||
*/
|
||||
register ctrl addr(chan_base, 0x00) "Channel Control Register" {
|
||||
_ 6 rsvd "Reserved";
|
||||
dca_en 1 rw "Direct Cache access enabled";
|
||||
in_use 1 rw "Channel is in use";
|
||||
_ 2 rsvd "reserved";
|
||||
snoop_ctrl 1 rw "Descriptor address snoop control";
|
||||
err_int_en 1 rw "Error Interrupt Enabled";
|
||||
err_abort 1 rw "Any Error Abort Enbled";
|
||||
err_cmp_en 1 rw "Error Completion Enabled";
|
||||
_ 1 rsvd "Reserved";
|
||||
intp_dis 1 rw1c "Interrupt disable";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.13 - DMA Compatibility Register
|
||||
*/
|
||||
register dma_comp ro addr(chan_base, 0x02) "DMA Compatibility Register" {
|
||||
_ 13 "Reserved";
|
||||
v3 1 "Compatible with CB Version 3";
|
||||
v2 1 "Compatible with CB Version 2";
|
||||
v1 1 "NOT compatible with CB Version 1";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.14 - DMA Channel Command Register
|
||||
*
|
||||
* Setting more than one of these bits with the same write operation
|
||||
* will result in an Fatal error affiliated.
|
||||
*/
|
||||
register cmd addr(chan_base, 0x84) "DMA Channel Command Register." {
|
||||
_ 2 rsvd "Reserved";
|
||||
reset 1 rw "Reset DMA channel";
|
||||
resume 1 rw "resume";
|
||||
abort 1 rw "Abort";
|
||||
susp 1 rw "Suspend the DMA channel";
|
||||
append 1 rw "Append";
|
||||
start 1 rw "Start";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.15 - DMA Descriptor Count Register
|
||||
*
|
||||
* This is the absolute value of the number of valid descriptors in
|
||||
* the chain. The hardware sets this register and an internal counter
|
||||
* to zero whenever the CHAINADDR register is written. When this
|
||||
* register does not equal the value of the internal register, the
|
||||
* DMA channel processes descriptors, incrementing the internal
|
||||
* counter each time that it completes (or skips) a descriptor.This
|
||||
* register is RW if CHANCNT register is 1 otherwise this register is RO.
|
||||
*/
|
||||
register dmacount addr(chan_base, 0x06) "DMA Descriptor Count Register"
|
||||
type(uint16);
|
||||
|
||||
|
||||
constants trans_state "DMA Transfer States" {
|
||||
trans_state_active = 0x0 "The transfer is active";
|
||||
trans_state_idle = 0x1 "Idle, All DMA transfers done";
|
||||
trans_state_susp = 0x2 "Suspended";
|
||||
trans_state_halt = 0x3 "Halted, operation aborted (error)";
|
||||
trans_state_armed = 0x4 "Armed State";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.16 - Channel Status Lo Register.
|
||||
*
|
||||
* The Channel Status Register records the address of the last
|
||||
* descriptor completed by the DMA channel. Refer to Crystal Beach
|
||||
* Architecture Specification 2.0 Rev 1.0 for special hardware
|
||||
* requirements when software reads this register.
|
||||
*/
|
||||
register sts_lo ro addr(chan_base, 0x08) "Channel Status Lo Register." {
|
||||
cmpdscaddr 26 "Uppder address of the last descriptor processed";
|
||||
_ 3 "Reserved";
|
||||
dma_trans_state 3 "DMA transfer State";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.17 - Channel Status Hi Register.
|
||||
*
|
||||
* The Channel Status Register records the address of the last
|
||||
* descriptor completed by the DMA channel. Refer to Crystal Beach
|
||||
* Architecture Specification for special hardware requirements when
|
||||
* software reads this register.
|
||||
*
|
||||
* Also stores the address of the last processed descriptor
|
||||
*/
|
||||
register sts_hi ro addr(chan_base, 0x0c) "Channel Status Hi Register."
|
||||
type(uint32);
|
||||
|
||||
/*
|
||||
* 8.5.18 - Descriptor Chain Address Lo Register.
|
||||
*
|
||||
* This register is written by the processor to specify the first
|
||||
* descriptor to be fetched by the DMA channel.
|
||||
*
|
||||
* This register is RW if CHANCNT register is 1 otherwise this register is RO.
|
||||
*/
|
||||
register chainaddr_lo rw addr(chan_base, 0x10) "Descriptor Chain Address Lo Register." {
|
||||
descaddr_lo 26 rw "Address of the first descriptor";
|
||||
_ 6 mbz "Must be zero";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.19 - Descriptor Chain Address Hi Register.
|
||||
*
|
||||
* This register is written by the processor to specify the first
|
||||
* descriptor to be fetched by the DMA channel.
|
||||
*
|
||||
* This register is RW if CHANCNT register is 1 otherwise this register is RO.
|
||||
*/
|
||||
register chainaddr_hi rw addr(chan_base, 0x14) "Descriptor Chain Address Hi Register."
|
||||
type(uint32);
|
||||
|
||||
|
||||
/*
|
||||
* 8.5.20 - Channel Completion Address Lo Register.
|
||||
*
|
||||
* This register specifies the address where the DMA channel writes
|
||||
* the completion status upon completion or an error condition i.e.
|
||||
* it writes the contents of the CHANSTS register to the destination
|
||||
* as pointed by the CHANCMP register.
|
||||
*
|
||||
* This register is RW if CHANCNT register is 1 otherwise this register is RO.
|
||||
*/
|
||||
register cmpl_lo addr(chan_base, 0x18) "Channel Completion Address Lo Register."
|
||||
type(uint32);
|
||||
|
||||
/*
|
||||
* 8.5.21 - Channel Completion Address Hi Register.
|
||||
*
|
||||
* This register specifies the address where the DMA channel writes
|
||||
* the completion status upon completion or an error condition i.e.
|
||||
* it writes the contents of the CHANSTS register to the destination
|
||||
* as pointed by the CHANCMP register.
|
||||
*
|
||||
* This register is RW if CHANCNT register is 1 otherwise this register is RO.
|
||||
*/
|
||||
register cmpl_hi addr(chan_base, 0x1c) "Channel Completion Address Hi Register."
|
||||
type(uint32);
|
||||
|
||||
/*
|
||||
* 8.5.22 - Channel Error Register
|
||||
*
|
||||
* The Channel Error Register records the error conditions occurring
|
||||
* within a given DMA channel.
|
||||
*/
|
||||
register err addr(chan_base, 0x28) "Channel Error Register" {
|
||||
_ 13 rsvd "reserved";
|
||||
desccnterr 1 rw1cs "Descriptor Count error";
|
||||
xorqerr 1 rw1cs "Xor error";
|
||||
crc_err 1 rw1cs "CRC test failed";
|
||||
unaffilerr 1 ro "Unaffiliated Error";
|
||||
_ 1 rsvd "Unused error";
|
||||
intcfgerr 1 rw1cs "Interrupt confiuguratio error";
|
||||
cmpaddrerr 1 rw1cs "Completion Address error";
|
||||
desclenerr 1 rw1cs "Description length error";
|
||||
descctrlerr 1 rw1cs "Description control error";
|
||||
wrdataerr 1 rw1cs "Write data error";
|
||||
rddataerr 1 rw1cs "Read Data error";
|
||||
dmadataerr 1 rw1cs "DMA Data Parity error";
|
||||
cdataerr 1 rw1cs "Data parity error";
|
||||
chancmderr 1 rw1cs "Channel command error";
|
||||
chanaddr 1 rw1cs "Channel address value error";
|
||||
descerr 1 rw1cs "Descriptor error";
|
||||
nxtdescerr 1 rw1cs "Next Descriptor Address error";
|
||||
dmaxfererr 1 rw1cs "DMA Transfer Destination address error";
|
||||
dmatranserr 1 rw1cs "DMA Transfer Source address error";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.23 - Channel Error Mask Register.
|
||||
*/
|
||||
register errmsk addr(chan_base, 0x2c) "Channel Error Mask Register." {
|
||||
_ 13 rsvd "reserved";
|
||||
desccnterr 1 rw1cs "Descriptor Count error";
|
||||
xorqerr 1 rw1cs "Xor error";
|
||||
crc_err 1 rw1cs "CRC test failed";
|
||||
unaffilerr 1 ro "Unaffiliated Error";
|
||||
_ 1 rsvd "Unused error";
|
||||
intcfgerr 1 rw1cs "Interrupt confiuguratio error";
|
||||
cmpaddrerr 1 rw1cs "Completion Address error";
|
||||
desclenerr 1 rw1cs "Description length error";
|
||||
descctrlerr 1 rw1cs "Description control error";
|
||||
wrdataerr 1 rw1cs "Write data error";
|
||||
rddataerr 1 rw1cs "Read Data error";
|
||||
dmadataerr 1 rw1cs "DMA Data Parity error";
|
||||
cdataerr 1 rw1cs "Data parity error";
|
||||
chancmderr 1 rw1cs "Channel command error";
|
||||
chanaddr 1 rw1cs "Channel address value error";
|
||||
descerr 1 rw1cs "Descriptor error";
|
||||
nxtdescerr 1 rw1cs "Next Descriptor Address error";
|
||||
dmaxfererr 1 rw1cs "DMA Transfer Destination address error";
|
||||
dmatranserr 1 rw1cs "DMA Transfer Source address error";
|
||||
};
|
||||
|
||||
constants dcactrl_targets "Target CPU Values" {
|
||||
dca_ctr_target_any = 0xffff "Any CPU as garget";
|
||||
};
|
||||
|
||||
/*
|
||||
* 8.5.24 - DCA Control Register
|
||||
*
|
||||
* This field is RW if CHANCNT register is 1 otherwise this register is RO
|
||||
*/
|
||||
register dcactrl addr(chan_base, 0x30) "DCA Control Register" {
|
||||
_ 16 rsvd "Reserved";
|
||||
target_cpu 16 rw "Specifies the APCI ID of the target CPU for compl writes";
|
||||
};
|
||||
};
|
||||
|
||||
85
devices/ixp2800_icp_pic0.dev
Normal file
85
devices/ixp2800_icp_pic0.dev
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ixp2800_icp_pic.dev
|
||||
*
|
||||
* DESCRIPTION: Primary interrupt controller for integrator/cp
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* This is derived from the Intel IXP2400/IXP2800 Network Processor
|
||||
* Programmer's Reference Manual (November 2003), p. 541ff
|
||||
*
|
||||
*/
|
||||
|
||||
device ixp2800_icp_pic0 msbfirst ( addr base ) "IXP2800 Integrator Primary PIC"
|
||||
{
|
||||
regtype source "Interrupt controller sources" {
|
||||
_ 4 "Reserved";
|
||||
THD96_127_B 1 "THD_RAW_STATUS_B_3";
|
||||
THD64_95_B 1 "THD_RAW_STATUS_B_2";
|
||||
THD32_63_B 1 "THD_RAW_STATUS_B_1";
|
||||
TH0_31_B 1 "THD_RAW_STATUS_B_0";
|
||||
_ 4 "Reserved";
|
||||
THD96_127_A 1 "THD_RAW_STATUS_A_3";
|
||||
THD64_95_A 1 "THD_RAW_STATUS_A_2";
|
||||
THD32_63_A 1 "THD_RAW_STATUS_A_1";
|
||||
THD0_31_A 1 "THD_RAW_STATUS_A_0";
|
||||
PCI_INT 1 "External PCI interrupt A & B";
|
||||
ME_ATTN 1 "Microengine attention register";
|
||||
PCI_DOORBELL 1 "A PCI device has set the doorbell interrupt";
|
||||
DMA2_DONE 1 "Completion status from the DMA2 engine";
|
||||
_ 1 "Reserved";
|
||||
DMA0_DONE 1 "Completion status from the DMA0 engine";
|
||||
SP_FINT 1 "Slow Port interrupt";
|
||||
PMU_INT 1 "PMU interrupt";
|
||||
TIMER_UFLW 4 "Timer underflow indicator";
|
||||
GPIO_INT 1 "interrupt request from the GPIO unit";
|
||||
UART_INT 1 "UART interrupt request";
|
||||
ERROR_SUM 1 "OR of all interrupt bits in the ErrorStatus register";
|
||||
SOFTINT 1 "Software Interrupt";
|
||||
};
|
||||
|
||||
register IRQ_STATUS ro addr (base, 0x08) "IRQ masked interrupt status"
|
||||
type(source);
|
||||
|
||||
register IRQ_RAW_STATUS ro addr (base, 0x00) "IRQ un-masked interrupt status"
|
||||
type(source);
|
||||
|
||||
register IRQ_ENABLE ro addr (base, 0x10) "Return enabled IRQs"
|
||||
type(source);
|
||||
|
||||
register IRQ_ENABLE_SET wo also addr (base, 0x10) "IRQ enable set"
|
||||
type(source);
|
||||
|
||||
register IRQ_ENABLE_CLR wo addr (base, 0x18) "IRQ enable clear"
|
||||
type(source);
|
||||
|
||||
register SOFT_INT addr (base, 0x54) "Software interrupt set" {
|
||||
_ 31 ro "Reserved";
|
||||
set 1 rw "Set or read software interrupt";
|
||||
};
|
||||
|
||||
|
||||
register FIQ_STATUS ro addr (base, 0x04) "FIQ masked interrupt status"
|
||||
type(source);
|
||||
|
||||
register FIQ_RAW_STATUS ro also addr (base, 0x00) "FIQ un-masked interrupt status"
|
||||
type(source);
|
||||
|
||||
register FIQ_ENABLE ro also addr (base, 0x0c) "Return enabled FIQs"
|
||||
type(source);
|
||||
|
||||
register FIQ_ENABLE_SET wo also addr (base, 0x0c) "FIQ enable set"
|
||||
type(source);
|
||||
|
||||
register FIQ_ENABLE_CLR wo addr (base, 0x14) "FIQ enable clear"
|
||||
type(source);
|
||||
|
||||
};
|
||||
59
devices/ixp2800_icp_pit.dev
Normal file
59
devices/ixp2800_icp_pit.dev
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* arm_icp_pit.dev
|
||||
*
|
||||
* DESCRIPTION: Timers for for integrator/cp
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* This is derived from the Intel IXP2400/IXP2800 Network Processor
|
||||
* Programmer's Reference Manual (November 2003), p. 352ff
|
||||
*
|
||||
*/
|
||||
|
||||
device ixp2800_icp_pit msbfirst ( addr base ) "IXP2800 Integrator timer"
|
||||
{
|
||||
// p.352, section 5.6.5.1
|
||||
constants scale "Timer scaling factors" {
|
||||
none = 0b00 "Use clock to trigger counter";
|
||||
div16 = 0b01 "Use clock devided by 16 to trigger counter";
|
||||
div256 = 0b10 "Use clock devided by 256 to trigger counter";
|
||||
gpio = 0b11 "Use GPIO pins";
|
||||
};
|
||||
|
||||
|
||||
register CONTROL addr(base, 0x00) "Control register" {
|
||||
_ 24 ro "Reserved";
|
||||
ACT 1 rw "Activate timer";
|
||||
_ 3 ro "Reserved";
|
||||
PSS 2 rw type(scale) "Select the pre-scalar";
|
||||
_ 2 ro "Reserved";
|
||||
};
|
||||
|
||||
register LOADING addr(base, 0x10) "Load value for timer" {
|
||||
CLV 32 rw "Counter initial value";
|
||||
};
|
||||
|
||||
register STATUS addr(base, 0x20) "Current value for timer" {
|
||||
CSV 32 rw "Current counter value";
|
||||
};
|
||||
|
||||
register CLEAR addr(base, 0x30) "Interrupt clear" {
|
||||
_ 31 ro "Reserved";
|
||||
ICL 1 rw "Write one to clear interrupt";
|
||||
};
|
||||
|
||||
register WATCHDOG addr(base, 0x40) "Enable timer 4 to be a watchdog timer" {
|
||||
_ 31 ro "Reserved";
|
||||
WDE 1 rw "Write one to enable watchdog";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
150
devices/ixp2800_uart.dev
Normal file
150
devices/ixp2800_uart.dev
Normal file
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* netronome_uart.dev
|
||||
*
|
||||
* DESCRIPTION: Netronome Universal Asynchronous Receiver Transmitter
|
||||
* similar to 16550 UART
|
||||
*
|
||||
* This is derived from the Intel IXP2400/IXP2800 Network Processor
|
||||
* Programmer's Reference Manual (November 2003), p. 364ff
|
||||
*/
|
||||
|
||||
device ixp2800_uart msbfirst ( addr base ) "Netronome UART Memory Represenation" {
|
||||
|
||||
|
||||
|
||||
/* Bram: I cannot verify this, maybe p.365 gives hints? */
|
||||
/* ******************************************************/
|
||||
|
||||
constants divisor "Baud Rate Divisor" {
|
||||
baud50 = 2304 "50 bps";
|
||||
baud75 = 1536 "75 bps";
|
||||
baud110 = 1047 "110 bps";
|
||||
baud134_5 = 857 "134.5 bps";
|
||||
baud150 = 768 "150 bps";
|
||||
baud300 = 384 "300 bps";
|
||||
baud600 = 192 "600 bps";
|
||||
baud1200 = 96 "1200 bps";
|
||||
baud1800 = 64 "1800 bps";
|
||||
baud2000 = 58 "2000 bps";
|
||||
baud2400 = 48 "2400 bps";
|
||||
baud4800 = 24 "4800 bps";
|
||||
baud7200 = 16 "7200 bps";
|
||||
baud9600 = 12 "9600 bps";
|
||||
baud19200 = 6 "19200 bps";
|
||||
baud38400 = 3 "38400 bps";
|
||||
baud57600 = 2 "57600 bps";
|
||||
baud115200 = 1 "115200 bps";
|
||||
};
|
||||
|
||||
constants interrupt_source "Interrupt Source Encoded" {
|
||||
request_data = 0b01 "Transmit FIFO requests data";
|
||||
recv_data_av = 0b10 "Received Data Available";
|
||||
recv_error = 0b11 "Receive error";
|
||||
};
|
||||
|
||||
constants fifo_type "FIFO Mode Enable Status" {
|
||||
no_fifo = 0b00 "No FIFO";
|
||||
fifo_enabled = 0b11 "FIFO enabled";
|
||||
};
|
||||
|
||||
constants interrupt_trigger "Interrupt Trigger Level" {
|
||||
bytes01 = 0b00 "1 byte in FIFO causes interrupt";
|
||||
bytes08 = 0b01 "8 byte in FIFO causes interrupt";
|
||||
bytes16 = 0b10 "16 byte in FIFO causes interrupt";
|
||||
bytes32 = 0b11 "32 byte in FIFO causes interrupt";
|
||||
};
|
||||
|
||||
constants char_len "Character Length" {
|
||||
bits5 = 0b00 "5 Bits";
|
||||
bits6 = 0b01 "6 Bits";
|
||||
bits7 = 0b10 "7 Bits";
|
||||
bits8 = 0b11 "8 Bits";
|
||||
};
|
||||
|
||||
register RBR ro addr ( base, 0x0 ) "Receiver buffer" {
|
||||
_ 24 ro "Reserved";
|
||||
rbr 8 ro "Receive Buffer Register. Data byte received, least significant bit first";
|
||||
};
|
||||
|
||||
register THR also addr ( base , 0x0 ) "Transmitter holding" {
|
||||
_ 24 ro "Reserved";
|
||||
thr 8 wo "Data byte transmitted, least significant bit first";
|
||||
};
|
||||
|
||||
register DLRL also addr (base , 0x0) "Divisor Latch low" {
|
||||
_ 24 ro "Reserved";
|
||||
lb 8 rw "Low byte for generating baud rate";
|
||||
};
|
||||
|
||||
register DLRH addr (base , 0x4) "Divisor Latch high" {
|
||||
_ 24 ro "Reserved";
|
||||
hb 8 rw "High byte for generating baud rate";
|
||||
};
|
||||
|
||||
register IER also addr ( base, 0x4 ) "Interrupt enable" {
|
||||
_ 25 ro "Reserved";
|
||||
uue 1 rw "UART Unit Enable";
|
||||
nrze 1 rw "NRZ coding Enable";
|
||||
rtoie 1 rw "Receiver Time out Interrupt Enable";
|
||||
_ 1 rw "Reserved";
|
||||
rlse 1 rw "Receiver Line Status Interrupt Enable";
|
||||
tie 1 rw "Transmit Data request Interrupt Enable";
|
||||
ravie 1 rw "Receiver Data Available Interrupt Enable";
|
||||
};
|
||||
|
||||
register iir addr ( base, 0x8 ) "Interrupt identification" {
|
||||
_ 24 ro "Reserved";
|
||||
FIFOES 2 ro type(fifo_type) "FIFO Mode Enable Status";
|
||||
_ 2 ro "Reserved";
|
||||
TOD 1 ro "Time Out Detected (0: No time out interrupt is pending)";
|
||||
IID 2 ro type(interrupt_source) "Interrupt Source Encoded";
|
||||
IP 1 ro "Interrupt Pending";
|
||||
};
|
||||
|
||||
register fcr rw also addr ( base, 0x8 ) "FIFO control" {
|
||||
_ 24 ro "Reserved";
|
||||
ITL 2 wo type(interrupt_trigger) "Interrupt Trigger Level";
|
||||
_ 3 ro "Reserved";
|
||||
RESETTF 1 wo "Reset transmitter FIFO";
|
||||
RESETRF 1 wo "Reset Receiver FIFO";
|
||||
TRFIFOE 1 wo "Transmit and Receive FIFO Enable";
|
||||
};
|
||||
|
||||
register LCR addr ( base, 0xC ) "Line control" {
|
||||
_ 24 ro "Reserved";
|
||||
dlab 1 rw "Divisor latch access";
|
||||
sb 1 rw "Set break";
|
||||
stkyp 1 rw "Stick parity";
|
||||
eps 1 rw "Even parity select";
|
||||
pen 1 rw "Parity enable";
|
||||
stb 1 rw "Number of stop bits";
|
||||
wls 2 rw type(char_len) "Word length select";
|
||||
};
|
||||
|
||||
register LSR addr ( base, 0x14 ) "Line status" {
|
||||
_ 24 ro "Reserved";
|
||||
fifoe 1 ro "FIFO Error Status ";
|
||||
temt 1 ro "Transmitter empty";
|
||||
tdrq 1 ro "Transmit Data Request";
|
||||
bi 1 ro "Break interrupt";
|
||||
fe 1 ro "Framing error";
|
||||
pe 1 ro "Parity error";
|
||||
oe 1 ro "Overrun error";
|
||||
dr 1 ro "Data ready";
|
||||
};
|
||||
|
||||
|
||||
register spr addr ( base, 0x1c ) "Scratchpad register" {
|
||||
_ 24 ro "Reserved";
|
||||
scratch 8 rw "No effect on UART functionality";
|
||||
};
|
||||
|
||||
};
|
||||
26
devices/lpc_bridge.dev
Normal file
26
devices/lpc_bridge.dev
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_bridge.dev
|
||||
*
|
||||
* DESCRIPTION: this maps to the PCI configuration space of the LPC bridge
|
||||
* and maps currently only the RCBA register, so that we can
|
||||
* access the base of the chipset configuration which we need
|
||||
* to implement the HPET timer
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
device lpc_bridge msbfirst ( pci base ) "LPC bridge PCI config space" {
|
||||
register rcba rw pci( base, 0xf0 ) "RCBA" {
|
||||
baseaddr 18 "Base Address";
|
||||
_ 13;
|
||||
enable 1 "Enable";
|
||||
};
|
||||
};
|
||||
135
devices/lpc_dma.dev
Normal file
135
devices/lpc_dma.dev
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (c) 2007, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_dma.dev
|
||||
*
|
||||
* DESCRIPTION: Legacy DMA controllers on the LPC (low pin count, or
|
||||
* legacy PC) bridge function of a typical Intel IHC
|
||||
* (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
*
|
||||
*/
|
||||
|
||||
device LPC_dma ( io base ) "LPC DMA registers" {
|
||||
|
||||
//
|
||||
// Section 21.2: DMA I/O registers
|
||||
//
|
||||
|
||||
// Yuck. There's a baroque protocol for accessing these
|
||||
// registers, which I'm not even going to attempt to express yet.
|
||||
|
||||
register base_a0 wo io(base, 0x00 ) "ch0 base addr" type(uint8);
|
||||
register base_a1 wo io(base, 0x02 ) "ch1 base addr" type(uint8);
|
||||
register base_a2 wo io(base, 0x04 ) "ch2 base addr" type(uint8);
|
||||
register base_a3 wo io(base, 0x06 ) "ch3 base addr" type(uint8);
|
||||
register base_a5 wo io(base, 0xc4 ) "ch5 base addr" type(uint8);
|
||||
register base_a6 wo io(base, 0xc8 ) "ch6 base addr" type(uint8);
|
||||
register base_a7 wo io(base, 0xcc ) "ch7 base addr" type(uint8);
|
||||
|
||||
register cur_a0 ro also io(base, 0x00 ) "ch0 cur addr" type(uint8);
|
||||
register cur_a1 ro also io(base, 0x02 ) "ch1 cur addr" type(uint8);
|
||||
register cur_a2 ro also io(base, 0x04 ) "ch2 cur addr" type(uint8);
|
||||
register cur_a3 ro also io(base, 0x06 ) "ch3 cur addr" type(uint8);
|
||||
register cur_a5 ro also io(base, 0xc4 ) "ch5 cur addr" type(uint8);
|
||||
register cur_a6 ro also io(base, 0xc8 ) "ch6 cur addr" type(uint8);
|
||||
register cur_a7 ro also io(base, 0xcc ) "ch7 cur addr" type(uint8);
|
||||
|
||||
register base_c0 wo also io(base, 0x00 ) "ch0 base count" type(uint8);
|
||||
register base_c1 wo also io(base, 0x02 ) "ch1 base count" type(uint8);
|
||||
register base_c2 wo also io(base, 0x04 ) "ch2 base count" type(uint8);
|
||||
register base_c3 wo also io(base, 0x06 ) "ch3 base count" type(uint8);
|
||||
register base_c5 wo also io(base, 0xc4 ) "ch5 base count" type(uint8);
|
||||
register base_c6 wo also io(base, 0xc8 ) "ch6 base count" type(uint8);
|
||||
register base_c7 wo also io(base, 0xcc ) "ch7 base count" type(uint8);
|
||||
|
||||
register cur_c0 ro also io(base, 0x00 ) "ch0 cur count" type(uint8);
|
||||
register cur_c1 ro also io(base, 0x02 ) "ch1 cur count" type(uint8);
|
||||
register cur_c2 ro also io(base, 0x04 ) "ch2 cur count" type(uint8);
|
||||
register cur_c3 ro also io(base, 0x06 ) "ch3 cur count" type(uint8);
|
||||
register cur_c5 ro also io(base, 0xc4 ) "ch5 cur count" type(uint8);
|
||||
register cur_c6 ro also io(base, 0xc8 ) "ch6 cur count" type(uint8);
|
||||
register cur_c7 ro also io(base, 0xcc ) "ch7 cur count" type(uint8);
|
||||
|
||||
register mem_lp0 rw io(base, 0x87 ) "ch0 mem low page" type(uint8);
|
||||
register mem_lp1 rw io(base, 0x83 ) "ch1 mem low page" type(uint8);
|
||||
register mem_lp2 rw io(base, 0x81 ) "ch2 mem low page" type(uint8);
|
||||
register mem_lp3 rw io(base, 0x82 ) "ch3 mem low page" type(uint8);
|
||||
register mem_lp5 rw io(base, 0x8b ) "ch5 mem low page" type(uint8);
|
||||
register mem_lp6 rw io(base, 0x89 ) "ch6 mem low page" type(uint8);
|
||||
register mem_lp7 rw io(base, 0x8a ) "ch7 mem low page" type(uint8);
|
||||
|
||||
regtype dmacmd "DMA command" {
|
||||
_ 2 mbz;
|
||||
chgrp_en 1 "channel group enable";
|
||||
_ 1 mbz;
|
||||
grp_arb 1 "group arbitration priority";
|
||||
_ 3 mbz;
|
||||
};
|
||||
register dmacmd_03 wo io(base, 0x08 ) "DMA cmd ch0-3" type(dmacmd);
|
||||
register dmacmd_47 wo io(base, 0xd0 ) "DMA cmd ch4-7" type(dmacmd);
|
||||
|
||||
regtype dmasta "DMA status" {
|
||||
ch_tcs 4 "Channel terminal count status";
|
||||
ch_reqs 4 "Channel request status";
|
||||
};
|
||||
register dmasta_03 ro also io(base, 0x08 ) "DMA status ch0-3" type(dmasta);
|
||||
register dmasta_47 ro also io(base, 0xd0 ) "DMA status ch4-7" type(dmasta);
|
||||
|
||||
regtype dma_wrsmsk "DMA write single mask" {
|
||||
ch_sel 2 "channel select";
|
||||
mask 1 "Channel mask select";
|
||||
_ 5 mbz;
|
||||
};
|
||||
register dma_wrsmsk_03 wo io(base, 0x0a ) "DMA wrt single msk ch0-3" type(dma_wrsmsk);
|
||||
register dma_wrsmsk_47 wo io(base, 0xd4 ) "DMA wrt single msk ch4-7" type(dma_wrsmsk);
|
||||
|
||||
constants dma_trans_type "DMA transaction type" {
|
||||
verify = 0b00;
|
||||
write = 0b01;
|
||||
read = 0b10;
|
||||
illegal = 0b11;
|
||||
};
|
||||
constants dma_trans_mode "DMA transaction mode" {
|
||||
demand = 0b00;
|
||||
single = 0b01;
|
||||
cascade = 0b11;
|
||||
};
|
||||
|
||||
regtype dmach_mode "channel mode" {
|
||||
ch_sel 2 "channel select";
|
||||
trans_tp 2 type(dma_trans_type) "transfer type";
|
||||
auto_init 1 "Autoinitialize enable";
|
||||
inc_dec 1 "Address inc/dec select";
|
||||
trans_mode 2 type(dma_trans_mode) "transfer mode";
|
||||
};
|
||||
|
||||
register dmach_mode_03 wo io(base, 0x0b ) "chan mode ch0-3" type(dmach_mode);
|
||||
register dmach_mode_47 wo io(base, 0xd6 ) "chan mode ch4-7" type(dmach_mode);
|
||||
|
||||
register dma_clbp_03 wo io(base, 0x0c ) "clr byte ptr ch0-3" type(uint8);
|
||||
register dma_clbp_47 wo io(base, 0xd8 ) "clr byte ptr ch4-7" type(uint8);
|
||||
|
||||
register dma_mclr_03 wo io(base, 0x0d ) "master clr ch0-3" type(uint8);
|
||||
register dma_mclr_47 wo io(base, 0xda ) "master clr ch4-7" type(uint8);
|
||||
|
||||
register dma_clrmsk_03 wo io(base, 0x0e ) "clr mask ch0-3" type(uint8);
|
||||
register dma_clrmsk_47 wo io(base, 0xdc ) "clr mask ch4-7" type(uint8);
|
||||
|
||||
regtype dma_wrmsk "write all mask" {
|
||||
chan 4 "Channel mask bits";
|
||||
_ 4 mbz;
|
||||
};
|
||||
register dma_wrmsk_03 rw io(base, 0x0f ) "write all mask ch0-3" type(dma_wrmsk);
|
||||
register dma_wrmsk_47 rw io(base, 0xde ) "write all mask ch4-7" type(dma_wrmsk);
|
||||
|
||||
};
|
||||
|
||||
102
devices/lpc_ioapic.dev
Normal file
102
devices/lpc_ioapic.dev
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_ioapic.dev
|
||||
*
|
||||
* DESCRIPTION: Definition of the LPC (low pin count, or legacy PC)
|
||||
* bridge function of a typical Intel IHC (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
*/
|
||||
|
||||
device lpc_ioapic lsbfirst (addr base) "LPC IHC I/O APIC function" {
|
||||
//
|
||||
// Advanced Programmable Interrupt Controller registers: section 21.5
|
||||
//
|
||||
|
||||
space ioapic(index) stepwise(4) "I/O APIC register space";
|
||||
|
||||
constants delivery_mode "Delivery Mode" {
|
||||
fixed = 0b000 "Fixed";
|
||||
lowest = 0b001 "Lowest Priority";
|
||||
smi = 0b010 "SMI (System Management Interrupt)";
|
||||
nmi = 0b100 "NMI (Non-maskable Interrupt)";
|
||||
init = 0b101 "INIT";
|
||||
extint = 0b111 "ExtINT";
|
||||
};
|
||||
|
||||
constants dest_mode "Destination Mode" {
|
||||
physical = 0b0 "Physical";
|
||||
logical = 0b1 "Logical";
|
||||
};
|
||||
|
||||
constants delivery_status "Delivery Status" {
|
||||
idle = 0b0 "Idle";
|
||||
pending = 0b1 "Pending";
|
||||
};
|
||||
|
||||
constants polarity "Interrupt Input Pin Polarity" {
|
||||
active_high = 0b0 "Active high";
|
||||
active_low = 0b1 "Active low";
|
||||
};
|
||||
|
||||
constants trigger_mode "Trigger Mode" {
|
||||
edge = 0b0 "Edge Triggered";
|
||||
level = 0b1 "Level Triggered";
|
||||
};
|
||||
|
||||
register ind rw addr(base, 0x0) "Index" type(uint32);
|
||||
register wdw rw addr(base, 0x10) "Window" type(uint32);
|
||||
|
||||
register eoir wo addr(base, 0x40) "EOI" {
|
||||
rec 8 "Redirection Entry Clear";
|
||||
_ 24 mbz;
|
||||
};
|
||||
|
||||
register id rw ioapic(0x0) "Identification" {
|
||||
_ 15;
|
||||
spb 1 "Scratchpad bit";
|
||||
_ 8;
|
||||
id 4 "APIC ID";
|
||||
_ 4;
|
||||
};
|
||||
|
||||
register ver ro ioapic(0x1) "Version" {
|
||||
ver 8 "Version";
|
||||
_ 7;
|
||||
prq 1 "Pin assertion register non-support";
|
||||
mre 8 "Maximum redirection entries";
|
||||
_ 8;
|
||||
};
|
||||
|
||||
register arb ro ioapic(0x2) "Arbitration" {
|
||||
_ 24;
|
||||
id 4 "IOAPIC Arbitration ID";
|
||||
_ 4;
|
||||
};
|
||||
|
||||
|
||||
regtype redir_tbl "Redirection Table" {
|
||||
vector 8 "Vector";
|
||||
mode 3 type(delivery_mode) "Delivery mode";
|
||||
destmode 1 type(dest_mode) "Destination mode";
|
||||
status 1 ro type(delivery_status) "Delivery status";
|
||||
polarity 1 type(polarity) "Interrupt input pin polarity";
|
||||
rirr 1 ro "Remote IRR";
|
||||
trigger 1 type(trigger_mode) "Trigger mode";
|
||||
mask 1 "Mask";
|
||||
_ 31;
|
||||
edid 8 ro "Extended destination ID";
|
||||
dest 8 "Destination";
|
||||
};
|
||||
|
||||
// XXX: Support up to 24 redirection table entries.
|
||||
regarray redirtbl rw ioapic(0x10)[24] type(redir_tbl);
|
||||
};
|
||||
75
devices/lpc_kbd.dev
Normal file
75
devices/lpc_kbd.dev
Normal file
@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, 2009, 2011, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_kbd.dev
|
||||
*
|
||||
* DESCRIPTION: Legacy keyboard and mouse port
|
||||
*
|
||||
* This file does not fully describe the 8042, which is not supported
|
||||
* on most PCs anymore.
|
||||
*
|
||||
* Ref: http://www.mcamafia.de/pdf/ibm_hitrc07.pdf
|
||||
*/
|
||||
|
||||
device lpc_kbd msbfirst (io base) "LPC Keyboard" {
|
||||
register input ro io(base, 0) "Input" type(uint8);
|
||||
register status ro io(base, 4) "Status" {
|
||||
perr 1 "Parity error";
|
||||
timeout 1 "General timeout";
|
||||
aobf 1 "Auxiliary device output buffer full";
|
||||
is 1 "Inhibit switch";
|
||||
cd 1 "Command/data";
|
||||
sf 1 "System flag";
|
||||
ibf 1 "Input buffer full";
|
||||
obf 1 "Output buffer full";
|
||||
};
|
||||
|
||||
register output wo also io(base, 0) "Output" type(uint8);
|
||||
|
||||
constants cmd "Command" {
|
||||
/* XXX: I don't attempt to encode the silly read/write RAM commands,
|
||||
* since they mix a bitfield and a constant in the same register.
|
||||
*/
|
||||
rd_ccmd = 0x20 "Read controller command byte";
|
||||
wr_ccmd = 0x60 "Write controller command byte";
|
||||
aux_disable = 0xa7 "Disable auxiliary device interface";
|
||||
aux_enable = 0xa8 "Enable auxiliary device interface";
|
||||
kbd_disable = 0xad "Disable keyboard interface";
|
||||
kbd_enable = 0xae "Enable keyboard interface";
|
||||
read_input = 0xc0 "Read input port";
|
||||
poll_input_low = 0xc1 "Poll input port low";
|
||||
poll_input_high = 0xc2 "Poll input port high";
|
||||
read_output = 0xd0 "Read output port";
|
||||
write_output = 0xd1 "Write output port";
|
||||
write_kbd_out = 0xd2 "Write keyboard output buffer";
|
||||
write_aux_out = 0xd3 "Write auxiliary device output buffer";
|
||||
write_aux = 0xd4 "Write to auxiliary device";
|
||||
};
|
||||
|
||||
// FIXME: why won't Mackerel allow this?
|
||||
// register command wo also io(base, 4) "Command" type(command);
|
||||
register command wo also io(base, 4) "Command" {
|
||||
cmd 8 type(cmd) "Command";
|
||||
};
|
||||
|
||||
/* This is the format of the "controller command" byte, which is data
|
||||
* returned in response to an 0x20 command, and not to be confused with
|
||||
* the command register, which is write-only.
|
||||
*/
|
||||
regtype ccmd "Controller command byte" {
|
||||
_ 1;
|
||||
kbd_xl 1 "Keyboard translate";
|
||||
aux_dis 1 "Disable auxiliary device";
|
||||
kbd_dis 1 "Disable keyboard";
|
||||
_ 1;
|
||||
sysflg 1 "System flag";
|
||||
aux_int 1 "Enable auxiliary interrupt";
|
||||
kbd_int 1 "Enable keyboard interrupt";
|
||||
};
|
||||
};
|
||||
221
devices/lpc_pci_config.dev
Normal file
221
devices/lpc_pci_config.dev
Normal file
@ -0,0 +1,221 @@
|
||||
/*
|
||||
* Copyright (c) 2007, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc.dev
|
||||
*
|
||||
* DESCRIPTION: Definition of the PCI config space for the LPC (low
|
||||
* pin count, or legacy PC) bridge function of a typical
|
||||
* Intel IHC (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
* Other parts of this chapter have been broken out into other
|
||||
* sections, because frankly, they're huge.
|
||||
*
|
||||
*/
|
||||
|
||||
device LPC_pci ( addr conf ) "LPC IHC function" {
|
||||
|
||||
//
|
||||
// This is big. First:
|
||||
// Section 21.1: PCI configuration space.
|
||||
//
|
||||
|
||||
register vid ro addr(conf, 0x00) "Vendor ID" type(uint16);
|
||||
register did ro addr(conf, 0x02) "Device ID" {
|
||||
fdcomp 4 "FDCOMP fuse";
|
||||
id 12 always(0x267) "device id";
|
||||
};
|
||||
|
||||
register pcicmd addr(conf, 0x04) "PCI command" {
|
||||
iose 1 ro "I/O space enable";
|
||||
mse 1 ro "Memory space enable";
|
||||
bme 1 ro "Bus master enable";
|
||||
sce 1 ro always(0) "Special cycle enable";
|
||||
mwie 1 ro always(0) "Memory write and invalidate enable";
|
||||
vps 1 ro always(0) "VGA palette snoop";
|
||||
pere 1 rw "Parity error response enable";
|
||||
wcc 1 ro always(0) "Wait cycle control";
|
||||
serr_en 1 rw "SERR# enable";
|
||||
fbe 1 ro always(0) "Fast back-to-back enable";
|
||||
_ 6 rsvd;
|
||||
};
|
||||
|
||||
register pcists addr(conf, 0x06) "PCI status" {
|
||||
_ 3 rsvd;
|
||||
is 1 ro "Interrupt status";
|
||||
clist 1 ro "Capabilities list";
|
||||
c66mhz 1 rsvd "66 Mhz capable";
|
||||
_ 1 rsvd;
|
||||
fbc 1 rsvd "Fast back-to-back capable";
|
||||
dped 1 rwc "Data parity error detected";
|
||||
dev_sts 2 ro "DEVSEL# timing status";
|
||||
sta 1 rwc "Signalled target abort";
|
||||
rta 1 rwc "Received target abort";
|
||||
rma 1 rwc "Master abort status";
|
||||
sse 1 rwc "Signalled system error";
|
||||
dpe 1 rwc "Detected parity error";
|
||||
};
|
||||
|
||||
register rid rwo addr(conf, 0x08) "Revision id" type(uint8);
|
||||
register pi ro addr(conf, 0x09) "Programming interface" type(uint8);
|
||||
register scc ro addr(conf, 0x0a) "Sub class code" type(uint8);
|
||||
register bcc ro addr(conf, 0x0b) "Base class code" type(uint8);
|
||||
register plt ro addr(conf, 0x0d) "Primary latency timer" type(uint8);
|
||||
register headtyp ro addr(conf, 0x0e) "Header type" type(uint8);
|
||||
|
||||
register ss rwo addr(conf, 0x2c) "Subsystem identifiers" {
|
||||
ssvid 16 rwo "Subsystem vendor id";
|
||||
ssid 16 rwo "Subsystem id";
|
||||
};
|
||||
|
||||
register pmbase addr(conf, 0x40) "ACPI base address" {
|
||||
rte 1 ro always(1) "Resource type indicator";
|
||||
_ 6 rsvd;
|
||||
base 9 rw "Base address";
|
||||
_ 16 rsvd;
|
||||
};
|
||||
|
||||
constants sci_irq "SCI IRQ select map" {
|
||||
irq9 = 0b000;
|
||||
irq10 = 0b001;
|
||||
irq11 = 0b010;
|
||||
irq20 = 0b100;
|
||||
irq21 = 0b101;
|
||||
irq22 = 0b110;
|
||||
irq23 = 0b111;
|
||||
};
|
||||
|
||||
register acpi_cntl addr(conf, 0x44) "ACPI control" {
|
||||
sci_irq_sel 3 rw type(sci_irq) "SCI IRQ select";
|
||||
_ 4 rsvd;
|
||||
acpi_en 1 rw "ACPI enable";
|
||||
};
|
||||
|
||||
register gpiobase addr(conf, 0x48) "GPIO base address" {
|
||||
_ 1 ro always(1);
|
||||
_ 5 mbz;
|
||||
ba 10 rw "Base address";
|
||||
_ 16 mbz;
|
||||
};
|
||||
|
||||
register gc addr(conf, 0x4c) "GPIO control" {
|
||||
_ 4 rsvd;
|
||||
en 1 rw "GPIO enable";
|
||||
_ 3 rsvd;
|
||||
};
|
||||
|
||||
regtype pirq_rout "PIRQ routing" {
|
||||
routing 4 rw "IRQ routing";
|
||||
_ 3 rsvd;
|
||||
irqen 1 rw "Interrupt routing enable";
|
||||
};
|
||||
register pirqa_rout addr(conf, 0x60) type(pirq_rout) "PIRQA routing control";
|
||||
register pirqb_rout addr(conf, 0x61) type(pirq_rout) "PIRQB routing control";
|
||||
register pirqc_rout addr(conf, 0x62) type(pirq_rout) "PIRQC routing control";
|
||||
register pirqd_rout addr(conf, 0x63) type(pirq_rout) "PIRQD routing control";
|
||||
register pirqe_rout addr(conf, 0x68) type(pirq_rout) "PIRQE routing control";
|
||||
register pirqf_rout addr(conf, 0x69) type(pirq_rout) "PIRQF routing control";
|
||||
register pirqg_rout addr(conf, 0x6A) type(pirq_rout) "PIRQG routing control";
|
||||
register pirqh_rout addr(conf, 0x6B) type(pirq_rout) "PIRQH routing control";
|
||||
|
||||
register sirq_cntl addr(conf, 0x64) "Serial IRQ control" {
|
||||
sfpw 2 rw "Start frame pulse width";
|
||||
sirqsz 4 ro "Serial IRQ frame size";
|
||||
sirqmd 1 rw "Serial IRQ mode select";
|
||||
sirqen 1 rw "Serial IRQ enable";
|
||||
};
|
||||
|
||||
register lpc_iodec addr(conf, 0x80) "I/O decode ranges" {
|
||||
coma 3 rw "COMA decode";
|
||||
_ 1 rsvd;
|
||||
comb 3 rw "COMB decode";
|
||||
_ 1 rsvd;
|
||||
lpt 2 rw "LPT decode";
|
||||
_ 2 rsvd;
|
||||
fdd 1 rw "FDD decode";
|
||||
_ 3 rsvd;
|
||||
};
|
||||
|
||||
register lpc_en addr(conf, 0x82) "LPC i/f enables" {
|
||||
coma 1 rw "Com port A";
|
||||
comb 1 rw "Com port B";
|
||||
lpt 1 rw "Parallel port";
|
||||
fdd 1 rw "Floppy";
|
||||
_ 4 rsvd;
|
||||
gamel 1 rw "Low gameport";
|
||||
gameh 1 rw "High gameport";
|
||||
kbd 1 rw "Keyboard";
|
||||
mc 1 rw "Microcontroller";
|
||||
cnf1 1 rw "Super I/O";
|
||||
cnf2 1 rw "Microcontroller #2";
|
||||
_ 2 rsvd;
|
||||
};
|
||||
|
||||
register gen1_dec addr(conf, 0x84) "Generic decode range 1" {
|
||||
en 1 rw "Enable";
|
||||
_ 6 rsvd;
|
||||
base 9 rw "Base address";
|
||||
};
|
||||
|
||||
register gen2_dec addr(conf, 0x88) "Generic decode range 2" {
|
||||
en 1 rw "Enable";
|
||||
_ 3 rsvd;
|
||||
base 12 rw "Base address";
|
||||
};
|
||||
|
||||
register fwh_sel1 addr(conf, 0xd0) "Firmware hub select 1" {
|
||||
idsel_c0 4 rw "IDSEL for ffc00000 & ff800000";
|
||||
idsel_c8 4 rw "IDSEL for ffc80000 & ff880000";
|
||||
idsel_d0 4 rw "IDSEL for ffd00000 & ff900000";
|
||||
idsel_d8 4 rw "IDSEL for ffd80000 & ff980000";
|
||||
idsel_e0 4 rw "IDSEL for ffe00000 & ffa00000";
|
||||
idsel_e8 4 rw "IDSEL for ffe80000 & ffa80000";
|
||||
idsel_f0 4 rw "IDSEL for fff00000 & ffb00000";
|
||||
idsel_f8 4 ro "IDSEL for fff80000 & ffb80000";
|
||||
};
|
||||
|
||||
register fwh_sel2 addr(conf, 0xd4) "Firmware hub select 2" {
|
||||
idsel_40 4 rw "IDSEL for ff400000 & ff000000";
|
||||
idsel_50 4 rw "IDSEL for ff500000 & ff100000";
|
||||
idsel_60 4 rw "IDSEL for ff600000 & ff200000";
|
||||
idsel_70 4 rw "IDSEL for ff700000 & ff300000";
|
||||
}
|
||||
|
||||
register fwh_dec_en1 addr(conf, 0xd8) "Firmware hub decode enable" {
|
||||
en_40 1 rw "enable for ff400000 & ff000000";
|
||||
en_50 1 rw "enable for ff500000 & ff100000";
|
||||
en_60 1 rw "enable for ff600000 & ff200000";
|
||||
en_70 1 rw "enable for ff700000 & ff300000";
|
||||
_ 2 rsvd;
|
||||
en_leg_e 1 rw "enable legacy e0000";
|
||||
en_leg_f 1 rw "enable legacy f0000";
|
||||
en_c0 1 rw "enable for ffc00000 & ff800000";
|
||||
en_c8 1 rw "enable for ffc80000 & ff880000";
|
||||
en_d0 1 rw "enable for ffd00000 & ff900000";
|
||||
en_d8 1 rw "enable for ffd80000 & ff980000";
|
||||
en_e0 1 rw "enable for ffe00000 & ffa00000";
|
||||
en_e8 1 rw "enable for ffe80000 & ffa80000";
|
||||
en_f0 1 rw "enable for fff00000 & ffb00000";
|
||||
en_f8 1 ro "enable for fff80000 & ffb80000";
|
||||
};
|
||||
|
||||
register bios_cntl addr(conf, 0xdc) "BIOS control" {
|
||||
bioswe 1 rw "BIOS write enable";
|
||||
ble 1 rw "BIOS lock enable";
|
||||
_ 6 rsvd;
|
||||
};
|
||||
|
||||
register rcba addr(conf, 0xf0) "Root complex base address" {
|
||||
en 1 rw "Enable";
|
||||
_ 13 rsvd;
|
||||
ba 18 rw "Base address";
|
||||
};
|
||||
};
|
||||
|
||||
138
devices/lpc_pic.dev
Normal file
138
devices/lpc_pic.dev
Normal file
@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_pic.dev
|
||||
*
|
||||
* DESCRIPTION: Definition of the LPC (low pin count, or legacy PC)
|
||||
* bridge function of a typical Intel IHC (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
*
|
||||
*/
|
||||
|
||||
device lpc_pic lsbfirst (io base) "LPC IHC PIC function" {
|
||||
//
|
||||
// 8259 PIC registers: section 21.4
|
||||
//
|
||||
|
||||
constants rrc "Register read command" {
|
||||
read_irq = 0b10 "Read IRQ register";
|
||||
read_is = 0b11 "Read IS register";
|
||||
};
|
||||
|
||||
constants rsleoi "Rotate and EOI codes" {
|
||||
raeoic = 0b000 "Rotate in auto EOI mode (clear)";
|
||||
eoi = 0b001 "Non-specific EOI command";
|
||||
seoi = 0b011 "Specific EOI command";
|
||||
raeois = 0b100 "Rotate in auto EOI mode (set)";
|
||||
reoi = 0b101 "Rotate on non-specific EOI command";
|
||||
sp = 0b110 "Set priority command";
|
||||
rseoi = 0b111 "Rotate on specific EOI command";
|
||||
};
|
||||
|
||||
regtype icw1 "Initialization Command Word 1" {
|
||||
_ 1 mb1;
|
||||
_ 1 mbz; // Specify cascade mode
|
||||
_ 1 mbz;
|
||||
ltim 1 "Edge / Level bank select (ignored)";
|
||||
_ 1 mb1;
|
||||
_ 3 mbz;
|
||||
};
|
||||
|
||||
regtype icw2 "Initialization Command Word 2" {
|
||||
req_level 3 "Interrupt request level";
|
||||
base 5 "Interrupt vector base address";
|
||||
};
|
||||
|
||||
regtype pic_master_icw3 "Master Controller Initialization Command Word 3" {
|
||||
_ 2 mbz;
|
||||
cascade 1 "Cascaded PIC IRQ connection";
|
||||
_ 5 mbz;
|
||||
};
|
||||
|
||||
regtype pic_slave_icw3 "Slave Controller Initialization Command Word 3" {
|
||||
slave_id 3 "Slave Identification Code";
|
||||
_ 5 mbz;
|
||||
};
|
||||
|
||||
regtype icw4 "Initialization Command Word 4" {
|
||||
_ 1 mb1;
|
||||
aeoi 1 "Automatic End of Interrupt";
|
||||
_ 1 mbz;
|
||||
_ 1 mbz;
|
||||
sfnm 1 "Special fully nested mode";
|
||||
_ 3 mbz;
|
||||
};
|
||||
|
||||
/*
|
||||
regtype ocw1 "Operational Control Word 1 (Interrupt Mask)" {
|
||||
irq_mask 8 type(uint8) "Interrupt request mask";
|
||||
};
|
||||
*/
|
||||
|
||||
regtype ocw2 "Operational Control Word 2" {
|
||||
level 3 "Interrupt level select";
|
||||
_ 2 mbz;
|
||||
rsleoi 3 type(rsleoi) "Rotate and EOI Codes";
|
||||
};
|
||||
|
||||
regtype ocw3 "Operational Control Word 3" {
|
||||
rrc 2 type(rrc) "Register read command";
|
||||
pmc 1 "Poll mode command";
|
||||
_ 1 mb1;
|
||||
_ 1 mbz;
|
||||
esmm 1 "Enable special mask mode";
|
||||
smm 1 "Special mask mode";
|
||||
_ 1 mbz;
|
||||
};
|
||||
|
||||
regtype pic_master_trigger "Master Controller Edge/Level Triggered" {
|
||||
_ 3 mbz;
|
||||
irq3_ecl 1 "IRQ3 ECL";
|
||||
irq4_ecl 1 "IRQ4 ECL";
|
||||
irq5_ecl 1 "IRQ5 ECL";
|
||||
irq6_ecl 1 "IRQ6 ECL";
|
||||
irq7_ecl 1 "IRQ7 ECL";
|
||||
};
|
||||
|
||||
regtype pic_slave_trigger "Slave Controller Edge/Level Triggered" {
|
||||
_ 1 mbz;
|
||||
irq9_ecl 1 "IRQ9 ECL";
|
||||
irq10_ecl 1 "IRQ10 ECL";
|
||||
irq11_ecl 1 "IRQ11 ECL";
|
||||
irq12_ecl 1 "IRQ12 ECL";
|
||||
_ 1 mbz;
|
||||
irq14_ecl 1 "IRQ14 ECL";
|
||||
irq15_ecl 1 "IRQ15 ECL";
|
||||
};
|
||||
|
||||
register master_icw1 wo io( base, 0x20 ) "Master PIC Initialization Command Word 1" type(icw1);
|
||||
register master_ocw2 wo also io( base, 0x20 ) "Master PIC Op Ctrl Word 2" type(ocw2);
|
||||
register master_ocw3 wo also io( base, 0x20 ) "Master PIC Op Ctrl Word 3" type(ocw3);
|
||||
register master_ocw3rd ro also io( base, 0x20 ) "Master PIC Op Ctrl Word 3" type(uint8);
|
||||
|
||||
register master_icw2 wo io( base, 0x21 ) "Master PIC Initialization Command Word 2" type(icw2);
|
||||
register master_icw3 wo also io( base, 0x21 ) "Master PIC Initialization Command Word 3" type(pic_master_icw3);
|
||||
register master_icw4 wo also io( base, 0x21 ) "Master PIC Initialization Command Word 4" type(icw4);
|
||||
register master_ocw1 rw also io( base, 0x21 ) "Master PIC Operation Control Word 1" type(uint8);
|
||||
|
||||
register slave_icw1 wo io( base, 0xa0 ) "Slave PIC Initialization Command Word 1" type(icw1);
|
||||
register slave_ocw2 wo also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 2" type(ocw2);
|
||||
register slave_ocw3 wo also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 3" type(ocw3);
|
||||
register slave_ocw3rd ro also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 3" type(uint8);
|
||||
|
||||
register slave_icw2 wo io( base, 0xa1 ) "Slave PIC Initialization Command Word 2" type(icw2);
|
||||
register slave_icw3 wo also io( base, 0xa1 ) "Slave PIC Initialization Command Word 3" type(pic_slave_icw3);
|
||||
register slave_icw4 wo also io( base, 0xa1 ) "Slave PIC Initialization Command Word 4" type(icw4);
|
||||
register slave_ocw1 rw also io( base, 0xa1 ) "Slave PIC Operation Control Word 1" type(uint8);
|
||||
|
||||
register master_trigger rw io( base, 0x4d0 ) "Master PIC Edge/Level Triggered" type(pic_master_trigger);
|
||||
register slave_trigger rw io( base, 0x4d1 ) "Slave PIC Edge/Level Triggered" type(pic_slave_trigger);
|
||||
};
|
||||
114
devices/lpc_rtc.dev
Normal file
114
devices/lpc_rtc.dev
Normal file
@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_rtc.dev
|
||||
*
|
||||
* DESCRIPTION: Legacy real-time clock registers on the LPC (low pin count, or
|
||||
* legacy PC) bridge function of a typical Intel IHC
|
||||
* (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
*
|
||||
*/
|
||||
|
||||
device lpc_rtc (io base) "LPC Real-Time Clock and CMOS RAM" {
|
||||
|
||||
// 21.6
|
||||
register ndx rw io(base, 0x70) "Standard index" type(uint8);
|
||||
register target rw io(base, 0x71) "Standard target" type(uint8);
|
||||
|
||||
register endx rw io(base, 0x72) "Extended index" type(uint8);
|
||||
register etarget rw io(base, 0x73) "Extended target" type(uint8);
|
||||
|
||||
// 21.6.2
|
||||
constants sndx "Standard index values" {
|
||||
seconds = 0x0 "Seconds";
|
||||
al_seconds = 0x1 "Seconds alarm";
|
||||
minutes = 0x2 "Minutes";
|
||||
al_minutes = 0x3 "Minutes Alarm";
|
||||
hours = 0x4 "Hours";
|
||||
al_hours = 0x5 "Hours Alarm";
|
||||
weekday = 0x6 "Day of Week";
|
||||
date = 0x7 "Day of Month";
|
||||
month = 0x8 "Month";
|
||||
year = 0x9 "Year";
|
||||
rega = 0xa "Register A";
|
||||
regb = 0xb "Register B";
|
||||
regc = 0xc "Register C";
|
||||
regd = 0xd "Register D";
|
||||
};
|
||||
|
||||
// 21.6.2.1
|
||||
constants dcs "Division chain select" {
|
||||
normal = 0b010 "Normal operation";
|
||||
divreset = 0b110 "Divider reset";
|
||||
divreset2 = 0b111 "Divider reset";
|
||||
bypass15 = 0b101 "Bypass 15 stages";
|
||||
bypass10 = 0b100 "Bypass 10 stages";
|
||||
bypass5 = 0b011 "Bypass 5 stages";
|
||||
};
|
||||
|
||||
constants rate "Rate select" {
|
||||
never = 0b0000 "Interrupt never toggles";
|
||||
ms3_90625_ = 0b0001 "3.90625 ms (duplicate)";
|
||||
ms7_8125_ = 0b0010 "7.8125 ms (duplicate)";
|
||||
us122_070 = 0b0011 "122.070 us";
|
||||
us244_141 = 0b0100 "244.141 us";
|
||||
us488_281 = 0b0101 "488.281 us";
|
||||
us976_5625 = 0b0110 "976.5625 us";
|
||||
ms1_953125 = 0b0111 "1.953125 ms";
|
||||
ms3_906251 = 0b1000 "3.906251 ms";
|
||||
ms7_8125 = 0b1001 "7.8125 ms";
|
||||
ms15_625 = 0b1010 "15.625 ms";
|
||||
ms31_25 = 0b1011 "31.25 ms";
|
||||
ms62_5 = 0b1100 "62.5 ms";
|
||||
ms125 = 0b1101 "125 ms";
|
||||
ms250 = 0b1110 "250 ms";
|
||||
ms500 = 0b1111 "500 ms";
|
||||
};
|
||||
|
||||
register rega rw also io(base, 0x71) "Register A" {
|
||||
rs 4 type(rate) "Rate select";
|
||||
dv 3 type(dcs) "Divisioin chain select";
|
||||
uip 1 "Update in progress";
|
||||
};
|
||||
|
||||
// 26.6.2.2
|
||||
register regb rw also io(base, 0x71) "General configuration" {
|
||||
dse 1 "Daylight savings enable";
|
||||
hourform 1 "Hour format";
|
||||
dm 1 "Data mode (BCD/binary)";
|
||||
sqwe 1 "Square wave enable";
|
||||
uie 1 "Update-ended interrupt enable";
|
||||
aie 1 "Alarm interrupt enable";
|
||||
pie 1 "Periodic interrupt enable";
|
||||
set 1 "Update cycle inhibit";
|
||||
};
|
||||
|
||||
// 26.6.2.3
|
||||
register regc ro also io(base, 0x71) "Flag register C" {
|
||||
_ 4;
|
||||
uf 1 "Update-ended";
|
||||
af 1 "Alarm";
|
||||
pf 1 "Periodic interrupt";
|
||||
irqf 1 "Interrupt request flag";
|
||||
};
|
||||
|
||||
// 26.6.2.4
|
||||
register regd rw also io(base, 0x71) "Flag register D" {
|
||||
al_date 6 "Date alarm";
|
||||
_ 1;
|
||||
vrt 1 mbz "Valid RAM and time";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
116
devices/lpc_rtc_spaces.dev
Normal file
116
devices/lpc_rtc_spaces.dev
Normal file
@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_rtc.dev
|
||||
*
|
||||
* DESCRIPTION: Legacy real-time clock registers on the LPC (low pin count, or
|
||||
* legacy PC) bridge function of a typical Intel IHC
|
||||
* (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
*
|
||||
*/
|
||||
|
||||
device LPC_rtc (io base) "LPC Real-Time Clock" {
|
||||
|
||||
// 21.6
|
||||
//
|
||||
// We have two register spaces: standard, and extended. They use
|
||||
// different index and target registers.
|
||||
//
|
||||
space std(addr) valuewise "Standard register space";
|
||||
register ndx rw io(base, 0x70) "Standard index" type(uint8);
|
||||
register target rw io(base, 0x71) "Standard target" type(uint8);
|
||||
regarray standard rw std(0x00)[256] type(uint8);
|
||||
|
||||
space ext(addr) valuewise "Extended register space";
|
||||
register endx rw io(base, 0x72) "Extended index" type(uint8);
|
||||
register etarget rw io(base, 0x73) "Extended target" type(uint8);
|
||||
regarray extended rw ext(0x00)[256] type(uint8);
|
||||
|
||||
// 21.6.2
|
||||
register seconds rw also std(0x0) "Seconds" type(uint8);
|
||||
register al_seconds rw also std(0x1) "Seconds alarm" type(uint8);
|
||||
register minutes rw also std(0x2) "Minutes" type(uint8);
|
||||
register al_minutes rw also std(0x3) "Minutes Alarm" type(uint8);
|
||||
register hours rw also std(0x4) "Hours" type(uint8);
|
||||
register al_hours rw also std(0x5) "Hours Alarm" type(uint8);
|
||||
register weekday rw also std(0x6) "Day of Week" type(uint8);
|
||||
register date rw also std(0x7) "Day of Month" type(uint8);
|
||||
register month rw also std(0x8) "Month" type(uint8);
|
||||
register year rw also std(0x9) "Year" type(uint8);
|
||||
|
||||
// 21.6.2.1
|
||||
constants dcs "Division chain select" {
|
||||
normal = 0b010 "Normal operation";
|
||||
divreset = 0b110 "Divider reset";
|
||||
divreset2 = 0b111 "Divider reset";
|
||||
bypass15 = 0b101 "Bypass 15 stages";
|
||||
bypass10 = 0b100 "Bypass 10 stages";
|
||||
bypass5 = 0b011 "Bypass 5 stages";
|
||||
};
|
||||
|
||||
constants rate "Rate select" {
|
||||
never = 0b0000 "Interrupt never toggles";
|
||||
ms3_90625_ = 0b0001 "3.90625 ms (duplicate)";
|
||||
ms7_8125_ = 0b0010 "7.8125 ms (duplicate)";
|
||||
us122_070 = 0b0011 "122.070 us";
|
||||
us244_141 = 0b0100 "244.141 us";
|
||||
us488_281 = 0b0101 "488.281 us";
|
||||
us976_5625 = 0b0110 "976.5625 us";
|
||||
ms1_953125 = 0b0111 "1.953125 ms";
|
||||
ms3_906251 = 0b1000 "3.906251 ms";
|
||||
ms7_8125 = 0b1001 "7.8125 ms";
|
||||
ms15_625 = 0b1010 "15.625 ms";
|
||||
ms31_25 = 0b1011 "31.25 ms";
|
||||
ms62_5 = 0b1100 "62.5 ms";
|
||||
ms125 = 0b1101 "125 ms";
|
||||
ms250 = 0b1110 "250 ms";
|
||||
ms500 = 0b1111 "500 ms";
|
||||
};
|
||||
|
||||
register rega rw also std(0xa) "Register A" {
|
||||
rs 4 type(rate) "Rate select";
|
||||
dv 3 type(dcs) "Divisioin chain select";
|
||||
uip 1 "Update in progress";
|
||||
};
|
||||
|
||||
// 26.6.2.2
|
||||
register regb rw also std(0xb) "General configuration" {
|
||||
dse 1 "Daylight savings enable";
|
||||
hourform 1 "Hour format";
|
||||
dm 1 "Data mode (BCD/binary)";
|
||||
sqwe 1 "Square wave enable";
|
||||
uie 1 "Update-ended interrupt enable";
|
||||
aie 1 "Alarm interrupt enable";
|
||||
pie 1 "Periodic interrupt enable";
|
||||
set 1 "Update cycle inhibit";
|
||||
};
|
||||
|
||||
// 26.6.2.3
|
||||
register regc ro also std(0xc) "Flag register C" {
|
||||
_ 4;
|
||||
uf 1 "Update-ended";
|
||||
af 1 "Alarm";
|
||||
pf 1 "Periodic interrupt";
|
||||
irqf 1 "Interrupt request flag";
|
||||
};
|
||||
|
||||
// 26.6.2.4
|
||||
register regd rw also std(0xd) "Flag register D" {
|
||||
al_date 6 "Date alarm";
|
||||
_ 1;
|
||||
vrt 1 mbz "Valid RAM and time";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
88
devices/lpc_timer.dev
Normal file
88
devices/lpc_timer.dev
Normal file
@ -0,0 +1,88 @@
|
||||
/*
|
||||
* Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpc_timer.dev
|
||||
*
|
||||
* DESCRIPTION: Legacy timer registers on the LPC (low pin count, or
|
||||
* legacy PC) bridge function of a typical Intel IHC
|
||||
* (Southbridge).
|
||||
*
|
||||
* This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
|
||||
* Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)".
|
||||
*/
|
||||
|
||||
device lpc_timer (io base) "LPC Timer" {
|
||||
//
|
||||
// Section 21.3: Timer I/O registers
|
||||
//
|
||||
|
||||
constants cnt_mode "Counter mode" {
|
||||
oseoc = 0b000 "Out signal on end of count (mode 0)";
|
||||
hr1s = 0b001 "Hardware retriggerable one-shot (mode 1)";
|
||||
rtgen = 0b010 "Rate generator (mode 2)";
|
||||
rtgen_ = 0b110 "Rate generator (mode 2)";
|
||||
sqwav = 0b011 "Square wave output (mode 3)";
|
||||
sqwav_ = 0b111 "Square wave output (mode 3)";
|
||||
swstr = 0b100 "Software triggered strobe (mode 4)";
|
||||
hwstr = 0b101 "Hardware triggered strobe (mode 5)";
|
||||
};
|
||||
|
||||
constants timer_rwsel "Read/write select" {
|
||||
clc = 0b00 "Counter latch cmd";
|
||||
lsb = 0b01 "R/w least sig. byte";
|
||||
msb = 0b10 "R/w most sig. byte";
|
||||
lmsb = 0b11 "R/w lsb then msb";
|
||||
};
|
||||
|
||||
constants timer_cntsel "Counter select" {
|
||||
c0 = 0b00 "Counter 0";
|
||||
c1 = 0b01 "Counter 1";
|
||||
c2 = 0b10 "Counter 2";
|
||||
rb = 0b11 "Read back cmd";
|
||||
};
|
||||
|
||||
register tcw wo io( base, 0x3 ) "Timer Control Word" {
|
||||
bcd 1 "Binary coded decimal select";
|
||||
mode 3 type(cnt_mode) "Counter mode";
|
||||
rwsel 2 type(timer_rwsel) "Read/write select";
|
||||
select 2 type(timer_cntsel) "Counter select";
|
||||
};
|
||||
|
||||
register rdbk_cmd wo also io( base, 0x3 ) "Read back command" {
|
||||
_ 1 mbz;
|
||||
c0 1 "Counter 0 select";
|
||||
c1 1 "Counter 1 select";
|
||||
c2 1 "Counter 2 select";
|
||||
stat 1 "Latch status of selected counters";
|
||||
count 1 "Latch count of selected counters";
|
||||
_ 2 mb1;
|
||||
};
|
||||
|
||||
register ltch_cmd wo also io( base, 0x3 ) "Counter latch command" {
|
||||
_ 6 mbz;
|
||||
select 2 type(timer_cntsel) "Counter select";
|
||||
};
|
||||
|
||||
regtype sbyte_fmt "Interval timer status byte format" {
|
||||
bcd 1 "Binary coded decimal select";
|
||||
mode 3 type(cnt_mode) "Counter mode";
|
||||
rwsel 2 type(timer_rwsel) "Read/write select";
|
||||
cnt_stat 1 "Count register status";
|
||||
cnt_out 1 "Counter OUT pin status";
|
||||
};
|
||||
register sbyte_fmt0 ro io( base, 0x0 ) "Int. timer 0 status format" type(sbyte_fmt);
|
||||
|
||||
register sbyte_fmt1 ro io( base, 0x1 ) "Int. timer 1 status format" type(sbyte_fmt);
|
||||
register sbyte_fmt2 ro io( base, 0x2 ) "Int. timer 2 status format" type(sbyte_fmt);
|
||||
|
||||
register cntacc0 rw also io( base, 0x0 ) "Counter 0 access" type(uint8);
|
||||
register cntacc1 rw also io( base, 0x1 ) "Counter 1 access" type(uint8);
|
||||
register cntacc2 rw also io( base, 0x2 ) "Counter 2 access" type(uint8);
|
||||
|
||||
};
|
||||
244
devices/lpuart.dev
Normal file
244
devices/lpuart.dev
Normal file
@ -0,0 +1,244 @@
|
||||
/*
|
||||
* Copyright (c) 2009, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* lpuart.dev
|
||||
*
|
||||
* DESCRIPTION: Low Power UART
|
||||
*
|
||||
* This is derived from:
|
||||
*
|
||||
* i.MX 8DualXPlus Appliacations Processor Reference Manual, revision D, NXP
|
||||
* Pages 2255 - 2298
|
||||
* (IMX8DQXPRM.pdf)
|
||||
*
|
||||
*/
|
||||
|
||||
device lpuart msbfirst (addr base) "LPUART" {
|
||||
|
||||
constants feature "feature set number" {
|
||||
standard = 0b01 "Standard feature set";
|
||||
irda = 0b11 "Standard feature set with MODEM/IrDA support";
|
||||
};
|
||||
|
||||
constants trgsel "trigger select" {
|
||||
disabled = 0b00 "Input trigger is disabled.";
|
||||
rx = 0b01 "Input trigger is used instead of RX pin input.";
|
||||
ctsb = 0b10 "Input trigger is used instead of CTS_B pin input.`";
|
||||
modrx = 0b11 "Input trigger is used to modulate TX pin output.";
|
||||
};
|
||||
|
||||
constants osr "oversampling ratio" {
|
||||
default = 0b00000 "Writing 0 to this field will result in an oversampling ratio of 16.";
|
||||
ratio4 = 0b00011 "Oversampling ratio of 4, requires BOTHEDGE to be set.";
|
||||
ratio5 = 0b00100 "Oversampling ratio of 5, requires BOTHEDGE to be set.";
|
||||
ratio6 = 0b00101 "Oversampling ratio of 6, requires BOTHEDGE to be set.";
|
||||
ratio7 = 0b00110 "Oversampling ratio of 7, requires BOTHEDGE to be set.";
|
||||
ratio8 = 0b00111 "Oversampling ratio of 8.";
|
||||
ratio9 = 0b01000 "Oversampling ratio of 9.";
|
||||
ratio10 = 0b01001 "Oversampling ratio of 10.";
|
||||
ratio11 = 0b01010 "Oversampling ratio of 11.";
|
||||
ratio12 = 0b01011 "Oversampling ratio of 12.";
|
||||
ratio13 = 0b01100 "Oversampling ratio of 13.";
|
||||
ratio14 = 0b01101 "Oversampling ratio of 14.";
|
||||
ratio15 = 0b01110 "Oversampling ratio of 15.";
|
||||
ratio16 = 0b01111 "Oversampling ratio of 16.";
|
||||
ratio17 = 0b10000 "Oversampling ratio of 17.";
|
||||
ratio18 = 0b10001 "Oversampling ratio of 18.";
|
||||
ratio19 = 0b10010 "Oversampling ratio of 19.";
|
||||
ratio20 = 0b10011 "Oversampling ratio of 20.";
|
||||
ratio21 = 0b10100 "Oversampling ratio of 21.";
|
||||
ratio22 = 0b10101 "Oversampling ratio of 22.";
|
||||
ratio23 = 0b10110 "Oversampling ratio of 23.";
|
||||
ratio24 = 0b10111 "Oversampling ratio of 24.";
|
||||
ratio25 = 0b11000 "Oversampling ratio of 25.";
|
||||
ratio26 = 0b11001 "Oversampling ratio of 26.";
|
||||
ratio27 = 0b11010 "Oversampling ratio of 27.";
|
||||
ratio28 = 0b11011 "Oversampling ratio of 28.";
|
||||
ratio29 = 0b11100 "Oversampling ratio of 29.";
|
||||
ratio30 = 0b11101 "Oversampling ratio of 30.";
|
||||
ratio31 = 0b11110 "Oversampling ratio of 31.";
|
||||
ratio32 = 0b11111 "Oversampling ratio of 32.";
|
||||
};
|
||||
|
||||
register verid ro addr(base, 0x0) "Version ID Register" {
|
||||
major 8 "Major Version Number";
|
||||
minor 8 "Minor Version Number";
|
||||
feature 16 type(feature) "Feature Identification Number";
|
||||
};
|
||||
|
||||
register param ro addr(base, 0x4) "Parameter Register" {
|
||||
_ 16;
|
||||
rxfifo 8 "Receive FIFO size (2^RXFIFO)";
|
||||
txfifo 8 "Transmit FIFO size (2^FIFO)";
|
||||
};
|
||||
|
||||
register global ro addr(base, 0x8) "LPUART Global Register" {
|
||||
_ 30;
|
||||
rst 1 rw "Software Reset";
|
||||
_ 1;
|
||||
};
|
||||
|
||||
register pincfg addr(base, 0xc) "LPUART Pin Configuration Register" {
|
||||
_ 30;
|
||||
trgsel 2 rw type(trgsel) "Trigger select";
|
||||
};
|
||||
|
||||
register baud addr(base, 0x10) "LPUART Baud Rate Register" {
|
||||
maen1 1 "Match address mode enable 1";
|
||||
maen2 1 "Match address mode enable 2";
|
||||
m10 1 "10-bit mode select";
|
||||
osr 5 type(osr) "Oversampling ratio";
|
||||
tdmae 1 "Transmitter DMA Enable";
|
||||
_ 1;
|
||||
rdmae 1 "Receiver Full DMA Enable";
|
||||
ridmae 1 "Receiver idle DMA Enable";
|
||||
matcfg 2 "Match Configuration";
|
||||
bothedge 1 "Both Edge Sampling";
|
||||
resynccdis 1 "Resynchronization Disable";
|
||||
lbkdie 1 "LIN Break Detect Interrupt Enable";
|
||||
rxedgie 1 "RX Input Active Edge Interrupt Enable";
|
||||
sbns 1 "Stop Bit Number Select";
|
||||
sbr 13 "Baud Rate Modulo Divisor";
|
||||
};
|
||||
|
||||
register stat addr(base, 0x14) "LPUART Status Register" {
|
||||
lbkdif 1 rw1c "LIN Break Detect Interrupt flag";
|
||||
rxedgif 1 rw1c "RX Pin Active Edge Interrupt Flag";
|
||||
msbf 1 "MSB first";
|
||||
rxinv 1 "Receive Data Inversion";
|
||||
rwuid 1 "Whether idle char sets IDLE bit.";
|
||||
brk13 1 "Break Character Generation Length";
|
||||
lbkde 1 "LIN Break Detection Enable";
|
||||
raf 1 ro "Receiver Active Flag";
|
||||
tdre 1 ro "Transmit Data Register Empty Flag";
|
||||
tc 1 ro "Transmit Complete Flag";
|
||||
rdrf 1 ro "Receive Data Register Full Flag";
|
||||
idle 1 rw1c "Idle Line Flag";
|
||||
or 1 rw1c "Receiver Overrun Flag";
|
||||
nf 1 rw1c "Noise Flag";
|
||||
fe 1 rw1c "Framing Error Flag";
|
||||
pf 1 rw1c "Parity Error Flag";
|
||||
ma1f 1 rw1c "Match 1 Flag";
|
||||
ma2f 1 rw1c "Match 2 Flag";
|
||||
_ 14;
|
||||
};
|
||||
|
||||
register ctrl addr(base, 0x18) "LPUART Control Register" {
|
||||
r8t9 1 "Receive Bit 8 / Transmit Bit 9";
|
||||
r9t8 1 "Receive Bit 9 / Transmit Bit 8";
|
||||
txdir 1 "TX Pin Direction Single-Wire Mode";
|
||||
txinv 1 "Transmit Data Inversion";
|
||||
orie 1 "Overrrun Interrupt Enable";
|
||||
neie 1 "Noise Error Interrupt Enable";
|
||||
feie 1 "Framing Error Interrupt Enable";
|
||||
peie 1 "Parity Error Interrupt Enable";
|
||||
tie 1 "Transmit Interrupt Enable";
|
||||
tcie 1 "Transmission Complete Interrupt Enable";
|
||||
rie 1 "Receiver Interrupt Enable";
|
||||
iue 1 "Idle Line Interrupt Enable";
|
||||
te 1 "Transmitter Enable";
|
||||
re 1 "Receiver Enable";
|
||||
rwu 1 "Receiver Wakeup Control";
|
||||
sbk 1 "Send Break";
|
||||
ma1ie 1 "Match 1 Interrupt Enable";
|
||||
ma2ie 1 "Match 2 Interrupt Enable";
|
||||
_ 2;
|
||||
m7 1 "7-Bit Mode Select";
|
||||
idlecfg 3 "Idle Configuration (2^IDLECFG idle characters before IDLE flag set)";
|
||||
loops 1 "Loop Mode Select";
|
||||
dozeen 1 "Doze Enable";
|
||||
rsrc 1 "Receiver Source Select";
|
||||
m 1 "9-Bit or 8-Bit Mode Select";
|
||||
wake 1 "Receiver Wakeup Method Select";
|
||||
ilt 1 "Idle Line Type Select";
|
||||
pe 1 "Parity Enable";
|
||||
pt 1 "Parity Type";
|
||||
};
|
||||
|
||||
/*
|
||||
* Data register is actually two registers for RX/TX
|
||||
* To prevent Mackerel from generating code for reading
|
||||
* things via the TX register and therefore clearing the RX
|
||||
* register we declare the readonly fields as mbz in the TX
|
||||
* register.
|
||||
*/
|
||||
register rxdata ro addr(base, 0x1c) "LPUART Receive Data Register" {
|
||||
_ 16;
|
||||
noisy 1 "Whether received with noise.";
|
||||
paritye 1 "Whether received with parity error.";
|
||||
fre 1 "Whether received with frame error";
|
||||
rxempt 1 "Receive Buffer Empty";
|
||||
idline 1 "Idle Line";
|
||||
_ 1;
|
||||
buf 10 "Data buffer";
|
||||
};
|
||||
|
||||
register txdata wo also addr(base, 0x1c) "LPUART Transmit Data Register" {
|
||||
_ 16 mbz;
|
||||
_ 1 mbz;
|
||||
_ 1 mbz;
|
||||
tsc 1 "Transmit Special Character";
|
||||
_ 1 mbz;
|
||||
_ 1 mbz;
|
||||
_ 1 mbz;
|
||||
buf 10 "Data buffer";
|
||||
};
|
||||
|
||||
register match addr(base, 0x20) "LPUART Match Address Register" {
|
||||
_ 6;
|
||||
ma2 10 "Match Address 2";
|
||||
_ 6;
|
||||
ma1 10 "Match Address 1";
|
||||
};
|
||||
|
||||
register modir addr(base, 0x24) "LPUART Modem IrDA Register" {
|
||||
_ 13;
|
||||
iren 1 "Infrared enable";
|
||||
tnp 2 "Transmitter narrow pulse";
|
||||
_ 2;
|
||||
rtswater 6 "Receive RTS Configuration";
|
||||
_ 2;
|
||||
txctssrc 1 "Transmit CTS Source";
|
||||
txctsc 1 "Transmit CTS Configuration";
|
||||
rxrtse 1 "Receiver request-to-send enable";
|
||||
txrtspol 1 "Transmitter request-to-send polarity";
|
||||
txrtse 1 "Transmitter request-to-send enable";
|
||||
txctse 1 "Transmitter clear-to-send enable";
|
||||
};
|
||||
|
||||
register fifo addr(base, 0x28) "LPUART FIFO Register" {
|
||||
_ 8;
|
||||
txempt 1 ro "Transmit Buffer/FIFO Empty";
|
||||
rxempt 1 ro "Receive Buffer/FIFO Empty";
|
||||
_ 4;
|
||||
txof 1 rw1c "Trasnmitter Buffer Overflow Flag";
|
||||
rxuf 1 rw1c "Receiver Buffer Underflow Flag";
|
||||
txflush 1 wo "Transmit FIFO/Buffer Flush";
|
||||
rxflush 1 wo "Receive FIFO/Buffer Flush";
|
||||
_ 1;
|
||||
rxiden 3 "Receiver Idle Empty Enable";
|
||||
txofe 1 "Transmit FIFO Overflow Interrupt Enable";
|
||||
rxufe 1 "Receive FIFO Underflow Interrupt Enable";
|
||||
txfe 1 "Transmit FIFO Enable";
|
||||
txfifosize 3 ro "Transmit FIFO Buffer Depth";
|
||||
rxfe 1 "Receive FIFO Enable";
|
||||
rxfifosize 3 ro "Receive FIFO Buffer Depth";
|
||||
};
|
||||
|
||||
register water addr(base, 0x2c) "LPUART Watemark Register" {
|
||||
_ 1;
|
||||
rxcount 7 ro "Receive Counter";
|
||||
_ 2;
|
||||
rxwater 6 "Receiver Watermark";
|
||||
_ 1;
|
||||
txcount 7 ro "Transmit Counter";
|
||||
_ 2;
|
||||
txwater 6 "Transmit Watermark";
|
||||
};
|
||||
};
|
||||
66
devices/megaraid.dev
Normal file
66
devices/megaraid.dev
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2014, University of Washington. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* megaraid.dev
|
||||
*
|
||||
* DESCRIPTION: LSI MegaRAID Controller
|
||||
*
|
||||
* From the FreeBSD driver.
|
||||
*/
|
||||
|
||||
device megaraid msbfirst ( addr base ) "LSI MegaRAID Controller" {
|
||||
register doorbell rw addr(base, 0x0) "Doorbell" type(uint32);
|
||||
register fusion_seq_offset rw addr(base, 0x4) "Fusion SEQ Offset" type (uint32);
|
||||
register fusion_host_diag rw addr(base, 0x8) "Fusion Host Diag" type (uint32);
|
||||
|
||||
register inbound_msg_0 rw addr(base, 0x10) "Inbound msg 0" type (uint32);
|
||||
register inbound_msg_1 rw addr(base, 0x14) "Inbound msg 0" type (uint32);
|
||||
register outbound_msg_0 rw addr(base, 0x18) "Outbound msg 0" type (uint32);
|
||||
register outbound_msg_1 rw addr(base, 0x1c) "Outbound msg 1" type (uint32);
|
||||
|
||||
register inbound_doorbell rw addr(base, 0x20) "Inbound doorbell" type (uint32);
|
||||
register inbound_intr_status rw addr(base, 0x24) "Inbound interrupt status" type (uint32);
|
||||
register inbound_intr_mask rw addr(base, 0x28) "Inbound interrupt mask" type (uint32);
|
||||
register outbound_doorbell rw addr(base, 0x2c) "Outbound doorbell" type (uint32);
|
||||
register outbound_intr_status rw addr(base, 0x30) "Outbound interrupt status" type (uint32);
|
||||
register outbound_intr_mask rw addr(base, 0x34) "Outbound interrupt mask" type (uint32);
|
||||
|
||||
register inbound_queue_port rw addr(base, 0x40) "Inbound queue port" type (uint32);
|
||||
register outbound_queue_port rw addr(base, 0x44) "Outbound queue port" type (uint32);
|
||||
|
||||
register reply_post_host_index rw addr(base, 0x6c) "Reply post host index" type (uint32);
|
||||
|
||||
register outbound_doorbell_clear rw addr(base, 0xa0) "Outbound doorbell clear" type (uint32);
|
||||
|
||||
constants state "Controller state" {
|
||||
state_undefined = 0x0 "Undefined";
|
||||
state_bb_init = 0x1 "BB Init";
|
||||
state_fw_init = 0x4 "FW Init";
|
||||
state_wait_handshake = 0x6 "Wait handshake";
|
||||
state_fw_init_2 = 0x7 "FW Init 2";
|
||||
state_device_scane = 0x8 "Device scan";
|
||||
state_boot_msg_pending = 0x9 "Boot message pending";
|
||||
state_flush_cache = 0xa "Flush cache";
|
||||
state_ready = 0xb "Ready";
|
||||
state_operational = 0xc "Operational";
|
||||
state_fault = 0xf "Fault";
|
||||
};
|
||||
|
||||
register status ro addr(base, 0xb0) "Device status" {
|
||||
state 4 type(state) "Controller status";
|
||||
_ 4;
|
||||
sge 8;
|
||||
max_cmds 16 "Max. # of commands";
|
||||
};
|
||||
|
||||
register outbound_scratch_pad_2 rw addr(base, 0xb4) "Outbound scratch pad #2" type (uint32);
|
||||
|
||||
register inbound_low_queue_port rw addr(base, 0xc0) "Inbound low queue port" type (uint32);
|
||||
register inbound_high_queue_port rw addr(base, 0xc4) "Inbound high queue port" type (uint32);
|
||||
};
|
||||
21
devices/msix.dev
Normal file
21
devices/msix.dev
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2016, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* msix.dev
|
||||
*
|
||||
* DESCRIPTION: MSIx Table specification
|
||||
*
|
||||
* According to PCI Spec V3, section, 6.8.2
|
||||
*/
|
||||
device msix lsbfirst ( addr base ) "MSIx Table Structure" {
|
||||
regarray vec_control addr(base, 0x0)[2048;0x10] "Vector Control" type(uint32);
|
||||
regarray msg_data addr(base, 0x4)[2048;0x10] "Msg Data" type(uint32);
|
||||
regarray msg_addr addr(base, 0x8)[2048;0x10] "Msg Addr" type(uint64);
|
||||
};
|
||||
|
||||
17
devices/msix_e1000.dev
Normal file
17
devices/msix_e1000.dev
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2016, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* msix_e1000.dev
|
||||
* According to Intel 82574 gigabit ethernet card
|
||||
*/
|
||||
device msix_e1000 lsbfirst ( addr base ) "E1000 MSIx Table Structure" {
|
||||
regarray msg_addr addr(base, 0x0)[4;0x10] "Address" type(uint64);
|
||||
regarray msg_data addr(base, 0x8)[4;0x10] "Message" type(uint32);
|
||||
regarray vec_control addr(base, 0xC)[4;0x10] "Vector Control" type(uint32);
|
||||
};
|
||||
340
devices/ohci.dev
Normal file
340
devices/ohci.dev
Normal file
@ -0,0 +1,340 @@
|
||||
/*
|
||||
* Copyright (c) 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaestr. 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ohci.dev
|
||||
*
|
||||
* DESCRIPTION: Open Host Controller Interface (OHCI) description
|
||||
*
|
||||
* Archaic USB interface, but still found on e.g. ATI and NVidia
|
||||
* chipsets.
|
||||
*
|
||||
* Numbers in comments refer to the OpenHCI Open Host Controller
|
||||
* Interface Specification for USB, by Compaq, Microsoft, and National
|
||||
* Semiconductor, 09/14/99 2:33 PM, Release: 1.0a
|
||||
*/
|
||||
|
||||
|
||||
device ohci lsbfirst ( io base ) "OHCI USB controller" {
|
||||
|
||||
/*
|
||||
//
|
||||
// Data structures
|
||||
//
|
||||
|
||||
// 4.2.1
|
||||
constants direction width(2) "Data flow direction" {
|
||||
dir_td = 0b00 "Get direction from TD";
|
||||
dir_out = 0b01 "Out";
|
||||
dir_in = 0b10 "In";
|
||||
dir_td1 = 0b11 "Get direction from TD (alt)";
|
||||
};
|
||||
|
||||
datatype epdesc lsbfirst(32) "Endpoint descriptor" {
|
||||
fa 7 "Function address";
|
||||
en 4 "Endpoint number";
|
||||
d 2 type(direction) "Direction";
|
||||
s 1 "Speed (1=low, 0=full)";
|
||||
k 1 "Skip";
|
||||
f 1 "Format (1=isochronous, 0=general)";
|
||||
mps 11 "Maximum packet size";
|
||||
_ 5;
|
||||
_ 4;
|
||||
tailp 28 "TD queue tail pointer";
|
||||
h 1 "Halted";
|
||||
c 1 "Toggle carry";
|
||||
_ 2 mbz;
|
||||
headp 28 "TD queue head pointer";
|
||||
_ 4;
|
||||
nexted 28 "Next endpoint descriptor";
|
||||
};
|
||||
|
||||
// 4.3.1
|
||||
constants pid width(2) "Direction / PID for token" {
|
||||
pid_setup = 0b00 "Setup (to endpoint)";
|
||||
pid_out = 0b01 "To endpoint";
|
||||
pid_in = 0b10 "From endpoint";
|
||||
};
|
||||
datatype gentd lsbfirst(32) "General transfer descriptor" {
|
||||
_ 18;
|
||||
r 1 "Buffer rounding";
|
||||
dp 2 type(pid) "Direction or PID";
|
||||
di 3 "Delay interrupt frames";
|
||||
t 2 "Data toggle";
|
||||
ec 2 "Error count";
|
||||
cc 4 type(ccode) "Condition code for last attempted transaction";
|
||||
cbp 32 "Current buffer pointer";
|
||||
_ 4 mbz;
|
||||
nexttd 28 "Next transfer descriptor";
|
||||
be 32 "Buffer end";
|
||||
};
|
||||
|
||||
|
||||
// 4.3.2
|
||||
datatype isotd lsbfirst(32) "Isochronous transfer descriptor" {
|
||||
sf 16 "Starting frame";
|
||||
_ 5;
|
||||
di 3 "Delay interrupt frames";
|
||||
fc 3 "Frame count";
|
||||
_ 1;
|
||||
cc 4 type(ccode) "Condition code for last attempted transaction";
|
||||
_ 12;
|
||||
bp0 20 "Buffer page 0";
|
||||
_ 5 mbz;
|
||||
nexttd 27 "Next transfer descriptor";
|
||||
be 32 "Buffer end";
|
||||
ofpsw0 16 "Offset / packet status word 0";
|
||||
ofpsw1 16 "Offset / packet status word 1";
|
||||
ofpsw2 16 "Offset / packet status word 2";
|
||||
ofpsw3 16 "Offset / packet status word 4";
|
||||
ofpsw4 16 "Offset / packet status word 3";
|
||||
ofpsw5 16 "Offset / packet status word 5";
|
||||
ofpsw6 16 "Offset / packet status word 6";
|
||||
ofpsw7 16 "Offset / packet status word 7";
|
||||
};
|
||||
datatype psw lsbfirst(16) "Packet status word" {
|
||||
size 11 "Size of packet";
|
||||
_ 1 mbz;
|
||||
cc 4 type(ccode) "Condition code";
|
||||
};
|
||||
|
||||
/// 4.3.3
|
||||
constants ccode width(4) "Completion codes" {
|
||||
cc_ne = 0b0000 "No error";
|
||||
cc_crc = 0b0001 "CRC error";
|
||||
cc_bs = 0b0010 "Bitstuffing violation";
|
||||
cc_dtm = 0b0011 "Data toggle PID mismatch";
|
||||
cc_stl = 0b0100 "EP returned stall PID";
|
||||
cc_dnr = 0b0101 "Device not responding";
|
||||
cc_pcf = 0b0110 "PID check failure";
|
||||
cc_uxp = 0b0111 "Unexpected PID";
|
||||
cc_dor = 0b1000 "Data overrun";
|
||||
cc_dur = 0b1001 "Data underrun";
|
||||
cc_bor = 0b1100 "Buffer overrun";
|
||||
cc_bur = 0b1101 "Buffer underrun";
|
||||
cc_nac = 0b1110 "Not accessed";
|
||||
cc_nac_ = 0b1111 "Not accessed (alternate)";
|
||||
};
|
||||
*/
|
||||
//
|
||||
// Registers
|
||||
//
|
||||
// 7.1 Control and status partition
|
||||
//
|
||||
|
||||
// 7.1.1 Interface revision
|
||||
/// Initially 0x10.
|
||||
register revision ro io(base, 0x00) "Revision" {
|
||||
rev 8 "BCD rep. of interface version";
|
||||
_ 24;
|
||||
};
|
||||
|
||||
// 7.1.2 Control register
|
||||
constants state "Functional state" {
|
||||
st_reset = 0b00 "Reset (after h/w reset)";
|
||||
st_resume = 0b01 "Resume from downstream port";
|
||||
st_operational = 0b10 "Operational (running)";
|
||||
st_suspend = 0b11 "Suspend (after s/w reset)";
|
||||
};
|
||||
// Initially 0x00
|
||||
register control rw io(base, 0x04) "Control" {
|
||||
cbsr 2 "Control/bulk service ratio";
|
||||
pe 1 "Periodic list enable";
|
||||
ie 1 "Isochronous enable";
|
||||
cle 1 "Control list enable";
|
||||
ble 1 "Bulk list enable";
|
||||
hcfs 2 type(state) "Host controller functional state";
|
||||
ir 1 "Interrupt routing";
|
||||
rwc 1 "Remote wakeup connected";
|
||||
rwe 1 "Remote wakeup enabled";
|
||||
_ 21;
|
||||
};
|
||||
|
||||
|
||||
// 7.1.3 Command and Status
|
||||
// Initially 0x00
|
||||
register cmdstatus rw io(base, 0x08) "08 CommandStatus" {
|
||||
hcr 1 "Host controller reset";
|
||||
clf 1 "Control list filled";
|
||||
blf 1 "Bulk list filled";
|
||||
ocr 1 "Ownership change request";
|
||||
_ 12;
|
||||
soc 2 ro "Scheduling overrun count";
|
||||
_ 14;
|
||||
};
|
||||
|
||||
// 7.1.4-6: Interrupt registers
|
||||
regtype interrupt "Interrupts" {
|
||||
so 1 "Scheduling overrun";
|
||||
wdh 1 "Writeback done head";
|
||||
sf 1 "Start of frame";
|
||||
rd 1 "Resume detected";
|
||||
ue 1 "Unrecoverable error";
|
||||
fno 1 "Frame number overflow";
|
||||
rhsc 1 "Root hub status change";
|
||||
_ 23;
|
||||
oc 1 "Ownership change";
|
||||
mie 1 "Master interrupt enable";
|
||||
};
|
||||
register intstatus rw io(base, 0x0C) "Interrupt status"
|
||||
type(interrupt);
|
||||
register intenable rw io(base, 0x10) "Interrupt enable"
|
||||
type(interrupt);
|
||||
register intdisable rw io(base, 0x14) "Interrupt disable"
|
||||
type(interrupt);
|
||||
|
||||
//
|
||||
// 7.2 Memory pointer partition
|
||||
//
|
||||
|
||||
// 7.2.1
|
||||
register hcca rw io(base, 0x18) "Host controller communication area" {
|
||||
_ 8 mbz;
|
||||
hcca 24 "Physical address";
|
||||
};
|
||||
|
||||
regtype physptr "Physical address pointer" {
|
||||
_ 4 mbz;
|
||||
addr 28 "Address";
|
||||
};
|
||||
|
||||
// 7.2.2.
|
||||
register period_cur ro io(base, 0x1C) "Cur. isochronous or int. ED"
|
||||
type(physptr);
|
||||
|
||||
// 7.2.3
|
||||
register ctrl_head rw io(base, 0x20) "First ED of control list"
|
||||
type(physptr);
|
||||
|
||||
|
||||
// 7.2.4
|
||||
register ctrl_cur rw io(base, 0x24) "Current ED of control list"
|
||||
type(physptr);
|
||||
|
||||
// 7.2.5
|
||||
register bulk_head rw io(base, 0x28) "First ED of bulk list"
|
||||
type(physptr);
|
||||
|
||||
// 7.2.6
|
||||
register bulk_cur rw io(base, 0x2C) "Current ED of bulk list"
|
||||
type(physptr);
|
||||
|
||||
|
||||
// 7.2.7
|
||||
register done_head ro io(base, 0x30) "Done head pointer"
|
||||
type(physptr);
|
||||
|
||||
//
|
||||
// 7.3 Frame counter partition
|
||||
//
|
||||
|
||||
// 7.3.1
|
||||
register fm_interval rw io(base, 0x34) "Frame interval" {
|
||||
fi 14 "Frame interval (dflt 0x2edf)";
|
||||
_ 2;
|
||||
fsmps 15 "FS largest data packet";
|
||||
fit 1 "Frame interval toggle";
|
||||
};
|
||||
|
||||
// 7.3.2
|
||||
register fm_remain ro io(base, 0x38) "Frame remaining" {
|
||||
fr 14 "Bit time remaining in current frame";
|
||||
_ 17;
|
||||
frt 1 "Frame remaining toggle";
|
||||
};
|
||||
|
||||
// 7.3.3
|
||||
register fm_num ro io(base, 0x3C) "Frame number" {
|
||||
fn 16 "Frame number (16-bit counter)";
|
||||
_ 16;
|
||||
};
|
||||
|
||||
// 7.3.4
|
||||
register period_start rw io(base, 0x40) "Period start" {
|
||||
ps 14 "Start time for processing periodic list";
|
||||
_ 18;
|
||||
};
|
||||
|
||||
// 7.3.5
|
||||
register hclsthreshold rw io(base, 0x44) "LS threshold" {
|
||||
lst 11 "Low-speed threshold (should be 0x0628)";
|
||||
_ 21;
|
||||
};
|
||||
|
||||
//
|
||||
// 7.4 Root Hub partition
|
||||
//
|
||||
|
||||
// 7.4.1
|
||||
register rh_descra rw io(base, 0x48) "Root hub descriptor a" {
|
||||
ndp 8 ro "Number of downstream ports";
|
||||
psm 1 "Power switching mode";
|
||||
nps 1 "No power switching";
|
||||
dt 1 ro "Device type";
|
||||
ocpm 1 "Overcurrent protection mode";
|
||||
nocp 1 "No overcurrent protection";
|
||||
_ 11;
|
||||
potpgt 8 "Power-on to power-good time (* 2ms)";
|
||||
};
|
||||
|
||||
// 7.4.2
|
||||
register rh_descrb rw io(base, 0x4C) "Root hub descriptor b" {
|
||||
dr 16 "Device removal";
|
||||
ppcm 16 "Port power control mask";
|
||||
};
|
||||
|
||||
// 7.4.3
|
||||
register rh_status rw io(base, 0x50) "Root hub status" {
|
||||
lps 1 wo "Clear global power";
|
||||
oci 1 ro "Overcurrent indicator";
|
||||
_ 13;
|
||||
drwe 1 rw1c "Device remote wakeup enable";
|
||||
lpsc 1 wo "Set globl power";
|
||||
ocic 1 rw1c "Overcurrent indicator change";
|
||||
_ 13;
|
||||
crwe 1 wo "Clear remote wakeup enable";
|
||||
};
|
||||
|
||||
// 7.4.4
|
||||
// Assume 256 ports at this stage; it's actually given by
|
||||
// rh_descra->ndp.
|
||||
regarray rh_portstat ro io(base, 0x54)[256] "Root hub port status" {
|
||||
ccs 1 "Current connection status";
|
||||
pes 1 "Port enable status";
|
||||
pss 1 "Port suspend status";
|
||||
poci 1 "Port overcurrent indicator";
|
||||
prs 1 "Port reset status";
|
||||
_ 3;
|
||||
pps 1 "Port power status";
|
||||
lsda 1 "Low-speed device attached";
|
||||
_ 6;
|
||||
csc 1 "Connect status change";
|
||||
pesc 1 "Port enable status change";
|
||||
pssc 1 "Port suspend status change";
|
||||
ocic 1 "Port overcurrent indicator change";
|
||||
prsc 1 "Port reset status change";
|
||||
_ 11;
|
||||
};
|
||||
regarray rh_portctrl wo also io(base, 0x54)[256] "Root hub port control" {
|
||||
cpe 1 "Clear port enable";
|
||||
spe 1 "Set port enable";
|
||||
sps 1 "Set port suspend";
|
||||
css 1 "Clear suspend status";
|
||||
spr 1 "Set port reset";
|
||||
_ 3;
|
||||
spp 1 "Set port power";
|
||||
cpp 1 "Clear port power";
|
||||
_ 6;
|
||||
csc 1 "Clear connect status change";
|
||||
pesc 1 "Clear port enable status change";
|
||||
pssc 1 "Clear port suspend status change";
|
||||
ocic 1 "Clear port overcurrent indicator change";
|
||||
prsc 1 "Clear port reset status change";
|
||||
_ 11;
|
||||
};
|
||||
};
|
||||
469
devices/omap/ehci.dev
Normal file
469
devices/omap/ehci.dev
Normal file
@ -0,0 +1,469 @@
|
||||
/*
|
||||
* Copyright (c) 2009, 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ehci.dev
|
||||
*
|
||||
* DESCRIPTION: Enhanced Host Controller Interface description
|
||||
*
|
||||
* Numbers in comments refer to the Intel Enhanced Host Controller
|
||||
* Interface Specification for Universal Serial Bus, March 12, 2002,
|
||||
* Revision: 1.0
|
||||
*/
|
||||
|
||||
device ehci msbfirst (addr cap, addr op) "EHCI USB Controller" {
|
||||
|
||||
/*
|
||||
* Section 2.2
|
||||
* Host controller capabilty registers
|
||||
*/
|
||||
|
||||
// 2.2.1
|
||||
// The correct value for 'op' is actually 'cap' plus this number.
|
||||
register caplength ro addr(cap, 0x00) "Capability Registers Length"
|
||||
type(uint8);
|
||||
|
||||
// 2.2.2
|
||||
register hciversion ro addr(cap, 0x02) "Host Controller Interface Version Number"
|
||||
type(uint16);
|
||||
|
||||
// 2.2.3
|
||||
register hcsparams ro addr(cap, 0x04) "Structural parameters" {
|
||||
_ 8;
|
||||
dpn 4 "Debug port number";
|
||||
_ 3;
|
||||
p_indicator 1 "Port indicator";
|
||||
n_cc 4 "Number of campanion controller";
|
||||
n_pcc 4 "Number of ports per companion controller";
|
||||
prr 1 "Port routing rules";
|
||||
_ 2;
|
||||
ppc 1 "Port power control";
|
||||
n_ports 4 "Num. physical downstream ports on this controller";
|
||||
};
|
||||
|
||||
// 2.2.4
|
||||
register hccparams ro addr(cap, 0x08) "Capability parameters" {
|
||||
_ 16;
|
||||
eecp 8 "EHCI extended capabilities pointer";
|
||||
ist 4 "Isochronous scheduling threshold";
|
||||
_ 1;
|
||||
aspc 1 "Asynchronous sechedule park capability";
|
||||
pflf 1 "Programmable frame list flag";
|
||||
bit64ac 1 "Extended 64 bit addressing capability";
|
||||
};
|
||||
|
||||
// section 2.2.5 Companion port route descriptor
|
||||
register hcspportroute ro addr(cap, 0x0C) "Companion port route descr." {
|
||||
attr 60 "Port array";
|
||||
_ 4;
|
||||
};
|
||||
|
||||
/*
|
||||
* Section 2.3
|
||||
* Host controller operational registers
|
||||
*/
|
||||
|
||||
constants itc_val "Interrupt threshold control" {
|
||||
itc_val_rsvd = 0x00 "Reserved";
|
||||
uframe_1 = 0x01 "1 Micro frame";
|
||||
uframes_2 = 0x02 "2 Micro frames";
|
||||
uframes_4 = 0x04 "4 Micro frames";
|
||||
uframes_8 = 0x08 "8 Micro frames (default, equates to 1 ms)";
|
||||
uframes_16 = 0x10 "16 Micro frames (2 ms)";
|
||||
uframes_32 = 0x20 "32 Micro frames (4 ms)";
|
||||
uframes_64 = 0x40 "64 Micro frames (8 ms)";
|
||||
};
|
||||
|
||||
constants frame_val "Frame list size" {
|
||||
elem_1024 = 0b00 "1024 Elements (4096 bytes, default)";
|
||||
elem_512 = 0b01 "512 Elements (2048 bytes)";
|
||||
elem_256 = 0b10 "256 Elements (1024 bytes)";
|
||||
frame_rsvd = 0b11 "Reserved";
|
||||
};
|
||||
|
||||
// 2.3.1
|
||||
register usbcmd rw addr(op, 0x00) "USB command" {
|
||||
_ 8 mbz;
|
||||
itc 8 type(itc_val) "Interrupt threshold control";
|
||||
_ 4 mbz;
|
||||
aspme 1 rw "Asynchronous schedule park mode enable";
|
||||
_ 1 mbz;
|
||||
aspmc 2 rw "Asynchronous schedule park mode count";
|
||||
lhcr 1 rw "Light host controller reset";
|
||||
iaad 1 rw "Interrupt on async advance doorbell";
|
||||
ase 1 rw "Asynchronous schedule enable";
|
||||
pse 1 rw "Periodic schedule enable";
|
||||
fls 2 type(frame_val) "Frame list size";
|
||||
hcr 1 rw "Host controller reset";
|
||||
rs 1 rw "Run stop for scheduling";
|
||||
};
|
||||
|
||||
// 2.3.2
|
||||
register usbsts rw addr(op, 0x04) "USB status" {
|
||||
_ 16 mbz;
|
||||
ass 1 ro "Asynchronous schedule status";
|
||||
pss 1 ro "Periodic schedule status";
|
||||
rec 1 ro "Reclamation";
|
||||
hch 1 ro "Host controller halted see Run/Stop";
|
||||
_ 6 mbz;
|
||||
iaa 1 rwc "Interrupt on Async advance";
|
||||
hse 1 rwc "Host system error";
|
||||
flr 1 rwc "Frame list rollover";
|
||||
pcd 1 rwc "Port change detect";
|
||||
usbei 1 rwc "USB error interrupt";
|
||||
usbi 1 rwc "USB interrupt";
|
||||
};
|
||||
|
||||
// 2.3.3
|
||||
register usbintr rw addr(op, 0x08) "USB interrupt enable" {
|
||||
_ 26 mbz;
|
||||
iaae 1 "Interrupt on async advance enable";
|
||||
hsee 1 "Host system error enable";
|
||||
flre 1 "Frame list rollover enable";
|
||||
pcie 1 "Port change interrupt enable";
|
||||
usbeie 1 "USB error interrupt enable";
|
||||
usbie 1 "USB interrupt enable";
|
||||
};
|
||||
|
||||
// 2.3.4
|
||||
register frindex rw addr(op, 0x0C) "Frame index" {
|
||||
_ 18 mbz;
|
||||
fi 14 "Frame index";
|
||||
};
|
||||
|
||||
// 2.3.5
|
||||
// NOTE: Only enabled if 64 bit address capability is enabled
|
||||
register ctrldssegment rw addr(op, 0x10) "Control data structure segment" {
|
||||
data 32 rw "MSB [63:32] bits of EHCI data strctures";
|
||||
};
|
||||
|
||||
// 2.3.6
|
||||
register periodiclistbase rw addr(op, 0x14) "Periodic frame list base addr" {
|
||||
addr 20 rw "Base address (must be 4k aligned)";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
// 2.3.7
|
||||
register asynclistaddr rw addr(op, 0x18) "Current async. list addr." {
|
||||
lpl 27 rw "Link pointer low";
|
||||
_ 5 mbz;
|
||||
};
|
||||
|
||||
// 2.3.8
|
||||
register configflag rw addr(op, 0x40) "Configure flag" {
|
||||
_ 31 mbz;
|
||||
cf 1 rw "Configure flag";
|
||||
};
|
||||
|
||||
// 2.3.9
|
||||
constants test_mode_val "Test modes" {
|
||||
disabled = 0b0000 "Test mode not enabled";
|
||||
test_j_st = 0b0001 "Test J_STATE";
|
||||
test_k_st = 0b0010 "Test K_STATE";
|
||||
se0_nak = 0b0011 "Test SE0_NAK";
|
||||
test_pack = 0b0100 "Test packet";
|
||||
force_ena = 0b0101 "Force enable";
|
||||
};
|
||||
|
||||
constants indi_val "Port indicator values" {
|
||||
off = 0b00 "Port indicators are off";
|
||||
amber = 0b01 "Amber";
|
||||
green = 0b10 "Green";
|
||||
indi_val_undef = 0b11 "Undefined";
|
||||
};
|
||||
|
||||
constants lstatus_val "USB line status" {
|
||||
se0 = 0b00 "Not low speed device, perform EHCI reset";
|
||||
j_state = 0b10 "Not low speed device, perform EHCI reset";
|
||||
k_state = 0b01 "Low speed device, release ownership of port";
|
||||
lstatus_undef = 0b11 "Not low speed device, perform EHCI reset";
|
||||
};
|
||||
|
||||
regarray portsc rw addr(op, 0x44)[16] "Port status and control" {
|
||||
_ 9 mbz;
|
||||
wkoc_e 1 "Wake on over-current enable";
|
||||
wkdscnnt_e 1 "Wake on disconnect enable";
|
||||
wkcnnt_e 1 "Wake on connect enable";
|
||||
ptc 4 type(test_mode_val) "Port test control";
|
||||
pic 2 type(indi_val) "Port indicator control";
|
||||
po 1 "Port owner";
|
||||
pp 1 "Port power";
|
||||
ls 2 type(lstatus_val) "Line status value";
|
||||
_ 1 mbz;
|
||||
pr 1 "Port reset";
|
||||
sus 1 "Port suspend";
|
||||
fpr 1 "Force port resume";
|
||||
occ 1 rwc "Over current change";
|
||||
oca 1 ro "Over current active";
|
||||
pec 1 rwc "Port enable/disbale change";
|
||||
ped 1 "Port enabled/disabled";
|
||||
csc 1 rwc "Connect status change";
|
||||
ccs 1 ro "Current connect status";
|
||||
};
|
||||
/*
|
||||
//
|
||||
// In-memory data structures
|
||||
//
|
||||
|
||||
// 3.1
|
||||
constants lptype width(2) "Link pointer type" {
|
||||
lp_itd = 0b00 "Isochronous transfer descriptor";
|
||||
lp_qh = 0b01 "Queue head";
|
||||
lp_sitd = 0b10 "Split transaction isochronous trans. desc.";
|
||||
lp_fstn = 0b11 "Frame span traversal node";
|
||||
};
|
||||
|
||||
datatype lp msbfirst(32) "Link pointer" {
|
||||
p 27 "Frame list link pointer";
|
||||
_ 2 mbz;
|
||||
typ 2 type(lptype) "Pointer type";
|
||||
t 1 "Pointer value invalid";
|
||||
};
|
||||
|
||||
// 3.3
|
||||
datatype itd msbfirst(32) "Isochronous transfer descriptor" {
|
||||
next 32 type(lp) "Next descriptor";
|
||||
sc0 32 type(itsc) "Transaction 0 Status/control";
|
||||
sc1 32 type(itsc) "Transaction 1 Status/control";
|
||||
sc2 32 type(itsc) "Transaction 2 Status/control";
|
||||
sc3 32 type(itsc) "Transaction 3 Status/control";
|
||||
sc4 32 type(itsc) "Transaction 4 Status/control";
|
||||
sc5 32 type(itsc) "Transaction 5 Status/control";
|
||||
sc6 32 type(itsc) "Transaction 6 Status/control";
|
||||
sc7 32 type(itsc) "Transaction 7 Status/control";
|
||||
bp0 32 type(itbp0) "Buffer pointer 0";
|
||||
bp1 32 type(itbp1) "Buffer pointer 1";
|
||||
bp2 32 type(itbp2) "Buffer pointer 2";
|
||||
bp3 32 type(itbp3) "Buffer pointer 3";
|
||||
bp4 32 type(itbp3) "Buffer pointer 4";
|
||||
bp5 32 type(itbp3) "Buffer pointer 5";
|
||||
bp6 32 type(itbp3) "Buffer pointer 6";
|
||||
};
|
||||
|
||||
// 3.3.2
|
||||
datatype itsc msbfirst(32) "Isochronous transaction status/control" {
|
||||
// Status
|
||||
active 1 "Active";
|
||||
dbe 1 "Data buffer error";
|
||||
bd 1 "Babble detected";
|
||||
xacterr 1 "Transaction error";
|
||||
// Control
|
||||
length 12 "Transaction length";
|
||||
ioc 1 "Interrupt on complete";
|
||||
pg 3 "Page select (0-6)";
|
||||
offset 12 "Offset from state of buffer";
|
||||
};
|
||||
|
||||
// 3.3.3
|
||||
datatype itbp0 msbfirst(32) "iTD buffer pointer page 0" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
epn 4 "Endpoint number";
|
||||
_ 1 mbz;
|
||||
da 7 "Device address";
|
||||
};
|
||||
datatype itdp1 msbfirst(32) "iTD buffer pointer page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
dir 1 "In (1) or out (0) PID";
|
||||
mps 11 "Maximum packet size";
|
||||
};
|
||||
datatype itdp2 msbfirst(32) "iTD buffer pointer page 2" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 10 mbz;
|
||||
multi 2 "Num. transactions/micro-frame + 1 (0=rsvd)";
|
||||
};
|
||||
datatype itdp3 msbfirst(32) "iTD buffer pointer page 3" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
// 3.4
|
||||
datatype sitd msbfirst(32) "Split isochronous transfer descriptor" {
|
||||
next 32 type(lp) "Next descriptor";
|
||||
cap 32 type(sitcap) "Endpoint capabilities/characteristics";
|
||||
msc 32 type(sitmsc) "Micro-frame schedule control";
|
||||
tsc 32 type(sittsc) "Transfer status and control";
|
||||
bpl0 32 type(sitbpl0) "Buffer page pointer 0";
|
||||
bpl1 32 type(sitbpl1) "Buffer page pointer 1";
|
||||
bp 32 type(sitblp) "Back link";
|
||||
};
|
||||
|
||||
// 3.4.2
|
||||
datatype sitcap msbfirst(32) "siTD endpoint capabilities/characteristics" {
|
||||
dir 1 "In (1) or out (0) PID";
|
||||
port 7 "Port number";
|
||||
_ 1 mbz;
|
||||
hub 7 "Hub address";
|
||||
_ 4 mbz;
|
||||
epn 4 "Endpoint number";
|
||||
_ 1 mbz;
|
||||
da 7 "Device address";
|
||||
};
|
||||
datatype sitmsc msbfirst(32) "siTD micro-frame schedule control" {
|
||||
_ 16 mbz;
|
||||
scm 8 "Split completion mask";
|
||||
ssm 8 "Split start mask";
|
||||
};
|
||||
|
||||
// 3.4.3
|
||||
datatype sittsc msbfirst(32) "siTD transfer status and control" {
|
||||
ioc 1 "Interrupt on complete";
|
||||
p 1 "Page select";
|
||||
_ 4 mbz;
|
||||
total 10 "Total bytes to transfer";
|
||||
cpm 8 "Microframe complete-split progress mask";
|
||||
active 1 "Status active";
|
||||
err 1 "ERR response rcvd from transaction translator";
|
||||
dbe 1 "Data buffer error";
|
||||
babble 1 "Babble detected";
|
||||
xacterr 1 "Transaction error";
|
||||
mmf 1 "Missed micro-frame";
|
||||
sts 1 "Split transaction state";
|
||||
_ 1 mbz;
|
||||
};
|
||||
|
||||
// 3.4.4
|
||||
constants xpos width(2) "Transaction position" {
|
||||
tp_all = 0b00 "Entire payload";
|
||||
tp_begin = 0b01 "First data payload";
|
||||
tp_mid = 0b10 "Middle payload";
|
||||
tp_end = 0b11 "Final payload";
|
||||
};
|
||||
datatype sitbpl0 msbfirst(32) "siTD buffer page pointer list page 0" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
offset 12 "Current offset";
|
||||
};
|
||||
datatype sitbpl1 msbfirst(32) "siTD buffer page pointer list page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 7 mbz;
|
||||
tp 2 type(xpos) "Transaction position";
|
||||
tc 3 "Transaction count";
|
||||
};
|
||||
|
||||
// 3.4.5
|
||||
datatype sitblp msbfirst(32) "siTD back link pointer" {
|
||||
bp 27 "Back pointer";
|
||||
_ 4 mbz;
|
||||
t 1 "Terminate (0 -> bp is valid)";
|
||||
};
|
||||
|
||||
// 3.5
|
||||
datatype qtd msbfirst(32) "Queue element transfer descriptor" {
|
||||
next 32 type(lp) "Next element";
|
||||
altnext 32 type(lp) "Alternate next pointer";
|
||||
token 32 type(qttok) "Token";
|
||||
bp0 32 type(qtbp0) "Buffer pointer 0";
|
||||
bp1 32 type(qtbp1) "Buffer pointer 1";
|
||||
bp2 32 type(qtbp1) "Buffer pointer 2";
|
||||
bp3 32 type(qtbp1) "Buffer pointer 3";
|
||||
bp4 32 type(qtbp1) "Buffer pointer 4";
|
||||
};
|
||||
|
||||
// 3.5.3
|
||||
constants pid "PID token encoding" {
|
||||
pid_out = 0b00 "Generates OUT token (E1H)";
|
||||
pid_in = 0b01 "Generates IN token (69H)";
|
||||
pid_setup = 0b10 "Generates SETUP token (2DH)";
|
||||
pid_rsvd = 0b11 "Reserved";
|
||||
};
|
||||
|
||||
datatype qttok msbfirst(32) "qTD Token" {
|
||||
toggle 1 "Data toggle";
|
||||
tbt 15 "Total bytes to transfer";
|
||||
ioc 1 "Interrupt on complete";
|
||||
cp 3 "Current page";
|
||||
cerr 2 "Error counter";
|
||||
pidc 2 type(pid) "PID code token";
|
||||
active 1 "Status active";
|
||||
halted 1 "Serious error at endpoint";
|
||||
dbe 1 "Data buffer error";
|
||||
babble 1 "Babble detected";
|
||||
xacterr 1 "Transaction error";
|
||||
mmf 1 "Missed micro-frame";
|
||||
sts 1 "Split transaction state";
|
||||
ping 1 "Ping state";
|
||||
};
|
||||
|
||||
// 3.5.4
|
||||
datatype qtbp0 msbfirst(32) "Queue element buffer pointer page 0" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
offset 12 "Current offset";
|
||||
};
|
||||
datatype qtbp1 msbfirst(32) "Queue element buffer pointer page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
// 3.6
|
||||
datatype qh msbfirst(32) "Queue head" {
|
||||
hlp 32 type(lp) "Horizontal link pointer";
|
||||
cap1 32 type(qhcap1) "Endpoint capabilities/characteristics 1";
|
||||
cap2 32 type(qhcap2) "Endpoint capabilities/characteristics 2";
|
||||
current 32 type(lp) "Current element";
|
||||
next 32 type(lp) "Next element";
|
||||
altnext 32 type(qhlp) "Alternate next pointer";
|
||||
token 32 type(qttok) "Token";
|
||||
bp0 32 type(qtbp0) "Buffer pointer 0";
|
||||
bp1 32 type(qhbp1) "Buffer pointer 1";
|
||||
bp2 32 type(qhbp2) "Buffer pointer 2";
|
||||
bp3 32 type(qtbp1) "Buffer pointer 3";
|
||||
bp4 32 type(qtbp1) "Buffer pointer 4";
|
||||
};
|
||||
|
||||
// 3.6.2
|
||||
constants speed width(2) "Endpoint speed" {
|
||||
fullspeed = 0b00 "Full-speed (12Mbs)";
|
||||
lowspeed = 0b01 "Low-speed (1.5Mbs)";
|
||||
highspeed = 0b10 "High-speed (480 Mb/s)";
|
||||
};
|
||||
|
||||
datatype qhcap1 msbfirst(32) "Endpoint capabilities: queue head word 1"{
|
||||
rl 4 "NAK count reload";
|
||||
c 1 "Control endpoint flag";
|
||||
mpl 11 "Maximum packet length";
|
||||
h 1 "Head of reclamation list flag";
|
||||
dtc 1 "Data toggle control";
|
||||
eps 2 type(speed) "Endpoint speed";
|
||||
epn 4 "Endpoint number";
|
||||
i 1 "Inactivate on next transaction";
|
||||
da 7 "Device address";
|
||||
};
|
||||
|
||||
datatype qhcap2 msbfirst(32) "Endpoint capabilities: queue head word 2"{
|
||||
mult 2 "High-bandwidth pipe multiplier";
|
||||
port 7 "Port number";
|
||||
hub 7 "Hub address";
|
||||
scm 8 "Split completion mask";
|
||||
ism 8 "Interrupt schedule mask";
|
||||
};
|
||||
|
||||
// 3.6.3
|
||||
datatype qhlpa msbfirst(32) "Alternate queue head link pointer" {
|
||||
p 27 "Frame list link pointer";
|
||||
nakcnt 4 "NACK counter";
|
||||
t 1 "Pointer value invalid";
|
||||
};
|
||||
|
||||
datatype qhbp1 msbfirst(32) "Queue head buffer pointer page 1" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
_ 4 mbz;
|
||||
cpm 8 "Split-transaction complete-split progress";
|
||||
};
|
||||
|
||||
datatype qhbp2 msbfirst(32) "Queue head buffer pointer page 2" {
|
||||
p 20 "Buffer pointer (4k aligned)";
|
||||
sb 7 "S-bytes";
|
||||
ft 5 "Split-transaction frame tag";
|
||||
};
|
||||
|
||||
// 3.7
|
||||
datatype fstm msbfirst(32) "Periodic Frame Span Traversal Node" {
|
||||
normal 32 type(lp) "Normal path link pointer";
|
||||
back 32 type(lp) "Back path link pointer";
|
||||
};*/
|
||||
};
|
||||
|
||||
340
devices/omap/ohci.dev
Normal file
340
devices/omap/ohci.dev
Normal file
@ -0,0 +1,340 @@
|
||||
/*
|
||||
* Copyright (c) 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaestr. 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ohci.dev
|
||||
*
|
||||
* DESCRIPTION: Open Host Controller Interface (OHCI) description
|
||||
*
|
||||
* Archaic USB interface, but still found on e.g. ATI and NVidia
|
||||
* chipsets.
|
||||
*
|
||||
* Numbers in comments refer to the OpenHCI Open Host Controller
|
||||
* Interface Specification for USB, by Compaq, Microsoft, and National
|
||||
* Semiconductor, 09/14/99 2:33 PM, Release: 1.0a
|
||||
*/
|
||||
|
||||
|
||||
device ohci lsbfirst ( addr base ) "OHCI USB controller" {
|
||||
|
||||
/*
|
||||
//
|
||||
// Data structures
|
||||
//
|
||||
|
||||
// 4.2.1
|
||||
constants direction width(2) "Data flow direction" {
|
||||
dir_td = 0b00 "Get direction from TD";
|
||||
dir_out = 0b01 "Out";
|
||||
dir_in = 0b10 "In";
|
||||
dir_td1 = 0b11 "Get direction from TD (alt)";
|
||||
};
|
||||
|
||||
datatype epdesc lsbfirst(32) "Endpoint descriptor" {
|
||||
fa 7 "Function address";
|
||||
en 4 "Endpoint number";
|
||||
d 2 type(direction) "Direction";
|
||||
s 1 "Speed (1=low, 0=full)";
|
||||
k 1 "Skip";
|
||||
f 1 "Format (1=isochronous, 0=general)";
|
||||
mps 11 "Maximum packet size";
|
||||
_ 5;
|
||||
_ 4;
|
||||
tailp 28 "TD queue tail pointer";
|
||||
h 1 "Halted";
|
||||
c 1 "Toggle carry";
|
||||
_ 2 mbz;
|
||||
headp 28 "TD queue head pointer";
|
||||
_ 4;
|
||||
nexted 28 "Next endpoint descriptor";
|
||||
};
|
||||
|
||||
// 4.3.1
|
||||
constants pid width(2) "Direction / PID for token" {
|
||||
pid_setup = 0b00 "Setup (to endpoint)";
|
||||
pid_out = 0b01 "To endpoint";
|
||||
pid_in = 0b10 "From endpoint";
|
||||
};
|
||||
datatype gentd lsbfirst(32) "General transfer descriptor" {
|
||||
_ 18;
|
||||
r 1 "Buffer rounding";
|
||||
dp 2 type(pid) "Direction or PID";
|
||||
di 3 "Delay interrupt frames";
|
||||
t 2 "Data toggle";
|
||||
ec 2 "Error count";
|
||||
cc 4 type(ccode) "Condition code for last attempted transaction";
|
||||
cbp 32 "Current buffer pointer";
|
||||
_ 4 mbz;
|
||||
nexttd 28 "Next transfer descriptor";
|
||||
be 32 "Buffer end";
|
||||
};
|
||||
|
||||
|
||||
// 4.3.2
|
||||
datatype isotd lsbfirst(32) "Isochronous transfer descriptor" {
|
||||
sf 16 "Starting frame";
|
||||
_ 5;
|
||||
di 3 "Delay interrupt frames";
|
||||
fc 3 "Frame count";
|
||||
_ 1;
|
||||
cc 4 type(ccode) "Condition code for last attempted transaction";
|
||||
_ 12;
|
||||
bp0 20 "Buffer page 0";
|
||||
_ 5 mbz;
|
||||
nexttd 27 "Next transfer descriptor";
|
||||
be 32 "Buffer end";
|
||||
ofpsw0 16 "Offset / packet status word 0";
|
||||
ofpsw1 16 "Offset / packet status word 1";
|
||||
ofpsw2 16 "Offset / packet status word 2";
|
||||
ofpsw3 16 "Offset / packet status word 4";
|
||||
ofpsw4 16 "Offset / packet status word 3";
|
||||
ofpsw5 16 "Offset / packet status word 5";
|
||||
ofpsw6 16 "Offset / packet status word 6";
|
||||
ofpsw7 16 "Offset / packet status word 7";
|
||||
};
|
||||
datatype psw lsbfirst(16) "Packet status word" {
|
||||
size 11 "Size of packet";
|
||||
_ 1 mbz;
|
||||
cc 4 type(ccode) "Condition code";
|
||||
};
|
||||
|
||||
/// 4.3.3
|
||||
constants ccode width(4) "Completion codes" {
|
||||
cc_ne = 0b0000 "No error";
|
||||
cc_crc = 0b0001 "CRC error";
|
||||
cc_bs = 0b0010 "Bitstuffing violation";
|
||||
cc_dtm = 0b0011 "Data toggle PID mismatch";
|
||||
cc_stl = 0b0100 "EP returned stall PID";
|
||||
cc_dnr = 0b0101 "Device not responding";
|
||||
cc_pcf = 0b0110 "PID check failure";
|
||||
cc_uxp = 0b0111 "Unexpected PID";
|
||||
cc_dor = 0b1000 "Data overrun";
|
||||
cc_dur = 0b1001 "Data underrun";
|
||||
cc_bor = 0b1100 "Buffer overrun";
|
||||
cc_bur = 0b1101 "Buffer underrun";
|
||||
cc_nac = 0b1110 "Not accessed";
|
||||
cc_nac_ = 0b1111 "Not accessed (alternate)";
|
||||
};
|
||||
*/
|
||||
//
|
||||
// Registers
|
||||
//
|
||||
// 7.1 Control and status partition
|
||||
//
|
||||
|
||||
// 7.1.1 Interface revision
|
||||
/// Initially 0x10.
|
||||
register revision ro addr (base, 0x00) "Revision" {
|
||||
rev 8 "BCD rep. of interface version";
|
||||
_ 24;
|
||||
};
|
||||
|
||||
// 7.1.2 Control register
|
||||
constants state "Functional state" {
|
||||
st_reset = 0b00 "Reset (after h/w reset)";
|
||||
st_resume = 0b01 "Resume from downstream port";
|
||||
st_operational = 0b10 "Operational (running)";
|
||||
st_suspend = 0b11 "Suspend (after s/w reset)";
|
||||
};
|
||||
// Initially 0x00
|
||||
register control rw addr (base, 0x04) "Control" {
|
||||
cbsr 2 "Control/bulk service ratio";
|
||||
pe 1 "Periodic list enable";
|
||||
ie 1 "Isochronous enable";
|
||||
cle 1 "Control list enable";
|
||||
ble 1 "Bulk list enable";
|
||||
hcfs 2 type(state) "Host controller functional state";
|
||||
ir 1 "Interrupt routing";
|
||||
rwc 1 "Remote wakeup connected";
|
||||
rwe 1 "Remote wakeup enabled";
|
||||
_ 21;
|
||||
};
|
||||
|
||||
|
||||
// 7.1.3 Command and Status
|
||||
// Initially 0x00
|
||||
register cmdstatus rw addr (base, 0x08) "08 CommandStatus" {
|
||||
hcr 1 "Host controller reset";
|
||||
clf 1 "Control list filled";
|
||||
blf 1 "Bulk list filled";
|
||||
ocr 1 "Ownership change request";
|
||||
_ 12;
|
||||
soc 2 ro "Scheduling overrun count";
|
||||
_ 14;
|
||||
};
|
||||
|
||||
// 7.1.4-6: Interrupt registers
|
||||
regtype interrupt "Interrupts" {
|
||||
so 1 "Scheduling overrun";
|
||||
wdh 1 "Writeback done head";
|
||||
sf 1 "Start of frame";
|
||||
rd 1 "Resume detected";
|
||||
ue 1 "Unrecoverable error";
|
||||
fno 1 "Frame number overflow";
|
||||
rhsc 1 "Root hub status change";
|
||||
_ 23;
|
||||
oc 1 "Ownership change";
|
||||
mie 1 "Master interrupt enable";
|
||||
};
|
||||
register intstatus rw addr (base, 0x0C) "Interrupt status"
|
||||
type(interrupt);
|
||||
register intenable rw addr (base, 0x10) "Interrupt enable"
|
||||
type(interrupt);
|
||||
register intdisable rw addr (base, 0x14) "Interrupt disable"
|
||||
type(interrupt);
|
||||
|
||||
//
|
||||
// 7.2 Memory pointer partition
|
||||
//
|
||||
|
||||
// 7.2.1
|
||||
register hcca rw addr (base, 0x18) "Host controller communication area" {
|
||||
_ 8 mbz;
|
||||
hcca 24 "Physical address";
|
||||
};
|
||||
|
||||
regtype physptr "Physical address pointer" {
|
||||
_ 4 mbz;
|
||||
addr 28 "Address";
|
||||
};
|
||||
|
||||
// 7.2.2.
|
||||
register period_cur ro addr (base, 0x1C) "Cur. isochronous or int. ED"
|
||||
type(physptr);
|
||||
|
||||
// 7.2.3
|
||||
register ctrl_head rw addr (base, 0x20) "First ED of control list"
|
||||
type(physptr);
|
||||
|
||||
|
||||
// 7.2.4
|
||||
register ctrl_cur rw addr (base, 0x24) "Current ED of control list"
|
||||
type(physptr);
|
||||
|
||||
// 7.2.5
|
||||
register bulk_head rw addr (base, 0x28) "First ED of bulk list"
|
||||
type(physptr);
|
||||
|
||||
// 7.2.6
|
||||
register bulk_cur rw addr (base, 0x2C) "Current ED of bulk list"
|
||||
type(physptr);
|
||||
|
||||
|
||||
// 7.2.7
|
||||
register done_head ro addr (base, 0x30) "Done head pointer"
|
||||
type(physptr);
|
||||
|
||||
//
|
||||
// 7.3 Frame counter partition
|
||||
//
|
||||
|
||||
// 7.3.1
|
||||
register fm_interval rw addr (base, 0x34) "Frame interval" {
|
||||
fi 14 "Frame interval (dflt 0x2edf)";
|
||||
_ 2;
|
||||
fsmps 15 "FS largest data packet";
|
||||
fit 1 "Frame interval toggle";
|
||||
};
|
||||
|
||||
// 7.3.2
|
||||
register fm_remain ro addr (base, 0x38) "Frame remaining" {
|
||||
fr 14 "Bit time remaining in current frame";
|
||||
_ 17;
|
||||
frt 1 "Frame remaining toggle";
|
||||
};
|
||||
|
||||
// 7.3.3
|
||||
register fm_num ro addr (base, 0x3C) "Frame number" {
|
||||
fn 16 "Frame number (16-bit counter)";
|
||||
_ 16;
|
||||
};
|
||||
|
||||
// 7.3.4
|
||||
register period_start rw addr (base, 0x40) "Period start" {
|
||||
ps 14 "Start time for processing periodic list";
|
||||
_ 18;
|
||||
};
|
||||
|
||||
// 7.3.5
|
||||
register hclsthreshold rw addr (base, 0x44) "LS threshold" {
|
||||
lst 11 "Low-speed threshold (should be 0x0628)";
|
||||
_ 21;
|
||||
};
|
||||
|
||||
//
|
||||
// 7.4 Root Hub partition
|
||||
//
|
||||
|
||||
// 7.4.1
|
||||
register rh_descra rw addr (base, 0x48) "Root hub descriptor a" {
|
||||
ndp 8 ro "Number of downstream ports";
|
||||
psm 1 "Power switching mode";
|
||||
nps 1 "No power switching";
|
||||
dt 1 ro "Device type";
|
||||
ocpm 1 "Overcurrent protection mode";
|
||||
nocp 1 "No overcurrent protection";
|
||||
_ 11;
|
||||
potpgt 8 "Power-on to power-good time (* 2ms)";
|
||||
};
|
||||
|
||||
// 7.4.2
|
||||
register rh_descrb rw addr (base, 0x4C) "Root hub descriptor b" {
|
||||
dr 16 "Device removal";
|
||||
ppcm 16 "Port power control mask";
|
||||
};
|
||||
|
||||
// 7.4.3
|
||||
register rh_status rw addr (base, 0x50) "Root hub status" {
|
||||
lps 1 wo "Clear global power";
|
||||
oci 1 ro "Overcurrent indicator";
|
||||
_ 13;
|
||||
drwe 1 rw1c "Device remote wakeup enable";
|
||||
lpsc 1 wo "Set globl power";
|
||||
ocic 1 rw1c "Overcurrent indicator change";
|
||||
_ 13;
|
||||
crwe 1 wo "Clear remote wakeup enable";
|
||||
};
|
||||
|
||||
// 7.4.4
|
||||
// Assume 256 ports at this stage; it's actually given by
|
||||
// rh_descra->ndp.
|
||||
regarray rh_portstat ro addr (base, 0x54)[256] "Root hub port status" {
|
||||
ccs 1 "Current connection status";
|
||||
pes 1 "Port enable status";
|
||||
pss 1 "Port suspend status";
|
||||
poci 1 "Port overcurrent indicator";
|
||||
prs 1 "Port reset status";
|
||||
_ 3;
|
||||
pps 1 "Port power status";
|
||||
lsda 1 "Low-speed device attached";
|
||||
_ 6;
|
||||
csc 1 "Connect status change";
|
||||
pesc 1 "Port enable status change";
|
||||
pssc 1 "Port suspend status change";
|
||||
ocic 1 "Port overcurrent indicator change";
|
||||
prsc 1 "Port reset status change";
|
||||
_ 11;
|
||||
};
|
||||
regarray rh_portctrl wo also addr (base, 0x54)[256] "Root hub port control" {
|
||||
cpe 1 "Clear port enable";
|
||||
spe 1 "Set port enable";
|
||||
sps 1 "Set port suspend";
|
||||
css 1 "Clear suspend status";
|
||||
spr 1 "Set port reset";
|
||||
_ 3;
|
||||
spp 1 "Set port power";
|
||||
cpp 1 "Clear port power";
|
||||
_ 6;
|
||||
csc 1 "Clear connect status change";
|
||||
pesc 1 "Clear port enable status change";
|
||||
pssc 1 "Clear port suspend status change";
|
||||
ocic 1 "Clear port overcurrent indicator change";
|
||||
prsc 1 "Clear port reset status change";
|
||||
_ 11;
|
||||
};
|
||||
};
|
||||
40
devices/omap/omap44xx_32ktimer.dev
Normal file
40
devices/omap/omap44xx_32ktimer.dev
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_32ktimer.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_32ktimer msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
register 32ksyncnt_rev ro addr(base, 0x0) "This register contains the sync counter IP revision code." type(uint32);
|
||||
|
||||
register 32ksyncnt_sysconfig addr(base, 0x4) "This register is used for IDLE modes only." {
|
||||
_ 27 mbz;
|
||||
idlemode 2 rw "Power management REQ/ACK control";
|
||||
_ 3 mbz;
|
||||
};
|
||||
|
||||
register 32ksyncnt_cr ro addr(base, 0x10) "This register contains the 32-kHz sync counter value." type(uint32);
|
||||
};
|
||||
235
devices/omap/omap44xx_abe_cm1.dev
Normal file
235
devices/omap/omap44xx_abe_cm1.dev
Normal file
@ -0,0 +1,235 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_abe_cm1.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_abe_cm1 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants clkactivity_abe_24m_fclk_status width(1) "" {
|
||||
CLKACTIVITY_ABE_24M_FCLK_0_r = 0 "Corresponding clock is definitely gated";
|
||||
CLKACTIVITY_ABE_24M_FCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
|
||||
};
|
||||
|
||||
constants clktrctrl_status width(2) "" {
|
||||
CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
|
||||
CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
|
||||
CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
|
||||
CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
|
||||
};
|
||||
|
||||
register cm1_abe_clkstctrl addr(base, 0x0) "This register enables the ABE domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
|
||||
_ 18 mbz;
|
||||
clkactivity_abe_24m_fclk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_24M_FCLK clock in the domain. [warm reset insensitive]";
|
||||
clkactivity_abe_alwon_32k_clk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_ALWON_32K_CLK clock in the domain. [warm reset insensitive]";
|
||||
clkactivity_abe_sysclk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_SYSCLK clock in the domain. [warm reset insensitive]";
|
||||
clkactivity_24m_fclk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the 24M_FCLK clock in the domain. [warm reset insensitive]";
|
||||
clkactivity_abe_iclk2 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_ICLK2 interface clock in the domain. [warm reset insensitive]";
|
||||
clkactivity_dpll_abe_x2_clk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the DPLL_ABE_X2_CLK clock in the domain. [warm reset insensitive]";
|
||||
_ 6 mbz;
|
||||
clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the ABE clock domain.";
|
||||
};
|
||||
|
||||
constants idlest_status width(2) "" {
|
||||
IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
|
||||
IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
|
||||
IDLEST_2_r = 2 "Module is in Idle mode (only INTRCONN part). It is functional if using separate functional clock";
|
||||
IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
|
||||
};
|
||||
|
||||
constants modulemode_status width(2) "" {
|
||||
MODULEMODE_1_r = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state.";
|
||||
};
|
||||
|
||||
register cm1_abe_l4abe_clkctrl addr(base, 0x20) "This register manages the L4ABE clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
constants clksel_aess_fclk_status width(1) "" {
|
||||
CLKSEL_AESS_FCLK_0 = 0 "AESS_FCLK is divide by 1 of ABE_CLK";
|
||||
CLKSEL_AESS_FCLK_1 = 1 "AESS_FCLK is divide by 2 of ABE_CLK";
|
||||
};
|
||||
|
||||
constants stbyst_status width(1) "" {
|
||||
STBYST_0_r = 0 "Module is functional (not in standby)";
|
||||
STBYST_1_r = 1 "Module is in standby";
|
||||
};
|
||||
|
||||
constants modulemode_status1 width(2) "" {
|
||||
MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
|
||||
MODULEMODE_1_r_1 = 1 "Reserved";
|
||||
MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
|
||||
MODULEMODE_3_r = 3 "Reserved";
|
||||
};
|
||||
|
||||
register cm1_abe_aess_clkctrl addr(base, 0x28) "This register manages the AESS clocks." {
|
||||
_ 7 mbz;
|
||||
clksel_aess_fclk 1 rw type(clksel_aess_fclk_status) "Selects the ratio of AESS_FCLK to ABE_CLK";
|
||||
_ 5 mbz;
|
||||
stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_pdm_clkctrl addr(base, 0x30) "This register manages the PDM clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
constants clksel_internal_source_status width(2) "" {
|
||||
CLKSEL_INTERNAL_SOURCE_0 = 0 "24MHz clock derived from DPLL_ABE is selected";
|
||||
CLKSEL_INTERNAL_SOURCE_1 = 1 "ABE_SYSCLK is selected";
|
||||
CLKSEL_INTERNAL_SOURCE_2 = 2 "24MHz clock derived from DPLL_PER is selected";
|
||||
CLKSEL_INTERNAL_SOURCE_3 = 3 "Reserved";
|
||||
};
|
||||
|
||||
constants clksel_source_status width(2) "" {
|
||||
CLKSEL_SOURCE_0 = 0 "Functional clock is sourced from an internal clock";
|
||||
CLKSEL_SOURCE_1 = 1 "Functional clock is sourced from CLKS pad";
|
||||
CLKSEL_SOURCE_2 = 2 "Functional clock is sourced from Audio SIMBUS pad";
|
||||
CLKSEL_SOURCE_3 = 3 "Reserved";
|
||||
};
|
||||
|
||||
register cm1_abe_dmic_clkctrl addr(base, 0x38) "This register manages the DMIC clocks." {
|
||||
_ 4 mbz;
|
||||
clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
|
||||
clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_mcasp_clkctrl addr(base, 0x40) "This register manages the MCASP clocks." {
|
||||
_ 4 mbz;
|
||||
clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
|
||||
clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_mcbsp1_clkctrl addr(base, 0x48) "This register manages the MCBSP1 clocks." {
|
||||
_ 4 mbz;
|
||||
clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
|
||||
clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_mcbsp2_clkctrl addr(base, 0x50) "This register manages the MCBSP2 clocks." {
|
||||
_ 4 mbz;
|
||||
clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
|
||||
clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_mcbsp3_clkctrl addr(base, 0x58) "This register manages the MCBSP3 clocks." {
|
||||
_ 4 mbz;
|
||||
clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
|
||||
clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
constants optfclken_slimbus_clk_status width(1) "" {
|
||||
OPTFCLKEN_SLIMBUS_CLK_0 = 0 "Optional functional clock is disabled";
|
||||
OPTFCLKEN_SLIMBUS_CLK_1 = 1 "Optional functional clock is enabled";
|
||||
};
|
||||
|
||||
register cm1_abe_slimbus_clkctrl addr(base, 0x60) "This register manages the SLIMBUS clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 4 mbz;
|
||||
optfclken_slimbus_clk 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
|
||||
optfclken_fclk2 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
|
||||
optfclken_fclk1 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
|
||||
optfclken_fclk0 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
|
||||
_ 6 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
constants clksel_status width(1) "" {
|
||||
CLKSEL_0 = 0 "Selects ABE_SYSCLK as the functional clock";
|
||||
CLKSEL_1 = 1 "Selects ABE_ALWON_32K_CLK as the functional clock";
|
||||
};
|
||||
|
||||
register cm1_abe_gptimer5_clkctrl addr(base, 0x68) "This register manages the TIMER5 clocks." {
|
||||
_ 7 mbz;
|
||||
clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_gptimer6_clkctrl addr(base, 0x70) "This register manages the TIMER6 clocks." {
|
||||
_ 7 mbz;
|
||||
clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_gptimer7_clkctrl addr(base, 0x78) "This register manages the TIMER7 clocks." {
|
||||
_ 7 mbz;
|
||||
clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_gptimer8_clkctrl addr(base, 0x80) "This register manages the TIMER8 clocks." {
|
||||
_ 7 mbz;
|
||||
clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
|
||||
_ 6 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm1_abe_wdtimer3_clkctrl addr(base, 0x88) "This register manages the WDT3 clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
};
|
||||
308
devices/omap/omap44xx_abe_prm.dev
Normal file
308
devices/omap/omap44xx_abe_prm.dev
Normal file
@ -0,0 +1,308 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_abe_prm.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_abe_prm msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants periphmem_onstate_status width(2) "" {
|
||||
PERIPHMEM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON.";
|
||||
};
|
||||
|
||||
constants periphmem_retstate_status width(1) "" {
|
||||
PERIPHMEM_RETSTATE_0_r = 0 "Memory bank is off when the domain is in the RETENTION state.";
|
||||
};
|
||||
|
||||
constants aessmem_retstate_status width(1) "" {
|
||||
AESSMEM_RETSTATE_1_r = 1 "Memory bank is retained when domain is in RETENTION state.";
|
||||
};
|
||||
|
||||
constants lowpowerstatechange_status width(1) "" {
|
||||
LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change.";
|
||||
LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON.";
|
||||
};
|
||||
|
||||
constants powerstate_status width(2) "" {
|
||||
POWERSTATE_0 = 0 "OFF state";
|
||||
POWERSTATE_1 = 1 "RETENTION state";
|
||||
POWERSTATE_2 = 2 "INACTIVE state";
|
||||
POWERSTATE_3 = 3 "ON State";
|
||||
};
|
||||
|
||||
register pm_abe_pwrstctrl addr(base, 0x0) "This register controls the ABE domain power state to reach upon a domain sleep transition" {
|
||||
_ 10 mbz;
|
||||
periphmem_onstate 2 ro type(periphmem_onstate_status) "PERIPHMEM memory state when domain is ON.";
|
||||
_ 2 mbz;
|
||||
aessmem_onstate 2 ro type(periphmem_onstate_status) "AESSMEM memory state when domain is ON.";
|
||||
_ 5 mbz;
|
||||
periphmem_retstate 1 ro type(periphmem_retstate_status) "PERIPHMEM memory state when domain is RETENTION.";
|
||||
_ 1 mbz;
|
||||
aessmem_retstate 1 ro type(aessmem_retstate_status) "AESSMEM memory state when domain is RETENTION.";
|
||||
_ 3 mbz;
|
||||
lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain.";
|
||||
_ 1 mbz;
|
||||
logicretstate 1 ro type(periphmem_retstate_status) "Logic state when power domain is RETENTION";
|
||||
powerstate 2 rw type(powerstate_status) "Power state control";
|
||||
};
|
||||
|
||||
constants lastpowerstateentered_status width(2) "" {
|
||||
LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE";
|
||||
LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE";
|
||||
LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION";
|
||||
LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF";
|
||||
};
|
||||
|
||||
constants intransition_status width(1) "" {
|
||||
INTRANSITION_0_r = 0 "No ongoing transition on power domain";
|
||||
INTRANSITION_1_r = 1 "Power domain transition is in progress.";
|
||||
};
|
||||
|
||||
constants periphmem_statest_status width(2) "" {
|
||||
PERIPHMEM_STATEST_0_r = 0 "Memory is OFF";
|
||||
PERIPHMEM_STATEST_1_r = 1 "Reserved";
|
||||
PERIPHMEM_STATEST_2_r = 2 "Reserved";
|
||||
PERIPHMEM_STATEST_3_r = 3 "Memory is ON";
|
||||
};
|
||||
|
||||
constants aessmem_statest_status width(2) "" {
|
||||
AESSMEM_STATEST_0_r = 0 "Memory is OFF";
|
||||
AESSMEM_STATEST_1_r = 1 "Memory is RETENTION";
|
||||
AESSMEM_STATEST_2_r = 2 "Reserved";
|
||||
AESSMEM_STATEST_3_r = 3 "Memory is ON";
|
||||
};
|
||||
|
||||
constants logicstatest_status width(1) "" {
|
||||
LOGICSTATEST_0_r = 0 "Logic in domain is OFF";
|
||||
LOGICSTATEST_1_r = 1 "Logic in domain is ON";
|
||||
};
|
||||
|
||||
constants powerstatest_status width(2) "" {
|
||||
POWERSTATEST_0_r = 0 "Power domain is OFF";
|
||||
POWERSTATEST_1_r = 1 "Power domain is in RETENTION";
|
||||
POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE";
|
||||
POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE";
|
||||
};
|
||||
|
||||
register pm_abe_pwrstst addr(base, 0x4) "This register provides a status on the ABE domain current power domain state. [warm reset insensitive]" {
|
||||
_ 6 mbz;
|
||||
lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only.";
|
||||
_ 3 mbz;
|
||||
intransition 1 ro type(intransition_status) "Domain transition status";
|
||||
_ 10 mbz;
|
||||
periphmem_statest 2 ro type(periphmem_statest_status) "PERIPHMEM memory state status";
|
||||
_ 2 mbz;
|
||||
aessmem_statest 2 ro type(aessmem_statest_status) "AESSMEM memory state status";
|
||||
_ 1 mbz;
|
||||
logicstatest 1 ro type(logicstatest_status) "Logic state status";
|
||||
powerstatest 2 ro type(powerstatest_status) "Current power state status";
|
||||
};
|
||||
|
||||
constants lostmem_aessmem_status width(1) "" {
|
||||
LOSTMEM_AESSMEM_0 = 0 "Context has been maintained";
|
||||
LOSTMEM_AESSMEM_1 = 1 "Context has been lost";
|
||||
};
|
||||
|
||||
register rm_abe_aess_context addr(base, 0x2C) "This register contains dedicated AESS context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_aessmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in AESSMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
constants wkupdep_pdm_dma_sdma_status width(1) "" {
|
||||
WKUPDEP_PDM_DMA_SDMA_0 = 0 "Dependency is disabled";
|
||||
WKUPDEP_PDM_DMA_SDMA_1 = 1 "Dependency is enabled";
|
||||
};
|
||||
|
||||
register pm_abe_pdm_wkdep addr(base, 0x30) "This register controls wakeup dependency based on PDM service requests." {
|
||||
_ 24 mbz;
|
||||
wkupdep_pdm_dma_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from PDM module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_pdm_dma_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from PDM module (softwareakeup_dma signal) towards DSP domain";
|
||||
_ 3 mbz;
|
||||
wkupdep_pdm_irq_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from PDM module (softwareakeup_irq signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_pdm_irq_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from PDM module (softwareakeup_irq signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_pdm_context addr(base, 0x34) "This register contains dedicated PDM context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_perihpmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_dmic_wkdep addr(base, 0x38) "This register controls wakeup dependency based on DMIC service requests." {
|
||||
_ 24 mbz;
|
||||
wkupdep_dmic_dma_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from DMIC module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_dmic_dma_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from DMIC module (softwareakeup_dma signal) towards DSP domain";
|
||||
_ 3 mbz;
|
||||
wkupdep_dmic_irq_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from DMIC module (softwareakeup_irq signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_dmic_irq_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from DMIC module (softwareakeup_irq signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_dmic_context addr(base, 0x3C) "This register contains dedicated DMIC context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_perihpmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_mcasp_wkdep addr(base, 0x40) "This register controls wakeup dependency based on MCASP service requests." {
|
||||
_ 24 mbz;
|
||||
wkupdep_mcasp1_dma_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCASP1 module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_mcasp1_dma_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCASP1 module (softwareakeup_dma signal) towards DSP domain";
|
||||
_ 3 mbz;
|
||||
wkupdep_mcasp1_irq_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCASP1 module (softwareakeup_irq signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_mcasp1_irq_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCASP1 module (softwareakeup_irq signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_mcasp_context addr(base, 0x44) "This register contains dedicated MCASP context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_mcbsp1_wkdep addr(base, 0x48) "This register controls wakeup dependency based on MCBSP1 service requests." {
|
||||
_ 28 mbz;
|
||||
wkupdep_mcbsp1_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP1 module (softwareakeup signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_mcbsp1_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP1 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_mcbsp1_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP1 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_mcbsp1_context addr(base, 0x4C) "This register contains dedicated MCBSP1 context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_perihpmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_mcbsp2_wkdep addr(base, 0x50) "This register controls wakeup dependency based on MCBSP2 service requests." {
|
||||
_ 28 mbz;
|
||||
wkupdep_mcbsp2_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP2 module (softwareakeup signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_mcbsp2_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP2 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_mcbsp2_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP2 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_mcbsp2_context addr(base, 0x54) "This register contains dedicated MCBSP2 context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_perihpmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_mcbsp3_wkdep addr(base, 0x58) "This register controls wakeup dependency based on MCBSP3 service requests." {
|
||||
_ 28 mbz;
|
||||
wkupdep_mcbsp3_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP3 module (softwareakeup signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_mcbsp3_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP3 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_mcbsp3_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from MCBSP3 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_mcbsp3_context addr(base, 0x5C) "This register contains dedicated MCBSP3 context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_perihpmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_slimbus_wkdep addr(base, 0x60) "This register controls wakeup dependency based on SLIMBUS service requests." {
|
||||
_ 24 mbz;
|
||||
wkupdep_slimbus1_dma_sdma 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from SLIMBUS1 module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains";
|
||||
wkupdep_slimbus1_dma_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from SLIMBUS1 module (softwareakeup_dma signal) towards DSP domain";
|
||||
_ 3 mbz;
|
||||
wkupdep_slimbus1_irq_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from SLIMBUS1 module (softwareakeup_irq signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_slimbus1_irq_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from SLIMBUS1 module (softwareakeup_irq signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_slimbus_context addr(base, 0x64) "This register contains dedicated SLIMBUS context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_perihpmem 1 rw1c type(lostmem_aessmem_status) "Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_gptimer5_wkdep addr(base, 0x68) "This register controls wakeup dependency based on TIMER5 service requests." {
|
||||
_ 29 mbz;
|
||||
wkupdep_timer5_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER5 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_timer5_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER5 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_gptimer5_context addr(base, 0x6C) "This register contains dedicated TIMER5 context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_gptimer6_wkdep addr(base, 0x70) "This register controls wakeup dependency based on TIMER6 service requests." {
|
||||
_ 29 mbz;
|
||||
wkupdep_timer6_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER6 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_timer6_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER6 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_gptimer6_context addr(base, 0x74) "This register contains dedicated TIMER6 context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_gptimer7_wkdep addr(base, 0x78) "This register controls wakeup dependency based on TIMER7 service requests." {
|
||||
_ 29 mbz;
|
||||
wkupdep_timer7_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER7 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_timer7_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER7 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_gptimer7_context addr(base, 0x7C) "This register contains dedicated TIMER7 context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_gptimer8_wkdep addr(base, 0x80) "This register controls wakeup dependency based on TIMER8 service requests." {
|
||||
_ 29 mbz;
|
||||
wkupdep_timer8_dsp 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER8 module (softwareakeup signal) towards DSP domain";
|
||||
_ 1 mbz;
|
||||
wkupdep_timer8_mpu 1 rw type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from TIMER8 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_gptimer8_context addr(base, 0x84) "This register contains dedicated TIMER8 context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
|
||||
register pm_abe_wdtimer3_wkdep addr(base, 0x88) "This register controls wakeup dependency based on WDT3 service requests." {
|
||||
_ 31 mbz;
|
||||
wkupdep_wdt3_mpu 1 ro type(wkupdep_pdm_dma_sdma_status) "Wakeup dependency from WDT3 module (softwareakeup signal) towards MPU domain";
|
||||
};
|
||||
|
||||
register rm_abe_wdtimer3_context addr(base, 0x8C) "This register contains dedicated WDT3 context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_aessmem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal)";
|
||||
};
|
||||
};
|
||||
104
devices/omap/omap44xx_always_on_cm2.dev
Normal file
104
devices/omap/omap44xx_always_on_cm2.dev
Normal file
@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_always_on_cm2.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_always_on_cm2 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants clkactivity_core_alwon_32k_gfclk_status width(1) "" {
|
||||
CLKACTIVITY_CORE_ALWON_32K_GFCLK_0_r = 0 "Corresponding clock is definitely gated.";
|
||||
CLKACTIVITY_CORE_ALWON_32K_GFCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing.";
|
||||
};
|
||||
|
||||
constants clkactivity_sr_core_sysclk_status width(1) "" {
|
||||
CLKACTIVITY_SR_CORE_SYSCLK_0_r = 0 "Corresponding clock is definitely gated";
|
||||
CLKACTIVITY_SR_CORE_SYSCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
|
||||
};
|
||||
|
||||
constants clktrctrl_status width(2) "" {
|
||||
CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
|
||||
CLKTRCTRL_1_r = 1 "Reserved";
|
||||
CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
|
||||
CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
|
||||
};
|
||||
|
||||
register cm_alwon_clkstctrl addr(base, 0x0) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
|
||||
_ 19 mbz;
|
||||
clkactivity_core_alwon_32k_gfclk 1 ro type(clkactivity_core_alwon_32k_gfclk_status) "This field indicates the state of the CORE_ALWON_32K_GFCLK clock in the domain. [warm reset insensitive]";
|
||||
clkactivity_sr_core_sysclk 1 ro type(clkactivity_sr_core_sysclk_status) "This field indicates the state of the SR_CORE_SYSCLK clock input of the domain. [warm reset insensitive]";
|
||||
clkactivity_sr_iva_sysclk 1 ro type(clkactivity_sr_core_sysclk_status) "This field indicates the state of the SR_IVA_SYSCLK clock input of the domain. [warm reset insensitive]";
|
||||
clkactivity_sr_mpu_sysclk 1 ro type(clkactivity_sr_core_sysclk_status) "This field indicates the state of the SR_MPU_SYSCLK clock input of the domain. [warm reset insensitive]";
|
||||
clkactivity_l4_ao_iclk 1 ro type(clkactivity_sr_core_sysclk_status) "This field indicates the state of the L4_AO_ICLK clock of the domain. [warm reset insensitive]";
|
||||
_ 6 mbz;
|
||||
clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the ALWONCORE clock domain.";
|
||||
};
|
||||
|
||||
constants idlest_status width(2) "" {
|
||||
IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
|
||||
IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
|
||||
IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
|
||||
IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
|
||||
};
|
||||
|
||||
constants modulemode_status width(2) "" {
|
||||
MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
|
||||
MODULEMODE_1_r = 1 "Reserved";
|
||||
MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
|
||||
MODULEMODE_3_r = 3 "Reserved";
|
||||
};
|
||||
|
||||
register cm_alwon_sr_mpu_clkctrl addr(base, 0x28) "This register manages the SR_MPU clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm_alwon_sr_iva_clkctrl addr(base, 0x30) "This register manages the SR_IVA clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
register cm_alwon_sr_core_clkctrl addr(base, 0x38) "This register manages the SR_CORE clocks." {
|
||||
_ 14 mbz;
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
constants optfclken_clk32k_status width(1) "" {
|
||||
OPTFCLKEN_CLK32K_0 = 0 "Optional functional clock is disabled";
|
||||
OPTFCLKEN_CLK32K_1 = 1 "Optional functional clock is enabled";
|
||||
};
|
||||
|
||||
register cm_alwon_usbphy_clkctrl addr(base, 0x40) "This register manages the USB PHY 32KHz clock." {
|
||||
_ 23 mbz;
|
||||
optfclken_clk32k 1 rw type(optfclken_clk32k_status) "Optional functional clock control.";
|
||||
_ 8 mbz;
|
||||
};
|
||||
};
|
||||
76
devices/omap/omap44xx_always_on_prm.dev
Normal file
76
devices/omap/omap44xx_always_on_prm.dev
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_always_on_prm.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_always_on_prm msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants wkupdep_sr_mpu_mpu_status width(1) "" {
|
||||
WKUPDEP_SR_MPU_MPU_1_r = 1 "Dependency is enabled";
|
||||
};
|
||||
|
||||
register pm_alwon_sr_mpu_wkdep addr(base, 0x28) "This register controls wakeup dependency based on SR_MPU service requests." {
|
||||
_ 31 mbz;
|
||||
wkupdep_sr_mpu_mpu 1 ro type(wkupdep_sr_mpu_mpu_status) "Wakeup dependency from SR_MPU module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
|
||||
};
|
||||
|
||||
constants lostcontext_dff_status width(1) "" {
|
||||
LOSTCONTEXT_DFF_0 = 0 "Context has been maintained";
|
||||
LOSTCONTEXT_DFF_1 = 1 "Context has been lost";
|
||||
};
|
||||
|
||||
register rm_alwon_sr_mpu_context addr(base, 0x2C) "This register contains dedicated SR_MPU context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostcontext_dff_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of Always_on_CORE_RST signal)";
|
||||
};
|
||||
|
||||
constants wkupdep_sr_iva_mpu_m3_status width(1) "" {
|
||||
WKUPDEP_SR_IVA_MPU_M3_0 = 0 "Dependency is disabled";
|
||||
WKUPDEP_SR_IVA_MPU_M3_1 = 1 "Dependency is enabled";
|
||||
};
|
||||
|
||||
register pm_alwon_sr_iva_wkdep addr(base, 0x30) "This register controls wakeup dependency based on SR_IVA service requests." {
|
||||
_ 30 mbz;
|
||||
wkupdep_sr_iva_mpu_m3 1 rw type(wkupdep_sr_iva_mpu_m3_status) "Wakeup dependency from SR_IVA module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
|
||||
wkupdep_sr_iva_mpu 1 rw type(wkupdep_sr_iva_mpu_m3_status) "Wakeup dependency from SR_IVA module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
|
||||
};
|
||||
|
||||
register rm_alwon_sr_iva_context addr(base, 0x34) "This register contains dedicated SR_IVA context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostcontext_dff_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of Always_on_CORE_RST signal)";
|
||||
};
|
||||
|
||||
register pm_alwon_sr_core_wkdep addr(base, 0x38) "This register controls wakeup dependency based on SR_CORE service requests." {
|
||||
_ 30 mbz;
|
||||
wkupdep_sr_core_mpu_m3 1 rw type(wkupdep_sr_iva_mpu_m3_status) "Wakeup dependency from SR_CORE module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains";
|
||||
wkupdep_sr_core_mpu 1 rw type(wkupdep_sr_iva_mpu_m3_status) "Wakeup dependency from SR_CORE module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains";
|
||||
};
|
||||
|
||||
register rm_alwon_sr_core_context addr(base, 0x3C) "This register contains dedicated SR_CORE context statuses. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostcontext_dff_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of Always_on_CORE_RST signal)";
|
||||
};
|
||||
};
|
||||
21
devices/omap/omap44xx_boot.dev
Normal file
21
devices/omap/omap44xx_boot.dev
Normal file
@ -0,0 +1,21 @@
|
||||
/* See OMAP4460 TRM S27.4.5. */
|
||||
device omap44xx_boot msbfirst () "OMAP44xx Peripheral Boot Messages" {
|
||||
|
||||
constants boot_msg "Booting Messages" {
|
||||
periph_boot = 0xF0030002 "Continue peripherial booting";
|
||||
get_asic_id = 0xF0030003 "Request ASIC ID";
|
||||
/* Change device requests. */
|
||||
chdev_void = 0xF0030006 "Void, no device";
|
||||
chdev_xip = 0xF0030106 "Switch to XIP memory";
|
||||
chdev_xipwait = 0xF0030206 "Switch to XIP memory, monitor wait signal";
|
||||
chdev_nand = 0xF0030306 "Switch to NAND";
|
||||
chdev_onenand = 0xF0030406 "Switch to OneNAND";
|
||||
chdev_mmc1 = 0xF0030506 "Switch to MMC1";
|
||||
chdev_mmc2_1 = 0xF0030606 "Switch to MMC2(1)";
|
||||
chdev_mmc2_2 = 0xF0030706 "Switch to MMC2(2)";
|
||||
chdev_uart3 = 0xF0034306 "Switch to UART3";
|
||||
chdev_usb1 = 0xF0034506 "Switch to USB(1) (internal transceiver)";
|
||||
chdev_ulpi = 0xF0034606 "Switch to USB-ULPI";
|
||||
chdev_usb2 = 0xF0034706 "Switch to USB(2) (internal transceiver)";
|
||||
};
|
||||
};
|
||||
454
devices/omap/omap44xx_c2c.dev
Normal file
454
devices/omap/omap44xx_c2c.dev
Normal file
@ -0,0 +1,454 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_c2c.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_c2c msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
register c2c_revision ro addr(base, 0x0) "IP Revision identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32);
|
||||
|
||||
register c2c_sysconfig ro addr(base, 0x4) "System configuration register (not used)" type(uint32);
|
||||
|
||||
register c2c_sysstatus ro addr(base, 0x8) "Reserved" type(uint32);
|
||||
|
||||
constants rx_width_status width(4) "" {
|
||||
RX_WIDTH_1 = 1 "Bus width is set to 10 bits (possible only if TX = 8).";
|
||||
RX_WIDTH_10 = 10 "Bus width is set to 16 bits.";
|
||||
};
|
||||
|
||||
constants tx_width_status width(4) "" {
|
||||
TX_WIDTH_1 = 1 "Bus width is set to 10 bits (possible only if RX = 8).";
|
||||
TX_WIDTH_10 = 10 "Bus width is set to 16 bits (default mode).";
|
||||
};
|
||||
|
||||
register c2c_portconfig addr(base, 0xC) "This register defines the widths of the TX and RX buses on the C2C interface." {
|
||||
_ 24 mbz;
|
||||
rx_width 4 rw type(rx_width_status) "0000: Bus width is set to 8 bits (default mode).Other values are reserved, and should not be used. .";
|
||||
tx_width 4 rw type(tx_width_status) "0000: Bus width is set to 8 bits.Other values are reserved, and shall not be used. .";
|
||||
};
|
||||
|
||||
constants mirrormode_status width(1) "" {
|
||||
MIRRORMODE_0 = 0 "Functional default mode";
|
||||
MIRRORMODE_1 = 1 "Mirror mode for debug";
|
||||
};
|
||||
|
||||
register c2c_mirrormode addr(base, 0x10) "This register sets the C2C L3 in mirror mode. See debug section." {
|
||||
_ 31 mbz;
|
||||
mirrormode 1 rw type(mirrormode_status) "Mirror mode.";
|
||||
};
|
||||
|
||||
register c2c_irq_raw_status_0 addr(base, 0x14) "Interrupt status register (OCP-compliant IRQ line) for C2c_Sscm_Irq(0), regardless of enable settings" {
|
||||
_ 28 mbz;
|
||||
wait_irq 1 rw "Reading 1 indicates WAIT value in WAIT register has been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
wake_ack_irq 1 rw "Reading 1 indicates WAKE_ACK value in the WAKE_ACK register has been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
rx_max_freq_ack_irq 1 rw "Reading 1 indicates GPI is not turned on OR RX_MAX_FREQ_ACK value in the RX_MAX_FREQ_ACK register equal RX_MAX_FREQ value in the RX_MAX_FREQ register.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
tx_freq_irq 1 rw "Reading 1 indicates that the FCLK_FREQ value in the FCLK_FREQ register has been updated AND the SSCM has finished updating the new division for the TX clock.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
};
|
||||
|
||||
register c2c_irq_raw_status_1 addr(base, 0x18) "" {
|
||||
geno_irq_31 1 rw "Reading 1 indicates C2c_Sscm_GENO (31) signal and GENO_31 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_30 1 rw "Reading 1 indicates C2c_Sscm_GENO (30) signal and GENO_30 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_29 1 rw "Reading 1 indicates C2c_Sscm_GENO (29) signal and GENO_29 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_28 1 rw "Reading 1 indicates C2c_Sscm_GENO (28) signal and GENO_28 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_27 1 rw "Reading 1 indicates C2c_Sscm_GENO (27) signal and GENO_27 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_26 1 rw "Reading 1 indicates C2c_Sscm_GENO (26) signal and GENO_26 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_25 1 rw "Reading 1 indicates C2c_Sscm_GENO (25) signal and GENO_25 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_24 1 rw "Reading 1 indicates C2c_Sscm_GENO (24) signal and GENO_24 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_23 1 rw "Reading 1 indicates C2c_Sscm_GENO (23) signal and GENO_23 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_22 1 rw "Reading 1 indicates C2c_Sscm_GENO (22) signal and GENO_22 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_21 1 rw "Reading 1 indicates C2c_Sscm_GENO (21) signal and GENO_21 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_20 1 rw "Reading 1 indicates C2c_Sscm_GENO (20) signal and GENO_20 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_19 1 rw "Reading 1 indicates C2c_Sscm_GENO (19) signal and GENO_19 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_18 1 rw "Reading 1 indicates C2c_Sscm_GENO (18) signal and GENO_18 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_17 1 rw "Reading 1 indicates C2c_Sscm_GENO (17) signal and GENO_17 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_16 1 rw "Reading 1 indicates C2c_Sscm_GENO (16) signal and GENO_16 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_15 1 rw "Reading 1 indicates C2c_Sscm_GENO (15) signal and GENO_15 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_14 1 rw "Reading 1 indicates C2c_Sscm_GENO (14) signal and GENO_14 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_13 1 rw "Reading 1 indicates C2c_Sscm_GENO (13) signal and GENO_13 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_12 1 rw "Reading 1 indicates C2c_Sscm_GENO (12) signal and GENO_12 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_11 1 rw "Reading 1 indicates C2c_Sscm_GENO (11) signal and GENO_11 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_10 1 rw "Reading 1 indicates C2c_Sscm_GENO (10) signal and GENO_10 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_9 1 rw "Reading 1 indicates C2c_Sscm_GENO (9) signal and GENO_9 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_8 1 rw "Reading 1 indicates C2c_Sscm_GENO (8) signal and GENO_8 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_7 1 rw "Reading 1 indicates C2c_Sscm_GENO (7) signal and GENO_7 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_6 1 rw "Reading 1 indicates C2c_Sscm_GENO (6) signal and GENO_6 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_5 1 rw "Reading 1 indicates C2c_Sscm_GENO (5) signal and GENO_5 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_4 1 rw "Reading 1 indicates C2c_Sscm_GENO (4) signal and GENO_4 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_3 1 rw "Reading 1 indicates C2c_Sscm_GENO (3) signal and GENO_3 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_2 1 rw "Reading 1 indicates C2c_Sscm_GENO (2) signal and GENO_2 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_1 1 rw "Reading 1 indicates C2c_Sscm_GENO (1) signal and GENO_1 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
geno_irq_0 1 rw "Reading 1 indicates C2c_Sscm_GENO (0) signal and GENO_0 value in GENO_STATUS register have been modified by distant C2C.Writing 1 to this bit sets the bit. . Writing 0 has no effect. .";
|
||||
};
|
||||
|
||||
register c2c_irq_enable_status_0 addr(base, 0x1C) "" {
|
||||
_ 28 mbz;
|
||||
wait_irq 1 rw1c "Reading 1 indicates WAIT value in WAIT register has been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
wake_ack_irq 1 rw1c "Reading 1 indicates WAKE_ACK value in the WAKE_ACK register has been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
rx_max_freq_ack_irq 1 rw1c "Reading 1 indicates GPI is not turned on OR RX_MAX_FREQ_ACK value in the RX_MAX_FREQ_ACK register equal RX_MAX_FREQ value in the RX_MAX_FREQ register.";
|
||||
tx_freq_irq 1 rw1c "Reading 1 indicates that the FCLK_FREQ value in the FCLK_FREQ register has been updated AND the SSCM has finished updating the new division for the Tx clock.";
|
||||
};
|
||||
|
||||
register c2c_irq_enable_status_1 addr(base, 0x20) "" {
|
||||
geno_irq_31 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (31) signal and GENO_31 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_30 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (30) signal and GENO_30 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_29 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (29) signal and GENO_29 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_28 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (28) signal and GENO_28 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_27 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (27) signal and GENO_27 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_26 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (26) signal and GENO_26 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_25 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (25) signal and GENO_25 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_24 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (24) signal and GENO_24 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_23 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (23) signal and GENO_23 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_22 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (22) signal and GENO_22 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_21 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (21) signal and GENO_21 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_20 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (20) signal and GENO_20 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_19 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (19) signal and GENO_19 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_18 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (18) signal and GENO_18 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_17 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (17) signal and GENO_17 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_16 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (16) signal and GENO_16 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_15 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (15) signal and GENO_15 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_14 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (14) signal and GENO_14 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_13 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (13) signal and GENO_13 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_12 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (12) signal and GENO_12 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_11 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (11) signal and GENO_11 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_10 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (10) signal and GENO_10 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_9 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (9) signal and GENO_9 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_8 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (8) signal and GENO_8 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_7 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (7) signal and GENO_7 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_6 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (6) signal and GENO_6 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_5 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (5) signal and GENO_5 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_4 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (4) signal and GENO_4 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_3 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (3) signal and GENO_3 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_2 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (2) signal and GENO_2 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_1 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (1) signal and GENO_1 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_0 1 rw1c "Reading 1 indicates C2c_Sscm_GENO (0) signal and GENO_0 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
};
|
||||
|
||||
register c2c_irq_enable_set_0 addr(base, 0x24) "" {
|
||||
_ 28 mbz;
|
||||
wait_irq_en 1 rw "Interrupt enable for WAIT IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect.";
|
||||
wake_ack_irq_en 1 rw "Interrupt enable for WAKE_ACK IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect.";
|
||||
rx_max_freq_ack_irq_en 1 rw "Interrupt enable for RX_MAX_FREQ_ACK IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect.";
|
||||
tx_freq_irq_en 1 rw "Interrupt enable for TX_FREQ IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect.";
|
||||
};
|
||||
|
||||
register c2c_irq_enable_set_1 addr(base, 0x28) "" {
|
||||
geno_irq_31_en 1 rw "Interrupt enable for GENO_IRQ_31 IRQ.";
|
||||
geno_irq_30_en 1 rw "Interrupt enable for GENO_IRQ_30 IRQ.";
|
||||
geno_irq_29_en 1 rw "Interrupt enable for GENO_IRQ_29 IRQ.";
|
||||
geno_irq_28_en 1 rw "Interrupt enable for GENO_IRQ_28 IRQ.";
|
||||
geno_irq_27_en 1 rw "Interrupt enable for GENO_IRQ_27 IRQ.";
|
||||
geno_irq_26_en 1 rw "Interrupt enable for GENO_IRQ_26 IRQ.";
|
||||
geno_irq_25_en 1 rw "Interrupt enable for GENO_IRQ_25 IRQ.";
|
||||
geno_irq_24_en 1 rw "Interrupt enable for GENO_IRQ_24 IRQ.";
|
||||
geno_irq_23_en 1 rw "Interrupt enable for GENO_IRQ_23 IRQ.";
|
||||
geno_irq_22_en 1 rw "Interrupt enable for GENO_IRQ_22 IRQ.";
|
||||
geno_irq_21_en 1 rw "Interrupt enable for GENO_IRQ_21 IRQ.";
|
||||
geno_irq_20_en 1 rw "Interrupt enable for GENO_IRQ_20 IRQ.";
|
||||
geno_irq_19_en 1 rw "Interrupt enable for GENO_IRQ_19 IRQ.";
|
||||
geno_irq_18_en 1 rw "Interrupt enable for GENO_IRQ_18 IRQ.";
|
||||
geno_irq_17_en 1 rw "Interrupt enable for GENO_IRQ_17 IRQ.";
|
||||
geno_irq_16_en 1 rw "Interrupt enable for GENO_IRQ_16 IRQ.";
|
||||
geno_irq_15_en 1 rw "Interrupt enable for GENO_IRQ_15 IRQ.";
|
||||
geno_irq_14_en 1 rw "Interrupt enable for GENO_IRQ_14 IRQ.";
|
||||
geno_irq_13_en 1 rw "Interrupt enable for GENO_IRQ_13 IRQ.";
|
||||
geno_irq_12_en 1 rw "Interrupt enable for GENO_IRQ_12 IRQ.";
|
||||
geno_irq_11_en 1 rw "Interrupt enable for GENO_IRQ_11 IRQ.";
|
||||
geno_irq_10_en 1 rw "Interrupt enable for GENO_IRQ_10 IRQ.";
|
||||
geno_irq_9_en 1 rw "Interrupt enable for GENO_IRQ_9 IRQ.";
|
||||
geno_irq_8_en 1 rw "Interrupt enable for GENO_IRQ_8 IRQ.";
|
||||
geno_irq_7_en 1 rw "Interrupt enable for GENO_IRQ_7 IRQ.";
|
||||
geno_irq_6_en 1 rw "Interrupt enable for GENO_IRQ_6 IRQ.";
|
||||
geno_irq_5_en 1 rw "Interrupt enable for GENO_IRQ_5 IRQ.";
|
||||
geno_irq_4_en 1 rw "Interrupt enable for GENO_IRQ_4 IRQ.";
|
||||
geno_irq_3_en 1 rw "Interrupt enable for GENO_IRQ_3 IRQ.";
|
||||
geno_irq_2_en 1 rw "Interrupt enable for GENO_IRQ_2 IRQ.";
|
||||
geno_irq_1_en 1 rw "Interrupt enable for GENO_IRQ_1 IRQ.";
|
||||
geno_irq_0_en 1 rw "Interrupt enable for GENO_IRQ_0 IRQ.";
|
||||
};
|
||||
|
||||
register c2c_irq_enable_clear_0 addr(base, 0x2C) "" {
|
||||
_ 28 mbz;
|
||||
wait_irq_en 1 rw1c "Interrupt enable for WAIT IRQ.";
|
||||
wake_ack_irq_en 1 rw1c "Interrupt enable for WAKE_ACK IRQ.";
|
||||
rx_max_freq_ack_irq_en 1 rw1c "Interrupt enable for RX_MAX_FREQ_ACK IRQ.";
|
||||
tx_freq_irq_en 1 rw1c "Interrupt enable for TX_FREQ IRQ.";
|
||||
};
|
||||
|
||||
register c2c_irq_enable_clear_1 addr(base, 0x30) "" {
|
||||
geno_irq_31_en 1 rw1c "Interrupt enable for GENO_IRQ_31 IRQ. Writing 1 to this bit clears the bit. Writing 0 has no effect.";
|
||||
geno_irq_30_en 1 rw1c "Interrupt enable for GENO_IRQ_30 IRQ.";
|
||||
geno_irq_29_en 1 rw1c "Interrupt enable for GENO_IRQ_29 IRQ.";
|
||||
geno_irq_28_en 1 rw1c "Interrupt enable for GENO_IRQ_28 IRQ.";
|
||||
geno_irq_27_en 1 rw1c "Interrupt enable for GENO_IRQ_27 IRQ.";
|
||||
geno_irq_26_en 1 rw1c "Interrupt enable for GENO_IRQ_26 IRQ.";
|
||||
geno_irq_25_en 1 rw1c "Interrupt enable for GENO_IRQ_25 IRQ.";
|
||||
geno_irq_24_en 1 rw1c "Interrupt enable for GENO_IRQ_24 IRQ.";
|
||||
geno_irq_23_en 1 rw1c "Interrupt enable for GENO_IRQ_23 IRQ.";
|
||||
geno_irq_22_en 1 rw1c "Interrupt enable for GENO_IRQ_22 IRQ.";
|
||||
geno_irq_21_en 1 rw1c "Interrupt enable for GENO_IRQ_21 IRQ.";
|
||||
geno_irq_20_en 1 rw1c "Interrupt enable for GENO_IRQ_20 IRQ.";
|
||||
geno_irq_19_en 1 rw1c "Interrupt enable for GENO_IRQ_19 IRQ.";
|
||||
geno_irq_18_en 1 rw1c "Interrupt enable for GENO_IRQ_18 IRQ.";
|
||||
geno_irq_17_en 1 rw1c "Interrupt enable for GENO_IRQ_17 IRQ.";
|
||||
geno_irq_16_en 1 rw1c "Interrupt enable for GENO_IRQ_16 IRQ.";
|
||||
geno_irq_15_en 1 rw1c "Interrupt enable for GENO_IRQ_15 IRQ.";
|
||||
geno_irq_14_en 1 rw1c "Interrupt enable for GENO_IRQ_14 IRQ.";
|
||||
geno_irq_13_en 1 rw1c "Interrupt enable for GENO_IRQ_13 IRQ.";
|
||||
geno_irq_12_en 1 rw1c "Interrupt enable for GENO_IRQ_12 IRQ.";
|
||||
geno_irq_11_en 1 rw1c "Interrupt enable for GENO_IRQ_11 IRQ.";
|
||||
geno_irq_10_en 1 rw1c "Interrupt enable for GENO_IRQ_10 IRQ.";
|
||||
geno_irq_9_en 1 rw1c "Interrupt enable for GENO_IRQ_9 IRQ.";
|
||||
geno_irq_8_en 1 rw1c "Interrupt enable for GENO_IRQ_8 IRQ.";
|
||||
geno_irq_7_en 1 rw1c "Interrupt enable for GENO_IRQ_7 IRQ.";
|
||||
geno_irq_6_en 1 rw1c "Interrupt enable for GENO_IRQ_6 IRQ.";
|
||||
geno_irq_5_en 1 rw1c "Interrupt enable for GENO_IRQ_5 IRQ.";
|
||||
geno_irq_4_en 1 rw1c "Interrupt enable for GENO_IRQ_4 IRQ.";
|
||||
geno_irq_3_en 1 rw1c "Interrupt enable for GENO_IRQ_3 IRQ.";
|
||||
geno_irq_2_en 1 rw1c "Interrupt enable for GENO_IRQ_2 IRQ.";
|
||||
geno_irq_1_en 1 rw1c "Interrupt enable for GENO_IRQ_1 IRQ.";
|
||||
geno_irq_0_en 1 rw1c "Interrupt enable for GENO_IRQ_0 IRQ.";
|
||||
};
|
||||
|
||||
register c2c_fclk_freq addr(base, 0x40) "" {
|
||||
_ 22 mbz;
|
||||
fclk_freq 10 rw "Value of the Functional clock frequency according to OPP written by software. Default value is 400 (MHz).";
|
||||
};
|
||||
|
||||
register c2c_rx_max_freq addr(base, 0x44) "" {
|
||||
_ 22 mbz;
|
||||
rx_max_freq 10 rw "Value of the requested RX maximum clock frequency according to OPP written by software. Default value is 50 (MHz).";
|
||||
};
|
||||
|
||||
register c2c_tx_max_freq addr(base, 0x48) "" {
|
||||
_ 22 mbz;
|
||||
tx_max_freq 10 rw "Value of the requested TX maximum clock frequency set by distant C2C. Default value is 50 (MHz).";
|
||||
};
|
||||
|
||||
register c2c_rx_max_freq_ack addr(base, 0x4C) "" {
|
||||
_ 22 mbz;
|
||||
rx_max_freq_ack 10 rw "Acknowledged maximum Rx clock frequency. Set by distant C2C. Default value is 50 (MHz).";
|
||||
};
|
||||
|
||||
register c2c_wake_req addr(base, 0x50) "" {
|
||||
_ 31 mbz;
|
||||
wake_req 1 rw "Value of the WAKE_REQ set by software";
|
||||
};
|
||||
|
||||
register c2c_wake_ack addr(base, 0x54) "" {
|
||||
_ 31 mbz;
|
||||
wake_ack 1 rw "Value of the WAKE_ACK set by distant C2C";
|
||||
};
|
||||
|
||||
register c2c_standby addr(base, 0x60) "" {
|
||||
_ 31 mbz;
|
||||
standby 1 rw "Value of the STANDBY set by software";
|
||||
};
|
||||
|
||||
register c2c_standby_in addr(base, 0x64) "" {
|
||||
_ 31 mbz;
|
||||
standby 1 rw "Value of the STANDBY set by distant C2C";
|
||||
};
|
||||
|
||||
register c2c_wait addr(base, 0x68) "" {
|
||||
_ 31 mbz;
|
||||
wait 1 rw "Value of the WAIT set by distant C2C";
|
||||
};
|
||||
|
||||
register c2c_geni_control addr(base, 0x70) "" {
|
||||
geni_31 1 rw "If GENI_MASK_31 in GENI_MASK register is reset, GENI_31 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked) If GENI_MASK_31 is set (signal is masked), GENI_31 can be modified by software.";
|
||||
geni_30 1 rw "f GENI_MASK_30 in GENI_MASK register is reset, GENI_30 is the value of C2C_Sscm_GenI_30 and cannot be modified by software. (signal is not masked) If GENI_MASK_30 is set (signal is masked), GENI_30 can be modified by software.";
|
||||
geni_29 1 rw "f GENI_MASK_29 in GENI_MASK register is reset, GENI_29 is the value of C2C_Sscm_GenI_29 and cannot be modified by software. (signal is not masked) If GENI_MASK_29 is set (signal is masked), GENI_29 can be modified by software.";
|
||||
geni_28 1 rw "f GENI_MASK_28 in GENI_MASK register is reset, GENI_28 is the value of C2C_Sscm_GenI_28 and cannot be modified by software. (signal is not masked) If GENI_MASK_28 is set (signal is masked), GENI_28 can be modified by software.";
|
||||
geni_27 1 rw "f GENI_MASK_27 in GENI_MASK register is reset, GENI_27 is the value of C2C_Sscm_GenI_27 and cannot be modified by software. (signal is not masked) If GENI_MASK_27 is set (signal is masked), GENI_27 can be modified by software.";
|
||||
geni_26 1 rw "f GENI_MASK_26 in GENI_MASK register is reset, GENI_26 is the value of C2C_Sscm_GenI_26 and cannot be modified by software. (signal is not masked) If GENI_MASK_26 is set (signal is masked), GENI_26 can be modified by software.";
|
||||
geni_25 1 rw "f GENI_MASK_25 in GENI_MASK register is reset, GENI_25 is the value of C2C_Sscm_GenI_25 and cannot be modified by software. (signal is not masked) If GENI_MASK_25 is set (signal is masked), GENI_25 can be modified by software.";
|
||||
geni_24 1 rw "f GENI_MASK_24 in GENI_MASK register is reset, GENI_24 is the value of C2C_Sscm_GenI_24 and cannot be modified by software. (signal is not masked) If GENI_MASK_24 is set (signal is masked), GENI_24 can be modified by software.";
|
||||
geni_23 1 rw "f GENI_MASK_23 in GENI_MASK register is reset, GENI_23 is the value of C2C_Sscm_GenI_23 and cannot be modified by software. (signal is not masked) If GENI_MASK_23 is set (signal is masked), GENI_23 can be modified by software.";
|
||||
geni_22 1 rw "f GENI_MASK_22 in GENI_MASK register is reset, GENI_22 is the value of C2C_Sscm_GenI_22 and cannot be modified by software. (signal is not masked) If GENI_MASK_22 is set (signal is masked), GENI_22 can be modified by software.";
|
||||
geni_21 1 rw "f GENI_MASK_21 in GENI_MASK register is reset, GENI_21 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked) If GENI_MASK_21 is set (signal is masked), GENI_21 can be modified by software.";
|
||||
geni_20 1 rw "f GENI_MASK_20 in GENI_MASK register is reset, GENI_20 is the value of C2C_Sscm_GenI_20 and cannot be modified by software. (signal is not masked) If GENI_MASK_20 is set (signal is masked), GENI_20 can be modified by software.";
|
||||
geni_19 1 rw "f GENI_MASK_19 in GENI_MASK register is reset, GENI_19 is the value of C2C_Sscm_GenI_19 and cannot be modified by software. (signal is not masked) If GENI_MASK_19 is set (signal is masked), GENI_19 can be modified by software.";
|
||||
geni_18 1 rw "f GENI_MASK_18 in GENI_MASK register is reset, GENI_18 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked) If GENI_MASK_18 is set (signal is masked), GENI_18 can be modified by software.";
|
||||
geni_17 1 rw "f GENI_MASK_17 in GENI_MASK register is reset, GENI_17 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked) If GENI_MASK_17 is set (signal is masked), GENI_17 can be modified by software.";
|
||||
geni_16 1 rw "f GENI_MASK_16 in GENI_MASK register is reset, GENI_16 is the value of C2C_Sscm_GenI_16 and cannot be modified by software. (signal is not masked) If GENI_MASK_156is set (signal is masked), GENI_16 can be modified by software.";
|
||||
geni_15 1 rw "f GENI_MASK_15 in GENI_MASK register is reset, GENI_15 is the value of C2C_Sscm_GenI_15 and cannot be modified by software. (signal is not masked) If GENI_MASK_15 is set (signal is masked), GENI_15 can be modified by software.";
|
||||
geni_14 1 rw "f GENI_MASK_14 in GENI_MASK register is reset, GENI_14 is the value of C2C_Sscm_GenI_14 and cannot be modified by software. (signal is not masked) If GENI_MASK_14 is set (signal is masked), GENI_14 can be modified by software.";
|
||||
geni_13 1 rw "f GENI_MASK_13 in GENI_MASK register is reset, GENI_13 is the value of C2C_Sscm_GenI_13 and cannot be modified by software. (signal is not masked) If GENI_MASK_13 is set (signal is masked), GENI_13 can be modified by software.";
|
||||
geni_12 1 rw "f GENI_MASK_12 in GENI_MASK register is reset, GENI_12 is the value of C2C_Sscm_GenI_12 and cannot be modified by software. (signal is not masked) If GENI_MASK_12 is set (signal is masked), GENI_12 can be modified by software.";
|
||||
geni_11 1 rw "f GENI_MASK_11 in GENI_MASK register is reset, GENI_11 is the value of C2C_Sscm_GenI_11 and cannot be modified by software. (signal is not masked) If GENI_MASK_11 is set (signal is masked), GENI_11 can be modified by software.";
|
||||
geni_10 1 rw "f GENI_MASK_10 in GENI_MASK register is reset, GENI_10 is the value of C2C_Sscm_GenI_10 and cannot be modified by software. (signal is not masked) If GENI_MASK_10 is set (signal is masked), GENI_10 can be modified by software.";
|
||||
geni_9 1 rw "f GENI_MASK_9 in GENI_MASK register is reset, GENI_9 is the value of C2C_Sscm_GenI_9 and cannot be modified by software. (signal is not masked) If GENI_MASK_9 is set (signal is masked), GENI_9 can be modified by software.";
|
||||
geni_8 1 rw "f GENI_MASK_8 in GENI_MASK register is reset, GENI_8 is the value of C2C_Sscm_GenI_8 and cannot be modified by software. (signal is not masked) If GENI_MASK_8 is set (signal is masked), GENI_8 can be modified by software.";
|
||||
geni_7 1 rw "f GENI_MASK_7 in GENI_MASK register is reset, GENI_7 is the value of C2C_Sscm_GenI_7 and cannot be modified by software. (signal is not masked) If GENI_MASK_7 is set (signal is masked), GENI_7 can be modified by software.";
|
||||
geni_6 1 rw "f GENI_MASK_6 in GENI_MASK register is reset, GENI_6 is the value of C2C_Sscm_GenI_6 and cannot be modified by software. (signal is not masked) If GENI_MASK_6 is set (signal is masked), GENI_6 can be modified by software.";
|
||||
geni_5 1 rw "f GENI_MASK_5 in GENI_MASK register is reset, GENI_5 is the value of C2C_Sscm_GenI_5 and cannot be modified by software. (signal is not masked) If GENI_MASK_5 is set (signal is masked), GENI_5 can be modified by software.";
|
||||
geni_4 1 rw "f GENI_MASK_4 in GENI_MASK register is reset, GENI_4 is the value of C2C_Sscm_GenI_4 and cannot be modified by software. (signal is not masked) If GENI_MASK_4 is set (signal is masked), GENI_4 can be modified by software.";
|
||||
geni_3 1 rw "f GENI_MASK_3 in GENI_MASK register is reset, GENI_3 is the value of C2C_Sscm_GenI_3 and cannot be modified by software. (signal is not masked) If GENI_MASK_3 is set (signal is masked), GENI_3 can be modified by software.";
|
||||
geni_2 1 rw "f GENI_MASK_2 in GENI_MASK register is reset, GENI_2 is the value of C2C_Sscm_GenI_2 and cannot be modified by software. (signal is not masked) If GENI_MASK_2 is set (signal is masked), GENI_2 can be modified by software.";
|
||||
geni_1 1 rw "f GENI_MASK_1 in GENI_MASK register is reset, GENI_1 is the value of C2C_Sscm_GenI_1 and cannot be modified by software. (signal is not masked) If GENI_MASK_1 is set (signal is masked), GENI_1 can be modified by software.";
|
||||
geni_0 1 rw "f GENI_MASK_0 in GENI_MASK register is reset, GENI_0 is the value of C2C_Sscm_GenI_0 and cannot be modified by software. (signal is not masked) If GENI_MASK_0 is set (signal is masked), GENI_0 can be modified by software.";
|
||||
};
|
||||
|
||||
register c2c_geni_mask addr(base, 0x74) "" {
|
||||
geni_mask_31 1 rw "If GENI_MASK_31 is reset, C2C_Sscm_GenI_31 signal is not masked If GENI_MASK_31 is set, signal is masked.";
|
||||
geni_mask_30 1 rw "If GENI_MASK_30 is reset, C2C_Sscm_GenI_30 signal is not masked If GENI_MASK_30 is set, signal is masked.";
|
||||
geni_mask_29 1 rw "If GENI_MASK_29 is reset, C2C_Sscm_GenI_29 signal is not masked If GENI_MASK_29 is set, signal is masked.";
|
||||
geni_mask_28 1 rw "If GENI_MASK_28 is reset, C2C_Sscm_GenI_28 signal is not masked If GENI_MASK_28 is set, signal is masked.";
|
||||
geni_mask_27 1 rw "If GENI_MASK_27 is reset, C2C_Sscm_GenI_27 signal is not masked If GENI_MASK_27 is set, signal is masked.";
|
||||
geni_mask_26 1 rw "If GENI_MASK_26 is reset, C2C_Sscm_GenI_26 signal is not masked If GENI_MASK_26 is set, signal is masked.";
|
||||
geni_mask_25 1 rw "If GENI_MASK_26 is reset, C2C_Sscm_GenI_25 signal is not masked If GENI_MASK_26 is set, signal is masked.";
|
||||
geni_mask_24 1 rw "If GENI_MASK_24 is reset, C2C_Sscm_GenI_24 signal is not masked If GENI_MASK_24 is set, signal is masked.";
|
||||
geni_mask_23 1 rw "If GENI_MASK_23 is reset, C2C_Sscm_GenI_23 signal is not masked If GENI_MASK_23 is set, signal is masked.";
|
||||
geni_mask_22 1 rw "If GENI_MASK_22 is reset, C2C_Sscm_GenI_22 signal is not masked If GENI_MASK_22 is set, signal is masked.";
|
||||
geni_mask_21 1 rw "If GENI_MASK_21 is reset, C2C_Sscm_GenI_21 signal is not masked If GENI_MASK_21 is set, signal is masked.";
|
||||
geni_mask_20 1 rw "If GENI_MASK_20 is reset, C2C_Sscm_GenI_20 signal is not masked If GENI_MASK_20 is set, signal is masked.";
|
||||
geni_mask_19 1 rw "If GENI_MASK_19 is reset, C2C_Sscm_GenI_19 signal is not masked If GENI_MASK_19 is set, signal is masked.";
|
||||
geni_mask_18 1 rw "If GENI_MASK_18 is reset, C2C_Sscm_GenI_18 signal is not masked If GENI_MASK_18 is set, signal is masked.";
|
||||
geni_mask_17 1 rw "If GENI_MASK_17 is reset, C2C_Sscm_GenI_17 signal is not masked If GENI_MASK_17 is set, signal is masked.";
|
||||
geni_mask_16 1 rw "If GENI_MASK_16 is reset, C2C_Sscm_GenI_16 signal is not masked If GENI_MASK_16 is set, signal is masked.";
|
||||
geni_mask_15 1 rw "If GENI_MASK_15 is reset, C2C_Sscm_GenI_15 signal is not masked If GENI_MASK_15 is set, signal is masked.";
|
||||
geni_mask_14 1 rw "If GENI_MASK_14 is reset, C2C_Sscm_GenI_14 signal is not masked If GENI_MASK_14 is set, signal is masked.";
|
||||
geni_mask_13 1 rw "If GENI_MASK_13 is reset, C2C_Sscm_GenI_13 signal is not masked If GENI_MASK_13 is set, signal is masked.";
|
||||
geni_mask_12 1 rw "If GENI_MASK_12is reset, C2C_Sscm_GenI_12 signal is not masked If GENI_MASK_12 is set, signal is masked.";
|
||||
geni_mask_11 1 rw "If GENI_MASK_11 is reset, C2C_Sscm_GenI_11 signal is not masked If GENI_MASK_11 is set, signal is masked.";
|
||||
geni_mask_10 1 rw "If GENI_MASK_10 is reset, C2C_Sscm_GenI_10 signal is not masked If GENI_MASK_10 is set, signal is masked.";
|
||||
geni_mask_9 1 rw "If GENI_MASK_9 is reset, C2C_Sscm_GenI_9 signal is not masked If GENI_MASK_9 is set, signal is masked.";
|
||||
geni_mask_8 1 rw "If GENI_MASK_8 is reset, C2C_Sscm_GenI_8 signal is not masked If GENI_MASK_8 is set, signal is masked.";
|
||||
geni_mask_7 1 rw "If GENI_MASK_7 is reset, C2C_Sscm_GenI_7 signal is not masked If GENI_MASK_7 is set, signal is masked.";
|
||||
geni_mask_6 1 rw "If GENI_MASK_6 is reset, C2C_Sscm_GenI_6 signal is not masked If GENI_MASK_6 is set, signal is masked.";
|
||||
geni_mask_5 1 rw "If GENI_MASK_5 is reset, C2C_Sscm_GenI_5 signal is not masked If GENI_MASK_5 is set, signal is masked.";
|
||||
geni_mask_4 1 rw "If GENI_MASK_4 is reset, C2C_Sscm_GenI_4 signal is not masked If GENI_MASK_4 is set, signal is masked.";
|
||||
geni_mask_3 1 rw "If GENI_MASK_3 is reset, C2C_Sscm_GenI_3 signal is not masked If GENI_MASK_3 is set, signal is masked.";
|
||||
geni_mask_2 1 rw "If GENI_MASK_2 is reset, C2C_Sscm_GenI_2 signal is not masked If GENI_MASK_2 is set, signal is masked.";
|
||||
geni_mask_1 1 rw "If GENI_MASK_1 is reset, C2C_Sscm_GenI_1 signal is not masked If GENI_MASK_1 is set, signal is masked.";
|
||||
geni_mask_0 1 rw "If GENI_MASK_0 is reset, C2C_Sscm_GenI_0 signal is not masked If GENI_MASK_0 is set, signal is masked.";
|
||||
};
|
||||
|
||||
register c2c_geno_status addr(base, 0x80) "" {
|
||||
geno_31 1 rw "GENO_31 is the value of C2C_Sscm_GenO_31 signal.";
|
||||
geno_30 1 rw "GENO_30 is the value of C2C_Sscm_GenO_30 signal.";
|
||||
geno_29 1 rw "GENO_29 is the value of C2C_Sscm_GenO_29 signal.";
|
||||
geno_28 1 rw "GENO_28 is the value of C2C_Sscm_GenO_28 signal.";
|
||||
geno_27 1 rw "GENO_27 is the value of C2C_Sscm_GenO_27 signal.";
|
||||
geno_26 1 rw "GENO_26 is the value of C2C_Sscm_GenO_26 signal.";
|
||||
geno_25 1 rw "GENO_25 is the value of C2C_Sscm_GenO_25 signal.";
|
||||
geno_24 1 rw "GENO_24 is the value of C2C_Sscm_GenO_24 signal.";
|
||||
geno_23 1 rw "GENO_23 is the value of C2C_Sscm_GenO_23 signal.";
|
||||
geno_22 1 rw "GENO_22 is the value of C2C_Sscm_GenO_22 signal.";
|
||||
geno_21 1 rw "GENO_21 is the value of C2C_Sscm_GenO_21 signal.";
|
||||
geno_20 1 rw "GENO_20 is the value of C2C_Sscm_GenO_20 signal.";
|
||||
geno_19 1 rw "GENO_19 is the value of C2C_Sscm_GenO_19 signal.";
|
||||
geno_18 1 rw "GENO_18 is the value of C2C_Sscm_GenO_18 signal.";
|
||||
geno_17 1 rw "GENO_17 is the value of C2C_Sscm_GenO_17 signal.";
|
||||
geno_16 1 rw "GENO_16 is the value of C2C_Sscm_GenO_16 signal.";
|
||||
geno_15 1 rw "GENO_15 is the value of C2C_Sscm_GenO_15 signal.";
|
||||
geno_14 1 rw "GENO_14 is the value of C2C_Sscm_GenO_14 signal.";
|
||||
geno_13 1 rw "GENO_13 is the value of C2C_Sscm_GenO_13 signal.";
|
||||
geno_12 1 rw "GENO_12 is the value of C2C_Sscm_GenO_12 signal.";
|
||||
geno_11 1 rw "GENO_11 is the value of C2C_Sscm_GenO_11 signal.";
|
||||
geno_10 1 rw "GENO_10 is the value of C2C_Sscm_GenO_10 signal.";
|
||||
geno_9 1 rw "GENO_9 is the value of C2C_Sscm_GenO_9 signal.";
|
||||
geno_8 1 rw "GENO_8 is the value of C2C_Sscm_GenO_8 signal.";
|
||||
geno_7 1 rw "GENO_7 is the value of C2C_Sscm_GenO_7 signal.";
|
||||
geno_6 1 rw "GENO_6 is the value of C2C_Sscm_GenO_6 signal.";
|
||||
geno_5 1 rw "GENO_5 is the value of C2C_Sscm_GenO_5 signal.";
|
||||
geno_4 1 rw "GENO_4 is the value of C2C_Sscm_GenO_4 signal.";
|
||||
geno_3 1 rw "GENO_3 is the value of C2C_Sscm_GenO_3 signal.";
|
||||
geno_2 1 rw "GENO_2 is the value of C2C_Sscm_GenO_2 signal.";
|
||||
geno_1 1 rw "GENO_1 is the value of C2C_Sscm_GenO_1 signal.";
|
||||
geno_0 1 rw "GENO_0 is the value of C2C_Sscm_GenO_0 signal.";
|
||||
};
|
||||
|
||||
register c2c_geno_interrupt addr(base, 0x84) "" {
|
||||
geno_int_31 1 rw "If GENO_INT_31=0, GENO_IRQ_31=1 when GENO_31 toggles; If GENO_INT_31=1: IF GENO_LEVEL_31=0, GENO_IRQ_31 =1 when GENO_31 toggles to 0. IF GENO_LEVEL_31=1, GENO_IRQ_31 =1 when GENO_31 toggles to 1.";
|
||||
geno_int_30 1 rw "If GENO_INT_30=0, GENO_IRQ_30=1 when GENO_30 toggles; If GENO_INT_30=1: IF GENO_LEVEL_30=0, GENO_IRQ_30 =1 when GENO_30 toggles to 0. IF GENO_LEVEL_30=1, GENO_IRQ_30 =1 when GENO_30 toggles to 1.";
|
||||
geno_int_29 1 rw "If GENO_INT_29=0, GENO_IRQ_29=1 when GENO_29 toggles; If GENO_INT_29=1: IF GENO_LEVEL_29=0, GENO_IRQ_29 =1 when GENO_29 toggles to 0. IF GENO_LEVEL_29=1, GENO_IRQ_29 =1 when GENO_29 toggles to 1.";
|
||||
geno_int_28 1 rw "If GENO_INT_28=0, GENO_IRQ_28=1 when GENO_28 toggles; If GENO_INT_28=1: IF GENO_LEVEL_28=0, GENO_IRQ_28 =1 when GENO_28 toggles to 0. IF GENO_LEVEL_28=1, GENO_IRQ_28 =1 when GENO_28 toggles to 1.";
|
||||
geno_int_27 1 rw "If GENO_INT_27=0, GENO_IRQ_27=1 when GENO_27 toggles; If GENO_INT_27=1: IF GENO_LEVEL_27=0, GENO_IRQ_27 =1 when GENO_27 toggles to 0. IF GENO_LEVEL_27=1, GENO_IRQ_27 =1 when GENO_27 toggles to 1.";
|
||||
geno_int_26 1 rw "If GENO_INT_26=0, GENO_IRQ_26=1 when GENO_26 toggles; If GENO_INT_26=1: IF GENO_LEVEL_26=0, GENO_IRQ_26 =1 when GENO_26 toggles to 0. IF GENO_LEVEL_26=1, GENO_IRQ_26 =1 when GENO_26 toggles to 1.";
|
||||
geno_int_25 1 rw "If GENO_INT_25=0, GENO_IRQ_25=1 when GENO_25 toggles; If GENO_INT_25=1: IF GENO_LEVEL_25=0, GENO_IRQ_25 =1 when GENO_25 toggles to 0. IF GENO_LEVEL_25=1, GENO_IRQ_25 =1 when GENO_25 toggles to 1.";
|
||||
geno_int_24 1 rw "If GENO_INT_24=0, GENO_IRQ_24=1 when GENO_24 toggles; If GENO_INT_24=1: IF GENO_LEVEL_24=0, GENO_IRQ_24 =1 when GENO_24 toggles to 0. IF GENO_LEVEL_24=1, GENO_IRQ_24 =1 when GENO_24 toggles to 1.";
|
||||
geno_int_23 1 rw "If GENO_INT_23=0, GENO_IRQ_23=1 when GENO_23 toggles; If GENO_INT_23=1: IF GENO_LEVEL_23=0, GENO_IRQ_23 =1 when GENO_23 toggles to 0. IF GENO_LEVEL_23=1, GENO_IRQ_23 =1 when GENO_23 toggles to 1.";
|
||||
geno_int_22 1 rw "If GENO_INT_22=0, GENO_IRQ_22=1 when GENO_22 toggles; If GENO_INT_22=1: IF GENO_LEVEL_22=0, GENO_IRQ_22 =1 when GENO_22 toggles to 0. IF GENO_LEVEL_22=1, GENO_IRQ_22 =1 when GENO_22 toggles to 1.";
|
||||
geno_int_21 1 rw "If GENO_INT_21=0, GENO_IRQ_21=1 when GENO_21 toggles; If GENO_INT_21=1: IF GENO_LEVEL_21=0, GENO_IRQ_21 =1 when GENO_21 toggles to 0. IF GENO_LEVEL_21=1, GENO_IRQ_21 =1 when GENO_21 toggles to 1.";
|
||||
geno_int_20 1 rw "If GENO_INT_20=0, GENO_IRQ_20=1 when GENO_20 toggles; If GENO_INT_20=1: IF GENO_LEVEL_20=0, GENO_IRQ_20 =1 when GENO_20 toggles to 0. IF GENO_LEVEL_20=1, GENO_IRQ_20 =1 when GENO_20 toggles to 1.";
|
||||
geno_int_19 1 rw "If GENO_INT_19=0, GENO_IRQ_19=1 when GENO_19 toggles; If GENO_INT_19=1: IF GENO_LEVEL_19=0, GENO_IRQ_19 =1 when GENO_19 toggles to 0. IF GENO_LEVEL_19=1, GENO_IRQ_19 =1 when GENO_19 toggles to 1.";
|
||||
geno_int_18 1 rw "If GENO_INT_18=0, GENO_IRQ_18=1 when GENO_18 toggles; If GENO_INT_18=1: IF GENO_LEVEL_18=0, GENO_IRQ_18 =1 when GENO_18 toggles to 0. IF GENO_LEVEL_18=1, GENO_IRQ_18 =1 when GENO_18 toggles to 1.";
|
||||
geno_int_17 1 rw "If GENO_INT_17=0, GENO_IRQ_17=1 when GENO_17 toggles; If GENO_INT_17=1: IF GENO_LEVEL_17=0, GENO_IRQ_17 =1 when GENO_17 toggles to 0. IF GENO_LEVEL_17=1, GENO_IRQ_17 =1 when GENO_17 toggles to 1.";
|
||||
geno_int_16 1 rw "If GENO_INT_16=0, GENO_IRQ_16=1 when GENO_16 toggles; If GENO_INT_16=1: IF GENO_LEVEL_16=0, GENO_IRQ_16 =1 when GENO_16 toggles to 0. IF GENO_LEVEL_16=1, GENO_IRQ_16 =1 when GENO_16 toggles to 1.";
|
||||
geno_int_15 1 rw "If GENO_INT_15=0, GENO_IRQ_15=1 when GENO_15 toggles; If GENO_INT_15=1: IF GENO_LEVEL_15=0, GENO_IRQ_15 =1 when GENO_15 toggles to 0. IF GENO_LEVEL_15=1, GENO_IRQ_15 =1 when GENO_15 toggles to 1.";
|
||||
geno_int_14 1 rw "If GENO_INT_14=0, GENO_IRQ_14=1 when GENO_14 toggles; If GENO_INT_14=1: IF GENO_LEVEL_14=0, GENO_IRQ_14 =1 when GENO_14 toggles to 0. IF GENO_LEVEL_14=1, GENO_IRQ_14 =1 when GENO_14 toggles to 1.";
|
||||
geno_int_13 1 rw "If GENO_INT_13=0, GENO_IRQ_13=1 when GENO_13 toggles; If GENO_INT_13=1: IF GENO_LEVEL_13=0, GENO_IRQ_13 =1 when GENO_13 toggles to 0. IF GENO_LEVEL_13=1, GENO_IRQ_13 =1 when GENO_13 toggles to 1.";
|
||||
geno_int_12 1 rw "If GENO_INT_12=0, GENO_IRQ_12=1 when GENO_12 toggles; If GENO_INT_12=1: IF GENO_LEVEL_12=0, GENO_IRQ_12 =1 when GENO_12 toggles to 0. IF GENO_LEVEL_12=1, GENO_IRQ_12 =1 when GENO_12 toggles to 1.";
|
||||
geno_int_11 1 rw "If GENO_INT_11=0, GENO_IRQ_11=1 when GENO_11 toggles; If GENO_INT_11=1: IF GENO_LEVEL_11=0, GENO_IRQ_11 =1 when GENO_11 toggles to 0. IF GENO_LEVEL_11=1, GENO_IRQ_11 =1 when GENO_11 toggles to 1.";
|
||||
geno_int_10 1 rw "If GENO_INT_10=0, GENO_IRQ_10=1 when GENO_10 toggles; If GENO_INT_10=1: IF GENO_LEVEL_10=0, GENO_IRQ_10 =1 when GENO_10 toggles to 0. IF GENO_LEVEL_10=1, GENO_IRQ_10 =1 when GENO_10 toggles to 1.";
|
||||
geno_int_9 1 rw "If GENO_INT_9=0, GENO_IRQ_9=1 when GENO_9 toggles; If GENO_INT_9=1: IF GENO_LEVEL_9=0, GENO_IRQ_9 =1 when GENO_9 toggles to 0. IF GENO_LEVEL_9=1, GENO_IRQ_9 =1 when GENO_9 toggles to 1.";
|
||||
geno_int_8 1 rw "If GENO_INT_8=0, GENO_IRQ_8=1 when GENO_8 toggles; If GENO_INT_8=1: IF GENO_LEVEL_8=0, GENO_IRQ_8 =1 when GENO_8 toggles to 0. IF GENO_LEVEL_8=1, GENO_IRQ_8 =1 when GENO_8 toggles to 1.";
|
||||
geno_int_7 1 rw "If GENO_INT_7=0, GENO_IRQ_7=1 when GENO_7 toggles; If GENO_INT_7=1: IF GENO_LEVEL_7=0, GENO_IRQ_7 =1 when GENO_7 toggles to 0. IF GENO_LEVEL_7=1, GENO_IRQ_7 =1 when GENO_7 toggles to 1.";
|
||||
geno_int_6 1 rw "If GENO_INT_6=0, GENO_IRQ_6=1 when GENO_6 toggles; If GENO_INT_6=1: IF GENO_LEVEL_6=0, GENO_IRQ_6 =1 when GENO_6 toggles to 0. IF GENO_LEVEL_6=1, GENO_IRQ_6 =1 when GENO_6 toggles to 1.";
|
||||
geno_int_5 1 rw "If GENO_INT_5=0, GENO_IRQ_5=1 when GENO_5 toggles; If GENO_INT_5=1: IF GENO_LEVEL_5=0, GENO_IRQ_5 =1 when GENO_5 toggles to 0. IF GENO_LEVEL_5=1, GENO_IRQ_5 =1 when GENO_5 toggles to 1.";
|
||||
geno_int_4 1 rw "If GENO_INT_4=0, GENO_IRQ_4=1 when GENO_4 toggles; If GENO_INT_4=1: IF GENO_LEVEL_4=0, GENO_IRQ_4 =1 when GENO_4 toggles to 0. IF GENO_LEVEL_4=1, GENO_IRQ_4 =1 when GENO_4 toggles to 1.";
|
||||
geno_int_3 1 rw "If GENO_INT_3=0, GENO_IRQ_3=1 when GENO_3 toggles; If GENO_INT_3=1: IF GENO_LEVEL_3=0, GENO_IRQ_3 =1 when GENO_3 toggles to 0. IF GENO_LEVEL_3=1, GENO_IRQ_3 =1 when GENO_3 toggles to 1.";
|
||||
geno_int_2 1 rw "If GENO_INT_2=0, GENO_IRQ_2=1 when GENO_2 toggles; If GENO_INT_2=1: IF GENO_LEVEL_2=0, GENO_IRQ_2 =1 when GENO_2 toggles to 0. IF GENO_LEVEL_2=1, GENO_IRQ_2 =1 when GENO_2 toggles to 1.";
|
||||
geno_int_1 1 rw "If GENO_INT_1=0, GENO_IRQ_1=1 when GENO_1 toggles; If GENO_INT_1=1: IF GENO_LEVEL_1=0, GENO_IRQ_1 =1 when GENO_1 toggles to 0. IF GENO_LEVEL_1=1, GENO_IRQ_1 =1 when GENO_1 toggles to 1.";
|
||||
geno_int_0 1 rw "If GENO_INT_0=0, GENO_IRQ_0=1 when GENO_0 toggles; If GENO_INT_0=1: IF GENO_LEVEL_0=0, GENO_IRQ_0 =1 when GENO_0 toggles to 0. IF GENO_LEVEL_0=1, GENO_IRQ_0 =1 when GENO_0 toggles to 1.";
|
||||
};
|
||||
|
||||
register c2c_geno_level addr(base, 0x88) "" {
|
||||
geno_level_31 1 rw "IF GENO_LEVEL_31=0, GENO_IRQ_31 =1 when GENO_31 toggles to 0. IF GENO_LEVEL_31=1, GENO_IRQ_31 =1 when GENO_31 toggles to 1.";
|
||||
geno_level_30 1 rw "IF GENO_LEVEL_30=0, GENO_IRQ_30 =1 when GENO_30 toggles to 0. IF GENO_LEVEL_30=1, GENO_IRQ_30 =1 when GENO_30 toggles to 1.";
|
||||
geno_level_29 1 rw "IF GENO_LEVEL_29=0, GENO_IRQ_29 =1 when GENO_29 toggles to 0. IF GENO_LEVEL_29=1, GENO_IRQ_29 =1 when GENO_29 toggles to 1.";
|
||||
geno_level_28 1 rw "IF GENO_LEVEL_28=0, GENO_IRQ_28 =1 when GENO_28 toggles to 0. IF GENO_LEVEL_28=1, GENO_IRQ_28 =1 when GENO_28 toggles to 1.";
|
||||
geno_level_27 1 rw "IF GENO_LEVEL_27=0, GENO_IRQ_27 =1 when GENO_27 toggles to 0. IF GENO_LEVEL_27=1, GENO_IRQ_27 =1 when GENO_27 toggles to 1.";
|
||||
geno_level_26 1 rw "IF GENO_LEVEL_26=0, GENO_IRQ_26 =1 when GENO_26 toggles to 0. IF GENO_LEVEL_26=1, GENO_IRQ_26 =1 when GENO_26 toggles to 1.";
|
||||
geno_level_25 1 rw "IF GENO_LEVEL_25=0, GENO_IRQ_25 =1 when GENO_25 toggles to 0. IF GENO_LEVEL_25=1, GENO_IRQ_25 =1 when GENO_25 toggles to 1.";
|
||||
geno_level_24 1 rw "IF GENO_LEVEL_24=0, GENO_IRQ_24 =1 when GENO_24 toggles to 0. IF GENO_LEVEL_24=1, GENO_IRQ_24 =1 when GENO_24 toggles to 1.";
|
||||
geno_level_23 1 rw "IF GENO_LEVEL_23=0, GENO_IRQ_23 =1 when GENO_23 toggles to 0. IF GENO_LEVEL_23=1, GENO_IRQ_23 =1 when GENO_23 toggles to 1.";
|
||||
geno_level_22 1 rw "IF GENO_LEVEL_22=0, GENO_IRQ_22 =1 when GENO_22 toggles to 0. IF GENO_LEVEL_22=1, GENO_IRQ_22 =1 when GENO_22 toggles to 1.";
|
||||
geno_level_21 1 rw "IF GENO_LEVEL_21=0, GENO_IRQ_21 =1 when GENO_21 toggles to 0. IF GENO_LEVEL_21=1, GENO_IRQ_21 =1 when GENO_21 toggles to 1.";
|
||||
geno_level_20 1 rw "IF GENO_LEVEL_20=0, GENO_IRQ_20 =1 when GENO_20 toggles to 0. IF GENO_LEVEL_20=1, GENO_IRQ_20 =1 when GENO_20 toggles to 1.";
|
||||
geno_level_19 1 rw "IF GENO_LEVEL_19=0, GENO_IRQ_19 =1 when GENO_19 toggles to 0. IF GENO_LEVEL_19=1, GENO_IRQ_19 =1 when GENO_19 toggles to 1.";
|
||||
geno_level_18 1 rw "IF GENO_LEVEL_18=0, GENO_IRQ_18 =1 when GENO_18 toggles to 0. IF GENO_LEVEL_18=1, GENO_IRQ_18 =1 when GENO_18 toggles to 1.";
|
||||
geno_level_17 1 rw "IF GENO_LEVEL_17=0, GENO_IRQ_17 =1 when GENO_17 toggles to 0. IF GENO_LEVEL_17=1, GENO_IRQ_17 =1 when GENO_17 toggles to 1.";
|
||||
geno_level_16 1 rw "IF GENO_LEVEL_16=0, GENO_IRQ_16 =1 when GENO_16 toggles to 0. IF GENO_LEVEL_16=1, GENO_IRQ_16 =1 when GENO_16 toggles to 1.";
|
||||
geno_level_15 1 rw "IF GENO_LEVEL_15=0, GENO_IRQ_15 =1 when GENO_15 toggles to 0. IF GENO_LEVEL_15=1, GENO_IRQ_15 =1 when GENO_15 toggles to 1.";
|
||||
geno_level_14 1 rw "IF GENO_LEVEL_14=0, GENO_IRQ_14 =1 when GENO_14 toggles to 0. IF GENO_LEVEL_14=1, GENO_IRQ_14 =1 when GENO_14 toggles to 1.";
|
||||
geno_level_13 1 rw "IF GENO_LEVEL_13=0, GENO_IRQ_13 =1 when GENO_13 toggles to 0. IF GENO_LEVEL_13=1, GENO_IRQ_13 =1 when GENO_13 toggles to 1.";
|
||||
geno_level_12 1 rw "IF GENO_LEVEL_12=0, GENO_IRQ_12 =1 when GENO_12 toggles to 0. IF GENO_LEVEL_12=1, GENO_IRQ_12 =1 when GENO_12 toggles to 1.";
|
||||
geno_level_11 1 rw "IF GENO_LEVEL_11=0, GENO_IRQ_11 =1 when GENO_11 toggles to 0. IF GENO_LEVEL_11=1, GENO_IRQ_11 =1 when GENO_11 toggles to 1.";
|
||||
geno_level_10 1 rw "IF GENO_LEVEL_10=0, GENO_IRQ_10 =1 when GENO_10 toggles to 0. IF GENO_LEVEL_10=1, GENO_IRQ_10 =1 when GENO_10 toggles to 1.";
|
||||
geno_level_9 1 rw "IF GENO_LEVEL_9=0, GENO_IRQ_9 =1 when GENO_9 toggles to 0. IF GENO_LEVEL_9=1, GENO_IRQ_9 =1 when GENO_9 toggles to 1.";
|
||||
geno_level_8 1 rw "IF GENO_LEVEL_8=0, GENO_IRQ_8 =1 when GENO_8 toggles to 0. IF GENO_LEVEL_8=1, GENO_IRQ_8 =1 when GENO_8 toggles to 1.";
|
||||
geno_level_7 1 rw "IF GENO_LEVEL_7=0, GENO_IRQ_7 =1 when GENO_7 toggles to 0. IF GENO_LEVEL_7=1, GENO_IRQ_7 =1 when GENO_7 toggles to 1.";
|
||||
geno_level_6 1 rw "IF GENO_LEVEL_6=0, GENO_IRQ_6 =1 when GENO_6 toggles to 0. IF GENO_LEVEL_6=1, GENO_IRQ_6 =1 when GENO_6 toggles to 1.";
|
||||
geno_level_5 1 rw "IF GENO_LEVEL_5=0, GENO_IRQ_5 =1 when GENO_5 toggles to 0. IF GENO_LEVEL_5=1, GENO_IRQ_5 =1 when GENO_5 toggles to 1.";
|
||||
geno_level_4 1 rw "IF GENO_LEVEL_4=0, GENO_IRQ_4 =1 when GENO_4 toggles to 0. IF GENO_LEVEL_4=1, GENO_IRQ_4 =1 when GENO_4 toggles to 1.";
|
||||
geno_level_3 1 rw "IF GENO_LEVEL_3=0, GENO_IRQ_3 =1 when GENO_3 toggles to 0. IF GENO_LEVEL_3=1, GENO_IRQ_3 =1 when GENO_3 toggles to 1.";
|
||||
geno_level_2 1 rw "IF GENO_LEVEL_2=0, GENO_IRQ_2 =1 when GENO_2 toggles to 0. IF GENO_LEVEL_2=1, GENO_IRQ_2 =1 when GENO_2 toggles to 1.";
|
||||
geno_level_1 1 rw "IF GENO_LEVEL_1=0, GENO_IRQ_1 =1 when GENO_1 toggles to 0. IF GENO_LEVEL_1=1, GENO_IRQ_1 =1 when GENO_1 toggles to 1.";
|
||||
geno_level_0 1 rw "IF GENO_LEVEL_0=0, GENO_IRQ_0 =1 when GENO_0 toggles to 0. IF GENO_LEVEL_0=1, GENO_IRQ_0 =1 when GENO_0 toggles to 1.";
|
||||
};
|
||||
};
|
||||
151
devices/omap/omap44xx_c2c_master_niu_firewall.dev
Normal file
151
devices/omap/omap44xx_c2c_master_niu_firewall.dev
Normal file
@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_c2c_master_niu_firewall.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_c2c_master_niu_firewall msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
register error_log_k addr(base, 0x0) "Error log register for port k" {
|
||||
_ 8 mbz;
|
||||
blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
_ 1 mbz;
|
||||
region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
};
|
||||
|
||||
register logical_addr_errlog_k ro addr(base, 0x4) "Logical Physical Address Error log register for port k" type(uint32);
|
||||
|
||||
register regupdate_control addr(base, 0x40) "Register update control register" {
|
||||
_ 30 mbz;
|
||||
fw_load_req 1 ro "Hadrdware set/Software clear";
|
||||
busy_req 1 rw "Busy request";
|
||||
};
|
||||
|
||||
register start_region_i_1 addr(base, 0x90) "Start physical address of region i" {
|
||||
start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
register start_region_i_2 addr(base, 0xA0) "Start physical address of region i" {
|
||||
start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
register start_region_i_3 addr(base, 0xB0) "Start physical address of region i" {
|
||||
start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
|
||||
_ 12 mbz;
|
||||
};
|
||||
|
||||
register end_region_i_1 addr(base, 0x94) "End physical address of region i" {
|
||||
end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
|
||||
_ 9 mbz;
|
||||
region_enable_port2 1 rw "Enable this region for port 2.";
|
||||
region_enable_port1 1 rw "Enable this region for port 1.";
|
||||
region_enable_port0 1 rw "Enable this region for port 0.";
|
||||
};
|
||||
|
||||
register end_region_i_2 addr(base, 0xA4) "End physical address of region i" {
|
||||
end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
|
||||
_ 9 mbz;
|
||||
region_enable_port2 1 rw "Enable this region for port 2.";
|
||||
region_enable_port1 1 rw "Enable this region for port 1.";
|
||||
region_enable_port0 1 rw "Enable this region for port 0.";
|
||||
};
|
||||
|
||||
register end_region_i_3 addr(base, 0xB4) "End physical address of region i" {
|
||||
end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
|
||||
_ 9 mbz;
|
||||
region_enable_port2 1 rw "Enable this region for port 2.";
|
||||
region_enable_port1 1 rw "Enable this region for port 1.";
|
||||
region_enable_port0 1 rw "Enable this region for port 0.";
|
||||
};
|
||||
|
||||
register mrm_permission_region_low_j addr(base, 0x88) "Region j Permission Low" {
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_debug 1 rw "Public Privilege Debug Allowed";
|
||||
pub_usr_debug 1 rw "Public User Debug Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_write 1 rw "Public Privilege Write Allowed";
|
||||
pub_prv_read 1 rw "Public Privilege Read Allowed";
|
||||
pub_prv_exe 1 rw "Public Privilege Exe Allowed";
|
||||
pub_usr_write 1 rw "Public User Write Access Allowed";
|
||||
pub_usr_read 1 rw "Public User Read Access Allowed";
|
||||
pub_usr_exe 1 rw "Public User Exe Access Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
register mrm_permission_region_high_j addr(base, 0x8C) "Region j Permission High" {
|
||||
_ 6 rsvd;
|
||||
w12 1 rw "Master NIU ConnID = 12 write permission";
|
||||
r12 1 rw "Master NIU ConnID = 12 read permission";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
w10 1 rw "Master NIU ConnID = 10 write permission";
|
||||
r10 1 rw "Master NIU ConnID = 10 read permission";
|
||||
w9 1 rw "Master NIU ConnID = 9 write permission";
|
||||
r9 1 rw "Master NIU ConnID = 9 read permission";
|
||||
w8 1 rw "Master NIU ConnID = 8 write permission";
|
||||
r8 1 rw "Master NIU ConnID = 8 read permission";
|
||||
w7 1 rw "Master NIU ConnID = 7 write permission";
|
||||
r7 1 rw "Master NIU ConnID = 7 read permission";
|
||||
w6 1 rw "Master NIU ConnID = 6 write permission";
|
||||
r6 1 rw "Master NIU ConnID = 6 read permission";
|
||||
w5 1 rw "Master NIU ConnID = 5 write permission";
|
||||
r5 1 rw "Master NIU ConnID = 5 read permission";
|
||||
w4 1 rw "Master NIU ConnID = 4 write permission";
|
||||
r4 1 rw "Master NIU ConnID = 4 read permission";
|
||||
w3 1 rw "Master NIU ConnID = 3 write permission";
|
||||
r3 1 rw "Master NIU ConnID = 3 read permission";
|
||||
w2 1 rw "Master NIU ConnID = 2 write permission";
|
||||
r2 1 rw "Master NIU ConnID = 2 read permission";
|
||||
w1 1 rw "Master NIU ConnID = 1 write permission";
|
||||
r1 1 rw "Master NIU ConnID = 1 read permission";
|
||||
w0 1 rw "Master NIU ConnID = 0 write permission";
|
||||
r0 1 rw "Master NIU ConnID = 0 read permission";
|
||||
};
|
||||
};
|
||||
307
devices/omap/omap44xx_c2c_slave_niu_firewall.dev
Normal file
307
devices/omap/omap44xx_c2c_slave_niu_firewall.dev
Normal file
@ -0,0 +1,307 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_c2c_slave_niu_firewall.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_c2c_slave_niu_firewall msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
register error_log_k addr(base, 0x0) "Error log register for port k" {
|
||||
_ 8 mbz;
|
||||
blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
_ 1 mbz;
|
||||
region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
|
||||
};
|
||||
|
||||
register logical_addr_errlog_k ro addr(base, 0x20004) "Logical Physical Address Error log register for port k" type(uint32);
|
||||
|
||||
register regupdate_control addr(base, 0x20040) "Register update control register" {
|
||||
_ 30 mbz;
|
||||
fw_load_req 1 ro "Hadrdware set/Software clear";
|
||||
busy_req 1 rw "Busy request";
|
||||
};
|
||||
|
||||
register mrm_permission_region_low_j_0 addr(base, 0x20088) "Region j Permission Low" {
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_debug 1 rw "Public Privilege Debug Allowed";
|
||||
pub_usr_debug 1 rw "Public User Debug Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_write 1 rw "Public Privilege Write Allowed";
|
||||
pub_prv_read 1 rw "Public Privilege Read Allowed";
|
||||
pub_prv_exe 1 rw "Public Privilege Exe Allowed";
|
||||
pub_usr_write 1 rw "Public User Write Access Allowed";
|
||||
pub_usr_read 1 rw "Public User Read Access Allowed";
|
||||
pub_usr_exe 1 rw "Public User Exe Access Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
register mrm_permission_region_low_j_1 addr(base, 0x20098) "Region j Permission Low" {
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_debug 1 rw "Public Privilege Debug Allowed";
|
||||
pub_usr_debug 1 rw "Public User Debug Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_write 1 rw "Public Privilege Write Allowed";
|
||||
pub_prv_read 1 rw "Public Privilege Read Allowed";
|
||||
pub_prv_exe 1 rw "Public Privilege Exe Allowed";
|
||||
pub_usr_write 1 rw "Public User Write Access Allowed";
|
||||
pub_usr_read 1 rw "Public User Read Access Allowed";
|
||||
pub_usr_exe 1 rw "Public User Exe Access Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
register mrm_permission_region_low_j_2 addr(base, 0x200A8) "Region j Permission Low" {
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_debug 1 rw "Public Privilege Debug Allowed";
|
||||
pub_usr_debug 1 rw "Public User Debug Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_write 1 rw "Public Privilege Write Allowed";
|
||||
pub_prv_read 1 rw "Public Privilege Read Allowed";
|
||||
pub_prv_exe 1 rw "Public Privilege Exe Allowed";
|
||||
pub_usr_write 1 rw "Public User Write Access Allowed";
|
||||
pub_usr_read 1 rw "Public User Read Access Allowed";
|
||||
pub_usr_exe 1 rw "Public User Exe Access Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
register mrm_permission_region_low_j_3 addr(base, 0x200B8) "Region j Permission Low" {
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_debug 1 rw "Public Privilege Debug Allowed";
|
||||
pub_usr_debug 1 rw "Public User Debug Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
pub_prv_write 1 rw "Public Privilege Write Allowed";
|
||||
pub_prv_read 1 rw "Public Privilege Read Allowed";
|
||||
pub_prv_exe 1 rw "Public Privilege Exe Allowed";
|
||||
pub_usr_write 1 rw "Public User Write Access Allowed";
|
||||
pub_usr_read 1 rw "Public User Read Access Allowed";
|
||||
pub_usr_exe 1 rw "Public User Exe Access Allowed";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
};
|
||||
|
||||
register mrm_permission_region_high_j_0 addr(base, 0x2008C) "Region j Permission High" {
|
||||
_ 6 rsvd;
|
||||
w12 1 rw "Master NIU ConnID = 12 write permission";
|
||||
r12 1 rw "Master NIU ConnID = 12 read permission";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
w10 1 rw "Master NIU ConnID = 10 write permission";
|
||||
r10 1 rw "Master NIU ConnID = 10 read permission";
|
||||
w9 1 rw "Master NIU ConnID = 9 write permission";
|
||||
r9 1 rw "Master NIU ConnID = 9 read permission";
|
||||
w8 1 rw "Master NIU ConnID = 8 write permission";
|
||||
r8 1 rw "Master NIU ConnID = 8 read permission";
|
||||
w7 1 rw "Master NIU ConnID = 7 write permission";
|
||||
r7 1 rw "Master NIU ConnID = 7 read permission";
|
||||
w6 1 rw "Master NIU ConnID = 6 write permission";
|
||||
r6 1 rw "Master NIU ConnID = 6 read permission";
|
||||
w5 1 rw "Master NIU ConnID = 5 write permission";
|
||||
r5 1 rw "Master NIU ConnID = 5 read permission";
|
||||
w4 1 rw "Master NIU ConnID = 4 write permission";
|
||||
r4 1 rw "Master NIU ConnID = 4 read permission";
|
||||
w3 1 rw "Master NIU ConnID = 3 write permission";
|
||||
r3 1 rw "Master NIU ConnID = 3 read permission";
|
||||
w2 1 rw "Master NIU ConnID = 2 write permission";
|
||||
r2 1 rw "Master NIU ConnID = 2 read permission";
|
||||
w1 1 rw "Master NIU ConnID = 1 write permission";
|
||||
r1 1 rw "Master NIU ConnID = 1 read permission";
|
||||
w0 1 rw "Master NIU ConnID = 0 write permission";
|
||||
r0 1 rw "Master NIU ConnID = 0 read permission";
|
||||
};
|
||||
|
||||
register mrm_permission_region_high_j_1 addr(base, 0x2009C) "Region j Permission High" {
|
||||
_ 6 rsvd;
|
||||
w12 1 rw "Master NIU ConnID = 12 write permission";
|
||||
r12 1 rw "Master NIU ConnID = 12 read permission";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
w10 1 rw "Master NIU ConnID = 10 write permission";
|
||||
r10 1 rw "Master NIU ConnID = 10 read permission";
|
||||
w9 1 rw "Master NIU ConnID = 9 write permission";
|
||||
r9 1 rw "Master NIU ConnID = 9 read permission";
|
||||
w8 1 rw "Master NIU ConnID = 8 write permission";
|
||||
r8 1 rw "Master NIU ConnID = 8 read permission";
|
||||
w7 1 rw "Master NIU ConnID = 7 write permission";
|
||||
r7 1 rw "Master NIU ConnID = 7 read permission";
|
||||
w6 1 rw "Master NIU ConnID = 6 write permission";
|
||||
r6 1 rw "Master NIU ConnID = 6 read permission";
|
||||
w5 1 rw "Master NIU ConnID = 5 write permission";
|
||||
r5 1 rw "Master NIU ConnID = 5 read permission";
|
||||
w4 1 rw "Master NIU ConnID = 4 write permission";
|
||||
r4 1 rw "Master NIU ConnID = 4 read permission";
|
||||
w3 1 rw "Master NIU ConnID = 3 write permission";
|
||||
r3 1 rw "Master NIU ConnID = 3 read permission";
|
||||
w2 1 rw "Master NIU ConnID = 2 write permission";
|
||||
r2 1 rw "Master NIU ConnID = 2 read permission";
|
||||
w1 1 rw "Master NIU ConnID = 1 write permission";
|
||||
r1 1 rw "Master NIU ConnID = 1 read permission";
|
||||
w0 1 rw "Master NIU ConnID = 0 write permission";
|
||||
r0 1 rw "Master NIU ConnID = 0 read permission";
|
||||
};
|
||||
|
||||
register mrm_permission_region_high_j_2 addr(base, 0x200AC) "Region j Permission High" {
|
||||
_ 6 rsvd;
|
||||
w12 1 rw "Master NIU ConnID = 12 write permission";
|
||||
r12 1 rw "Master NIU ConnID = 12 read permission";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
w10 1 rw "Master NIU ConnID = 10 write permission";
|
||||
r10 1 rw "Master NIU ConnID = 10 read permission";
|
||||
w9 1 rw "Master NIU ConnID = 9 write permission";
|
||||
r9 1 rw "Master NIU ConnID = 9 read permission";
|
||||
w8 1 rw "Master NIU ConnID = 8 write permission";
|
||||
r8 1 rw "Master NIU ConnID = 8 read permission";
|
||||
w7 1 rw "Master NIU ConnID = 7 write permission";
|
||||
r7 1 rw "Master NIU ConnID = 7 read permission";
|
||||
w6 1 rw "Master NIU ConnID = 6 write permission";
|
||||
r6 1 rw "Master NIU ConnID = 6 read permission";
|
||||
w5 1 rw "Master NIU ConnID = 5 write permission";
|
||||
r5 1 rw "Master NIU ConnID = 5 read permission";
|
||||
w4 1 rw "Master NIU ConnID = 4 write permission";
|
||||
r4 1 rw "Master NIU ConnID = 4 read permission";
|
||||
w3 1 rw "Master NIU ConnID = 3 write permission";
|
||||
r3 1 rw "Master NIU ConnID = 3 read permission";
|
||||
w2 1 rw "Master NIU ConnID = 2 write permission";
|
||||
r2 1 rw "Master NIU ConnID = 2 read permission";
|
||||
w1 1 rw "Master NIU ConnID = 1 write permission";
|
||||
r1 1 rw "Master NIU ConnID = 1 read permission";
|
||||
w0 1 rw "Master NIU ConnID = 0 write permission";
|
||||
r0 1 rw "Master NIU ConnID = 0 read permission";
|
||||
};
|
||||
|
||||
register mrm_permission_region_high_j_3 addr(base, 0x200BC) "Region j Permission High" {
|
||||
_ 6 rsvd;
|
||||
w12 1 rw "Master NIU ConnID = 12 write permission";
|
||||
r12 1 rw "Master NIU ConnID = 12 read permission";
|
||||
_ 1 rsvd;
|
||||
_ 1 rsvd;
|
||||
w10 1 rw "Master NIU ConnID = 10 write permission";
|
||||
r10 1 rw "Master NIU ConnID = 10 read permission";
|
||||
w9 1 rw "Master NIU ConnID = 9 write permission";
|
||||
r9 1 rw "Master NIU ConnID = 9 read permission";
|
||||
w8 1 rw "Master NIU ConnID = 8 write permission";
|
||||
r8 1 rw "Master NIU ConnID = 8 read permission";
|
||||
w7 1 rw "Master NIU ConnID = 7 write permission";
|
||||
r7 1 rw "Master NIU ConnID = 7 read permission";
|
||||
w6 1 rw "Master NIU ConnID = 6 write permission";
|
||||
r6 1 rw "Master NIU ConnID = 6 read permission";
|
||||
w5 1 rw "Master NIU ConnID = 5 write permission";
|
||||
r5 1 rw "Master NIU ConnID = 5 read permission";
|
||||
w4 1 rw "Master NIU ConnID = 4 write permission";
|
||||
r4 1 rw "Master NIU ConnID = 4 read permission";
|
||||
w3 1 rw "Master NIU ConnID = 3 write permission";
|
||||
r3 1 rw "Master NIU ConnID = 3 read permission";
|
||||
w2 1 rw "Master NIU ConnID = 2 write permission";
|
||||
r2 1 rw "Master NIU ConnID = 2 read permission";
|
||||
w1 1 rw "Master NIU ConnID = 1 write permission";
|
||||
r1 1 rw "Master NIU ConnID = 1 read permission";
|
||||
w0 1 rw "Master NIU ConnID = 0 write permission";
|
||||
r0 1 rw "Master NIU ConnID = 0 read permission";
|
||||
};
|
||||
};
|
||||
127
devices/omap/omap44xx_cam_cm2.dev
Normal file
127
devices/omap/omap44xx_cam_cm2.dev
Normal file
@ -0,0 +1,127 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_cam_cm2.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_cam_cm2 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants clkactivity_fdif_fclk_status width(1) "" {
|
||||
CLKACTIVITY_FDIF_FCLK_0_r = 0 "Corresponding clock is definitely gated";
|
||||
CLKACTIVITY_FDIF_FCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
|
||||
};
|
||||
|
||||
constants clktrctrl_status width(2) "" {
|
||||
CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
|
||||
CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
|
||||
CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
|
||||
CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
|
||||
};
|
||||
|
||||
register cm_cam_clkstctrl addr(base, 0x0) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
|
||||
_ 21 mbz;
|
||||
clkactivity_fdif_fclk 1 ro type(clkactivity_fdif_fclk_status) "This field indicates the state of the FDIF_FCLK clock input of the domain. [warm reset insensitive]";
|
||||
clkactivity_cam_phy_ctrl_clk 1 ro type(clkactivity_fdif_fclk_status) "This field indicates the state of the CAM_PHY_CTRL_CLK clock input of the domain. [warm reset insensitive]";
|
||||
clkactivity_iss_clk 1 ro type(clkactivity_fdif_fclk_status) "This field indicates the state of the ISS_CLK clock input of the domain. [warm reset insensitive]";
|
||||
_ 6 mbz;
|
||||
clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the CAM clock domain.";
|
||||
};
|
||||
|
||||
constants l3_2_statdep_status width(1) "" {
|
||||
L3_2_STATDEP_1_r = 1 "Dependency is enabled";
|
||||
};
|
||||
|
||||
constants l3_1_statdep_status width(1) "" {
|
||||
L3_1_STATDEP_0 = 0 "Dependency is disabled";
|
||||
L3_1_STATDEP_1 = 1 "Dependency is enabled";
|
||||
};
|
||||
|
||||
register cm_cam_staticdep addr(base, 0x4) "This register controls the static domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having system initiator(s)." {
|
||||
_ 25 mbz;
|
||||
l3_2_statdep 1 ro type(l3_2_statdep_status) "Static dependency towards L3_2 clock domain";
|
||||
l3_1_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards L3_1 clock domain";
|
||||
memif_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards MEMIF clock domain";
|
||||
_ 1 mbz;
|
||||
ivahd_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards IVAHD clock domain";
|
||||
_ 2 mbz;
|
||||
};
|
||||
|
||||
register cm_cam_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." {
|
||||
_ 25 mbz;
|
||||
l3_2_dyndep 1 ro type(l3_1_statdep_status) "Dynamic dependency towards L3_2 clock domain";
|
||||
_ 6 mbz;
|
||||
};
|
||||
|
||||
constants stbyst_status width(1) "" {
|
||||
STBYST_0_r = 0 "Module is functional (not in standby)";
|
||||
STBYST_1_r = 1 "Module is in standby";
|
||||
};
|
||||
|
||||
constants idlest_status width(2) "" {
|
||||
IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
|
||||
IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
|
||||
IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
|
||||
IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
|
||||
};
|
||||
|
||||
constants optfclken_ctrlclk_status width(1) "" {
|
||||
OPTFCLKEN_CTRLCLK_0 = 0 "Optional functional clock is disabled";
|
||||
OPTFCLKEN_CTRLCLK_1 = 1 "Optional functional clock is enabled";
|
||||
};
|
||||
|
||||
constants modulemode_status width(2) "" {
|
||||
MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
|
||||
MODULEMODE_1_r = 1 "Reserved";
|
||||
MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
|
||||
MODULEMODE_3_r = 3 "Reserved";
|
||||
};
|
||||
|
||||
register cm_cam_iss_clkctrl addr(base, 0x20) "This register manages the ISS clocks." {
|
||||
_ 13 mbz;
|
||||
stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 7 mbz;
|
||||
optfclken_ctrlclk 1 rw type(optfclken_ctrlclk_status) "Optional functional clock control for CAM_PHY_CTRL_GCLK 96Mhz clock.";
|
||||
_ 6 mbz;
|
||||
modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
|
||||
constants clksel_fclk_status width(2) "" {
|
||||
CLKSEL_FCLK_0 = 0 "FDIF_FCLK is divide by 1 of FUNC_128_CLK, to be used for OPP100";
|
||||
CLKSEL_FCLK_1 = 1 "FDIF_FCLK is divide by 2 of FUNC_128_CLK, to be used for OPP50";
|
||||
CLKSEL_FCLK_2 = 2 "FDIF_FCLK is divide by 4 of FUNC_128_CLK";
|
||||
CLKSEL_FCLK_3 = 3 "Reserved";
|
||||
};
|
||||
|
||||
register cm_cam_fdif_clkctrl addr(base, 0x28) "This register manages the FDIF clocks." {
|
||||
_ 6 mbz;
|
||||
clksel_fclk 2 rw type(clksel_fclk_status) "Select the ration of FDIF_FCLK to FUNC_128M_CLK";
|
||||
_ 5 mbz;
|
||||
stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
|
||||
idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
|
||||
_ 14 mbz;
|
||||
modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
|
||||
};
|
||||
};
|
||||
117
devices/omap/omap44xx_cam_prm.dev
Normal file
117
devices/omap/omap44xx_cam_prm.dev
Normal file
@ -0,0 +1,117 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_cam_prm.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_cam_prm msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants cam_mem_onstate_status width(2) "" {
|
||||
CAM_MEM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON.";
|
||||
};
|
||||
|
||||
constants lowpowerstatechange_status width(1) "" {
|
||||
LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change.";
|
||||
LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON.";
|
||||
};
|
||||
|
||||
constants powerstate_status width(2) "" {
|
||||
POWERSTATE_0 = 0 "OFF state";
|
||||
POWERSTATE_1_r = 1 "Reserved";
|
||||
POWERSTATE_2 = 2 "INACTIVE state";
|
||||
POWERSTATE_3 = 3 "ON State";
|
||||
};
|
||||
|
||||
register pm_cam_pwrstctrl addr(base, 0x0) "This register controls the CAM power state to reach upon a domain sleep transition" {
|
||||
_ 14 mbz;
|
||||
cam_mem_onstate 2 ro type(cam_mem_onstate_status) "CAM_MEM memory state when domain is ON.";
|
||||
_ 11 mbz;
|
||||
lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain.";
|
||||
_ 2 mbz;
|
||||
powerstate 2 rw type(powerstate_status) "Power state control";
|
||||
};
|
||||
|
||||
constants lastpowerstateentered_status width(2) "" {
|
||||
LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE";
|
||||
LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE";
|
||||
LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION";
|
||||
LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF";
|
||||
};
|
||||
|
||||
constants intransition_status width(1) "" {
|
||||
INTRANSITION_1_r = 1 "Power domain transition is in progress.";
|
||||
INTRANSITION_0_r = 0 "No on-going transition on power domain";
|
||||
};
|
||||
|
||||
constants cam_mem_statest_status width(2) "" {
|
||||
CAM_MEM_STATEST_3_r = 3 "Memory is ON";
|
||||
CAM_MEM_STATEST_2_r = 2 "Reserved";
|
||||
CAM_MEM_STATEST_1_r = 1 "Reserved";
|
||||
CAM_MEM_STATEST_0_r = 0 "Memory is OFF";
|
||||
};
|
||||
|
||||
constants logicstatest_status width(1) "" {
|
||||
LOGICSTATEST_1_r = 1 "Logic in domain is ON";
|
||||
LOGICSTATEST_0_r = 0 "Logic in domain is OFF";
|
||||
};
|
||||
|
||||
constants powerstatest_status width(2) "" {
|
||||
POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE";
|
||||
POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE";
|
||||
POWERSTATEST_1_r = 1 "Power domain is in RETENTION";
|
||||
POWERSTATEST_0_r = 0 "Power domain is OFF";
|
||||
};
|
||||
|
||||
register pm_cam_pwrstst addr(base, 0x4) "This register provides a status on the current CAM power domain state. [warm reset insensitive]" {
|
||||
_ 6 mbz;
|
||||
lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only.";
|
||||
_ 3 mbz;
|
||||
intransition 1 ro type(intransition_status) "Domain transition status";
|
||||
_ 14 mbz;
|
||||
cam_mem_statest 2 ro type(cam_mem_statest_status) "CAM_MEM memory state status";
|
||||
_ 1 mbz;
|
||||
logicstatest 1 ro type(logicstatest_status) "Logic state status";
|
||||
powerstatest 2 ro type(powerstatest_status) "Current power state status";
|
||||
};
|
||||
|
||||
constants lostmem_cam_mem_status width(1) "" {
|
||||
LOSTMEM_CAM_MEM_0 = 0 "Context has been maintained";
|
||||
LOSTMEM_CAM_MEM_1 = 1 "Context has been lost";
|
||||
};
|
||||
|
||||
register rm_cam_iss_context addr(base, 0x24) "This register contains dedicated ISS context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_cam_mem 1 rw1c type(lostmem_cam_mem_status) "Specify if memory-based context in CAM_MEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_cam_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)";
|
||||
};
|
||||
|
||||
register rm_cam_fdif_context addr(base, 0x2C) "This register contains dedicated FDIF context statuses. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
lostmem_cam_mem 1 rw1c type(lostmem_cam_mem_status) "Specify if memory-based context in CAM_MEM memory bank has been lost due to a previous power transition or other reset source.";
|
||||
_ 7 mbz;
|
||||
lostcontext_dff 1 rw1c type(lostmem_cam_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)";
|
||||
};
|
||||
};
|
||||
2163
devices/omap/omap44xx_cfg_ap.dev
Normal file
2163
devices/omap/omap44xx_cfg_ap.dev
Normal file
File diff suppressed because it is too large
Load Diff
639
devices/omap/omap44xx_ckgen_cm1.dev
Normal file
639
devices/omap/omap44xx_ckgen_cm1.dev
Normal file
@ -0,0 +1,639 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_ckgen_cm1.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_ckgen_cm1 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants clksel_l4_status width(1) "" {
|
||||
CLKSEL_L4_0 = 0 "L4_CLK is L3_CLK divided by 1";
|
||||
CLKSEL_L4_1 = 1 "L4_CLK is L3_CLK divided by 2, to be used for OPP100 and OPP50";
|
||||
};
|
||||
|
||||
constants clksel_l3_status width(1) "" {
|
||||
CLKSEL_L3_0 = 0 "L3_CLK is CORE_CLK divided by 1";
|
||||
CLKSEL_L3_1 = 1 "L3_CLK is CORE_CLK divided by 2, to be used for OPP100 and OPP50";
|
||||
};
|
||||
|
||||
constants clksel_core_status width(1) "" {
|
||||
CLKSEL_CORE_0 = 0 "CORE_CLK is CORE_X2_CLK divided by 1, to be used for OPP100 and OPP50";
|
||||
CLKSEL_CORE_1 = 1 "CORE_CLK is CORE_X2_CLK divided by 2";
|
||||
};
|
||||
|
||||
register cm_clksel_core addr(base, 0x0) "CORE module clock selection." {
|
||||
_ 23 mbz;
|
||||
clksel_l4 1 rw type(clksel_l4_status) "Selects L4 interconnect clock (L4_clk)";
|
||||
_ 3 mbz;
|
||||
clksel_l3 1 rw type(clksel_l3_status) "Selects L3 interconnect clock (L3_clk)";
|
||||
_ 3 mbz;
|
||||
clksel_core 1 rw type(clksel_core_status) "Selects CORE_CLK configuration";
|
||||
};
|
||||
|
||||
constants slimbus_clk_gate_status width(1) "" {
|
||||
SLIMBUS_CLK_GATE_0 = 0 "The clock is gated";
|
||||
SLIMBUS_CLK_GATE_1 = 1 "The clock is enabled";
|
||||
};
|
||||
|
||||
constants clksel_opp_status width(2) "" {
|
||||
CLKSEL_OPP_0 = 0 "ABE_CLK is divide by 1 of DPLL_ABE_X2_CLK, to be used for OPP100";
|
||||
CLKSEL_OPP_1 = 1 "ABE_CLK is divide by 2 of DPLL_ABE_X2_CLK, to be used for OPP50";
|
||||
CLKSEL_OPP_2 = 2 "ABE_CLK is divide by 4 of DPLL_ABE_X2_CLK";
|
||||
CLKSEL_OPP_3 = 3 "Reserved";
|
||||
};
|
||||
|
||||
register cm_clksel_abe addr(base, 0x8) "ABE module clock selection." {
|
||||
_ 21 mbz;
|
||||
slimbus_clk_gate 1 rw type(slimbus_clk_gate_status) "Gating control for SLIMBUS_CLK clock tree in ABE. SLIMbus module always gets the ungated version.";
|
||||
_ 1 mbz;
|
||||
pad_clks_gate 1 rw type(slimbus_clk_gate_status) "Gating control for PAD_CLKS clock tree in ABE";
|
||||
_ 6 mbz;
|
||||
clksel_opp 2 rw type(clksel_opp_status) "Selects the OPP divider ABE domain";
|
||||
};
|
||||
|
||||
constants dll_override_status width(1) "" {
|
||||
DLL_OVERRIDE_0 = 0 "Lock and code outputs are not overriden";
|
||||
DLL_OVERRIDE_1 = 1 "Lock output is overriden to 1 and code output is overriden with a value coming from control module.";
|
||||
};
|
||||
|
||||
register cm_dll_ctrl addr(base, 0x10) "Special register for DLL control" {
|
||||
_ 31 mbz;
|
||||
dll_override 1 rw type(dll_override_status) "Control if DLL lock and code outputs are overriden or not";
|
||||
};
|
||||
|
||||
constants dpll_ssc_downspread_status width(1) "" {
|
||||
DPLL_SSC_DOWNSPREAD_0 = 0 "When SSC is enabled, clock frequency is spread on both sides of the programmed frequency";
|
||||
DPLL_SSC_DOWNSPREAD_1 = 1 "When SSC is enabled, clock frequency is spread only on the lower side of the programmed frequency";
|
||||
};
|
||||
|
||||
constants dpll_ssc_ack_status width(1) "" {
|
||||
DPLL_SSC_ACK_0_r = 0 "SSC has been turned off on PLL o/ps";
|
||||
DPLL_SSC_ACK_1_r = 1 "SSC has been turned on on PLL o/ps";
|
||||
};
|
||||
|
||||
constants dpll_ssc_en_status width(1) "" {
|
||||
DPLL_SSC_EN_0 = 0 "SSC disabled";
|
||||
DPLL_SSC_EN_1 = 1 "SSC enabled";
|
||||
};
|
||||
|
||||
constants dpll_regm4xen_status width(1) "" {
|
||||
DPLL_REGM4XEN_0_r = 0 "REGM4XEN mode of the DPLL is disabled";
|
||||
};
|
||||
|
||||
constants dpll_lpmode_en_status width(1) "" {
|
||||
DPLL_LPMODE_EN_0 = 0 "Low-power mode of the DPLL is disabled";
|
||||
DPLL_LPMODE_EN_1 = 1 "Low-power mode of the DPLL is enabled";
|
||||
};
|
||||
|
||||
constants dpll_driftguard_en_status width(1) "" {
|
||||
DPLL_DRIFTGUARD_EN_0 = 0 "DRIFTGUARD feature is disabled";
|
||||
DPLL_DRIFTGUARD_EN_1 = 1 "DRIFTGUARD feature is enabled";
|
||||
};
|
||||
|
||||
constants dpll_en_status width(3) "" {
|
||||
DPLL_EN_0 = 0 "Reserved";
|
||||
DPLL_EN_1 = 1 "Reserved";
|
||||
DPLL_EN_2 = 2 "Reserved";
|
||||
DPLL_EN_3 = 3 "Reserved";
|
||||
DPLL_EN_MN = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode.";
|
||||
DPLL_EN_LP = 5 "Put the DPLL in Idle bypass low-power mode.";
|
||||
DPLL_EN_FR = 6 "Put the DPLL in Idle bypass fast-relock mode.";
|
||||
DPLL_EN_LM = 7 "Enables the DPLL in lock mode";
|
||||
};
|
||||
|
||||
register cm_clkmode_dpll_core addr(base, 0x20) "This register allows controlling the DPLL modes." {
|
||||
_ 17 mbz;
|
||||
dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required";
|
||||
dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature";
|
||||
dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking";
|
||||
dpll_regm4xen 1 ro type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled.";
|
||||
dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled.";
|
||||
_ 1 mbz;
|
||||
dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set.";
|
||||
_ 5 mbz;
|
||||
dpll_en 3 rw type(dpll_en_status) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode.";
|
||||
};
|
||||
|
||||
constants st_mn_bypass_status width(1) "" {
|
||||
ST_MN_BYPASS_1_r = 1 "DPLL is in MN_Bypass";
|
||||
ST_MN_BYPASS_0_r = 0 "DPLL is not in MN_Bypass";
|
||||
};
|
||||
|
||||
constants st_dpll_clk_status width(1) "" {
|
||||
ST_DPLL_CLK_1_r = 1 "DPLL is LOCKED";
|
||||
ST_DPLL_CLK_0_r = 0 "DPLL is either in bypass mode or in stop mode.";
|
||||
};
|
||||
|
||||
register cm_idlest_dpll_core addr(base, 0x24) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status";
|
||||
_ 7 mbz;
|
||||
st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status";
|
||||
};
|
||||
|
||||
constants auto_dpll_mode_status width(3) "" {
|
||||
AUTO_DPLL_MODE_0 = 0 "DPLL auto control disabled";
|
||||
AUTO_DPLL_MODE_1 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_2 = 2 "The DPLL is automatically put in fast-relock stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_3 = 3 "Reserved";
|
||||
AUTO_DPLL_MODE_4 = 4 "Reserved";
|
||||
AUTO_DPLL_MODE_5 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_6 = 6 "The DPLL is automatically put in idle bypass fast-relock mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_7 = 7 "Reserved";
|
||||
};
|
||||
|
||||
register cm_autoidle_dpll_core addr(base, 0x28) "This register provides automatic control over the DPLL activity." {
|
||||
_ 29 mbz;
|
||||
auto_dpll_mode 3 rw type(auto_dpll_mode_status) "DPLL automatic control.";
|
||||
};
|
||||
|
||||
constants dpll_clkouthif_clksel_status width(1) "" {
|
||||
DPLL_CLKOUTHIF_CLKSEL_0 = 0 "CLKOUTHIF is generated from the DPLL oscillator (DCO)";
|
||||
DPLL_CLKOUTHIF_CLKSEL_1 = 1 "CLKOUTHIF is generated from CLKINPHIF";
|
||||
};
|
||||
|
||||
register cm_clksel_dpll_core addr(base, 0x2C) "This register provides controls over the DPLL." {
|
||||
_ 8 mbz;
|
||||
dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2";
|
||||
_ 2 mbz;
|
||||
dpll_clkouthif_clksel 1 rw type(dpll_clkouthif_clksel_status) "Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL";
|
||||
_ 1 mbz;
|
||||
dpll_mult 11 rw type(dpll_en_status) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M).";
|
||||
_ 1 mbz;
|
||||
dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
constants st_dpll_clkout_status width(1) "" {
|
||||
ST_DPLL_CLKOUT_0_r = 0 "The clock output is gated";
|
||||
ST_DPLL_CLKOUT_1_r = 1 "The clock output is enabled";
|
||||
};
|
||||
|
||||
constants dpll_clkout_gate_ctrl_status width(1) "" {
|
||||
DPLL_CLKOUT_GATE_CTRL_0 = 0 "Automatically gate this clock when there is no dependency for it";
|
||||
DPLL_CLKOUT_GATE_CTRL_1 = 1 "Force this clock to stay enabled even if there is no request";
|
||||
};
|
||||
|
||||
constants dpll_clkout_div_status width(5) "" {
|
||||
DPLL_CLKOUT_DIV_0 = 0 "Reserved";
|
||||
DPLL_CLKOUT_DIV_1 = 1 "1, to be used for OPP100";
|
||||
DPLL_CLKOUT_DIV_2 = 2 "2, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m2_dpll_core addr(base, 0x30) "This register provides controls over the M2 divider of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkout 1 ro type(st_dpll_clkout_status) "DPLL CLKOUT status";
|
||||
dpll_clkout_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUT";
|
||||
_ 2 mbz;
|
||||
dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect";
|
||||
dpll_clkout_div 5 rw type(dpll_clkout_div_status) "DPLL post-divider factor, M2, for internal clock generation (1 to 31); Divide value from 1 to 31.";
|
||||
};
|
||||
|
||||
constants dpll_clkouthif_div_status width(5) "" {
|
||||
DPLL_CLKOUTHIF_DIV_0 = 0 "Reserved";
|
||||
DPLL_CLKOUTHIF_DIV_5 = 5 "5, to be used for OPP100";
|
||||
DPLL_CLKOUTHIF_DIV_8 = 8 "8, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m3_dpll_core addr(base, 0x34) "This register provides controls over the M3 divider of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkouthif 1 ro type(st_dpll_clkout_status) "DPLL CLKOUTHIF status";
|
||||
dpll_clkouthif_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUTHIF";
|
||||
_ 2 mbz;
|
||||
dpll_clkouthif_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect";
|
||||
dpll_clkouthif_div 5 rw type(dpll_clkouthif_div_status) "DPLL post-divider factor, M3, for internal clock generation (1 to 31). Divide value from 1 to 31";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout1_pwdn_status width(1) "" {
|
||||
HSDIVIDER_CLKOUT1_PWDN_0 = 0 "Divider is powered up";
|
||||
HSDIVIDER_CLKOUT1_PWDN_1 = 1 "Divider is powered down";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout1_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT1_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT1_DIV_8 = 8 "8, to be used for OPP100 and OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m4_dpll_core addr(base, 0x38) "This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout1_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M4 divider and CLKOUT1 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout1 1 ro type(st_dpll_clkout_status) "HSDIVIDER CLKOUT1 status";
|
||||
hsdivider_clkout1_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT1";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout1_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect";
|
||||
hsdivider_clkout1_div 5 rw type(hsdivider_clkout1_div_status) "DPLL M4 post-divider factor (1 to 31).";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout2_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT2_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT2_DIV_4 = 4 "4, to be used for OPP100";
|
||||
HSDIVIDER_CLKOUT2_DIV_8 = 8 "8, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m5_dpll_core addr(base, 0x3C) "This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout2_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M5 divider and CLKOUT2 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout2 1 ro type(st_dpll_clkout_status) "HSDIVIDER CLKOUT2 status";
|
||||
hsdivider_clkout2_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT2";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout2_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect";
|
||||
hsdivider_clkout2_div 5 rw type(hsdivider_clkout2_div_status) "DPLL M5 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout3_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT3_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT3_DIV_6 = 6 "6, to be used for OPP100";
|
||||
HSDIVIDER_CLKOUT3_DIV_8 = 8 "8, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m6_dpll_core addr(base, 0x40) "This register provides controls over the CLKOUT3 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout3_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M6 divider and CLKOUT3 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout3 1 ro type(st_dpll_clkout_status) "HSDIVIDER CLKOUT3 status";
|
||||
hsdivider_clkout3_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT3";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout3_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect";
|
||||
hsdivider_clkout3_div 5 rw type(hsdivider_clkout3_div_status) "DPLL M6 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout4_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT4_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT4_DIV_6 = 6 "6, to be used for OPP100 for 266.7-MHz clock output";
|
||||
HSDIVIDER_CLKOUT4_DIV_8 = 8 "8, to be used for OPP100 for 200-MHz clock output";
|
||||
HSDIVIDER_CLKOUT4_DIV_12 = 12 "12, to be used for OPP50 for 133.3-MHz clock output";
|
||||
HSDIVIDER_CLKOUT4_DIV_16 = 16 "16, to be used for OPP50 for 100-MHz clock output";
|
||||
};
|
||||
|
||||
register cm_div_m7_dpll_core addr(base, 0x44) "This register provides controls over the CLKOUT4 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout4_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M7 divider and CLKOUT4 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout4 1 ro type(st_dpll_clkout_status) "HSDIVIDER CLKOUT4 status";
|
||||
hsdivider_clkout4_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT4";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout4_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect";
|
||||
hsdivider_clkout4_div 5 rw type(hsdivider_clkout4_div_status) "DPLL M7 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
register cm_ssc_deltamstep_dpll_core addr(base, 0x48) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" {
|
||||
_ 12 mbz;
|
||||
deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part";
|
||||
};
|
||||
|
||||
register cm_ssc_modfreqdiv_dpll_core addr(base, 0x4C) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" {
|
||||
_ 21 mbz;
|
||||
modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor";
|
||||
_ 1 mbz;
|
||||
modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor";
|
||||
};
|
||||
|
||||
register cm_emu_override_dpll_core addr(base, 0x50) "This register provides emulation override controls over the CORE DPLL." {
|
||||
_ 12 mbz;
|
||||
override_enable 1 rw type(dpll_clkout_gate_ctrl_status) "This bit allows to enable or disable the emulation override controls";
|
||||
core_dpll_emu_mult 11 rw type(dpll_en_status) "DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M)";
|
||||
_ 1 mbz;
|
||||
core_dpll_emu_div 7 rw "CORE DPLL override divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
register cm_clkmode_dpll_mpu addr(base, 0x60) "This register allows controlling the DPLL modes." {
|
||||
_ 17 mbz;
|
||||
dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required";
|
||||
dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature";
|
||||
dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking";
|
||||
dpll_regm4xen 1 ro type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled.";
|
||||
dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled.";
|
||||
_ 1 mbz;
|
||||
dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set.";
|
||||
_ 5 mbz;
|
||||
dpll_en 3 rw type(dpll_en_status) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode.";
|
||||
};
|
||||
|
||||
register cm_idlest_dpll_mpu addr(base, 0x64) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status";
|
||||
_ 7 mbz;
|
||||
st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status";
|
||||
};
|
||||
|
||||
register cm_autoidle_dpll_mpu addr(base, 0x68) "This register provides automatic control over the DPLL activity." {
|
||||
_ 29 mbz;
|
||||
auto_dpll_mode 3 rw type(auto_dpll_mode_status) "DPLL automatic control;";
|
||||
};
|
||||
|
||||
constants dcc_en_status width(1) "" {
|
||||
DCC_EN_0 = 0 "DCC disabled";
|
||||
DCC_EN_1 = 1 "DCC enabled";
|
||||
};
|
||||
|
||||
register cm_clksel_dpll_mpu addr(base, 0x6C) "This register provides controls over the DPLL." {
|
||||
dcc_count_max 8 rw "The value 'NbCycles' set in this field determines the duration of the clock ramp step during which the output frequency is Fdpll/(2*M2). The duration is computed as 32 x NbCycles of L4 clock cycles (100 MHz). Duration should be 2.5 us to allow enough time for DCC to lock. This bit field is relevant only when DCC_EN = 1.";
|
||||
dpll_byp_clksel 1 ro "Only CLKINPULOW bypass clock supported for this PLL";
|
||||
dcc_en 1 rw type(dcc_en_status) "Enable or disable duty cycle correction. Must be enabled only for frequency 1 GHz.When enabled, the CLKOUTHIF output of the DPLL is used after duty cycle correction instead of CLKOUT. The M3 divider is hard-wired to 1 so the lock frequency Fdpll is directly provided to MPU. .";
|
||||
_ 3 mbz;
|
||||
dpll_mult 11 rw type(dpll_en_status) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M).";
|
||||
_ 1 mbz;
|
||||
dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
constants dpll_clkout_div_status1 width(5) "" {
|
||||
DPLL_CLKOUT_DIV_0_1 = 0 "Reserved";
|
||||
DPLL_CLKOUT_DIV_1_1 = 1 "1, to be used for OPP100, OPP_TURBO, OPP_NITRO, and OPP_NITROSB";
|
||||
DPLL_CLKOUT_DIV_2_1 = 2 "2, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m2_dpll_mpu addr(base, 0x70) "This register provides controls over the M2 divider of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkout 1 ro type(st_dpll_clkout_status) "DPLL CLKOUT status";
|
||||
dpll_clkout_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUT";
|
||||
_ 2 mbz;
|
||||
dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect";
|
||||
dpll_clkout_div 5 rw type(dpll_clkout_div_status1) "DPLL post-divider factor, M2, for internal clock generation (1 to 31);Divide value from 1 to 31";
|
||||
};
|
||||
|
||||
register cm_ssc_deltamstep_dpll_mpu addr(base, 0x88) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" {
|
||||
_ 12 mbz;
|
||||
deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part";
|
||||
};
|
||||
|
||||
register cm_ssc_modfreqdiv_dpll_mpu addr(base, 0x8C) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" {
|
||||
_ 21 mbz;
|
||||
modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor";
|
||||
_ 1 mbz;
|
||||
modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor";
|
||||
};
|
||||
|
||||
constants clksel_status width(2) "" {
|
||||
CLKSEL_0 = 0 "DPLL_MPU bypass clock is CORE_X2_CLK divided by 1, to be used for OPP100 and OPP50";
|
||||
CLKSEL_1 = 1 "DPLL_MPU bypass clock is CORE_X2_CLK divided by 2";
|
||||
CLKSEL_2 = 2 "DPLL_MPU bypass clock is CORE_X2_CLK divided by 4";
|
||||
CLKSEL_3 = 3 "DPLL_MPU bypass clock is CORE_X2_CLK divided by 8";
|
||||
};
|
||||
|
||||
register cm_bypclk_dpll_mpu addr(base, 0x9C) "Control MPU PLL BYPASS clock. [warm reset insensitive]" {
|
||||
_ 30 mbz;
|
||||
clksel 2 rw type(clksel_status) "Select the DPLL MPU bypass clock";
|
||||
};
|
||||
|
||||
constants dpll_en_status1 width(3) "" {
|
||||
DPLL_EN_0_2 = 0 "Reserved";
|
||||
DPLL_EN_1_2 = 1 "Reserved";
|
||||
DPLL_EN_2_2 = 2 "Reserved";
|
||||
DPLL_EN_3_2 = 3 "Reserved";
|
||||
DPLL_EN_4_2 = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode.";
|
||||
DPLL_EN_5_2 = 5 "Put the DPLL in idle bypass low-power mode.";
|
||||
DPLL_EN_6_2 = 6 "Reserved";
|
||||
DPLL_EN_7_2 = 7 "Enables the DPLL in lock mode";
|
||||
};
|
||||
|
||||
register cm_clkmode_dpll_iva addr(base, 0xA0) "This register allows controlling the DPLL modes." {
|
||||
_ 17 mbz;
|
||||
dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required";
|
||||
dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature";
|
||||
dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking";
|
||||
dpll_regm4xen 1 ro type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled.";
|
||||
dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled.";
|
||||
_ 1 mbz;
|
||||
dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set.";
|
||||
_ 5 mbz;
|
||||
dpll_en 3 rw type(dpll_en_status1) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode.";
|
||||
};
|
||||
|
||||
register cm_idlest_dpll_iva addr(base, 0xA4) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status";
|
||||
_ 7 mbz;
|
||||
st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status";
|
||||
};
|
||||
|
||||
constants auto_dpll_mode_status1 width(3) "" {
|
||||
AUTO_DPLL_MODE_0_2 = 0 "DPLL auto control disabled";
|
||||
AUTO_DPLL_MODE_1_2 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_2_2 = 2 "The DPLL is automatically put in fast-relock stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_3_2 = 3 "Reserved";
|
||||
AUTO_DPLL_MODE_4_2 = 4 "Reserved";
|
||||
AUTO_DPLL_MODE_5_2 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_6_2 = 6 "Reserved";
|
||||
AUTO_DPLL_MODE_7_2 = 7 "Reserved";
|
||||
};
|
||||
|
||||
register cm_autoidle_dpll_iva addr(base, 0xA8) "This register provides automatic control over the DPLL activity." {
|
||||
_ 29 mbz;
|
||||
auto_dpll_mode 3 rw type(auto_dpll_mode_status1) "DPLL automatic control;";
|
||||
};
|
||||
|
||||
register cm_clksel_dpll_iva addr(base, 0xAC) "This register provides controls over the DPLL." {
|
||||
_ 8 mbz;
|
||||
dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2";
|
||||
_ 4 mbz;
|
||||
dpll_mult 11 rw type(dpll_en_status1) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M).";
|
||||
_ 1 mbz;
|
||||
dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout1_div_status1 width(5) "" {
|
||||
HSDIVIDER_CLKOUT1_DIV_0_1 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT1_DIV_2 = 2 "2, to be used for OPP_TURBO and OPP_NITRO";
|
||||
HSDIVIDER_CLKOUT1_DIV_4 = 4 "4, to be used for OPP100";
|
||||
HSDIVIDER_CLKOUT1_DIV_8_1 = 8 "8, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m4_dpll_iva addr(base, 0xB8) "This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout1_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M4 divider and CLKOUT1 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout1 1 ro type(st_dpll_clkout_status) "HSDIVIDER CLKOUT1 status";
|
||||
hsdivider_clkout1_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT1";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout1_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect";
|
||||
hsdivider_clkout1_div 5 rw type(hsdivider_clkout1_div_status1) "DPLL M4 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout2_div_status1 width(5) "" {
|
||||
HSDIVIDER_CLKOUT2_DIV_0_1 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT2_DIV_2 = 2 "2, to be used for OPP_NITRO";
|
||||
HSDIVIDER_CLKOUT2_DIV_3 = 3 "3, to be used for OPP_TURBO";
|
||||
HSDIVIDER_CLKOUT2_DIV_7 = 7 "7, to be used for OPP100";
|
||||
HSDIVIDER_CLKOUT2_DIV_14 = 14 "14, to be used for OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m5_dpll_iva addr(base, 0xBC) "This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout2_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M5 divider and CLKOUT2 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout2 1 ro type(st_dpll_clkout_status) "HSDIVIDER CLKOUT2 status";
|
||||
hsdivider_clkout2_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT2";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout2_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect.";
|
||||
hsdivider_clkout2_div 5 rw type(hsdivider_clkout2_div_status1) "DPLL M5 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
register cm_ssc_deltamstep_dpll_iva addr(base, 0xC8) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" {
|
||||
_ 12 mbz;
|
||||
deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part";
|
||||
};
|
||||
|
||||
register cm_ssc_modfreqdiv_dpll_iva addr(base, 0xCC) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" {
|
||||
_ 21 mbz;
|
||||
modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor";
|
||||
_ 1 mbz;
|
||||
modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor";
|
||||
};
|
||||
|
||||
constants clksel_status1 width(2) "" {
|
||||
CLKSEL_0_1 = 0 "DPLL_IVA bypass clock is CORE_X2_CLK divided by 1, to be used for OPP100 and OPP50";
|
||||
CLKSEL_1_1 = 1 "DPLL_IVA bypass clock is CORE_X2_CLK divided by 2";
|
||||
CLKSEL_2_1 = 2 "DPLL_IVA bypass clock is CORE_X2_CLK divided by 4";
|
||||
CLKSEL_3_1 = 3 "DPLL_IVA bypass clock is CORE_X2_CLK divided by 8";
|
||||
};
|
||||
|
||||
register cm_bypclk_dpll_iva addr(base, 0xDC) "Control IVA PLL BYPASS clock. [warm reset insensitive]" {
|
||||
_ 30 mbz;
|
||||
clksel 2 rw type(clksel_status1) "Select the DPLL IVA bypass clock";
|
||||
};
|
||||
|
||||
register cm_clkmode_dpll_abe addr(base, 0xE0) "This register allows controlling the DPLL modes." {
|
||||
_ 17 mbz;
|
||||
dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required";
|
||||
dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature";
|
||||
dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking";
|
||||
dpll_regm4xen 1 rw type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled.";
|
||||
dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled.";
|
||||
_ 1 mbz;
|
||||
dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set.";
|
||||
_ 5 mbz;
|
||||
dpll_en 3 rw type(dpll_en_status) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode.";
|
||||
};
|
||||
|
||||
register cm_idlest_dpll_abe addr(base, 0xE4) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status";
|
||||
_ 7 mbz;
|
||||
st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status";
|
||||
};
|
||||
|
||||
register cm_autoidle_dpll_abe addr(base, 0xE8) "This register provides automatic control over the DPLL activity." {
|
||||
_ 29 mbz;
|
||||
auto_dpll_mode 3 rw type(auto_dpll_mode_status) "DPLL automatic control;";
|
||||
};
|
||||
|
||||
register cm_clksel_dpll_abe addr(base, 0xEC) "This register provides controls over the DPLL." {
|
||||
_ 8 mbz;
|
||||
dpll_byp_clksel 1 ro "Only CLKINPULOW bypass clock supported for this PLL";
|
||||
_ 4 mbz;
|
||||
dpll_mult 11 rw type(dpll_en_status1) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M).";
|
||||
_ 1 mbz;
|
||||
dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
constants dpll_clkout_div_status2 width(5) "" {
|
||||
DPLL_CLKOUT_DIV_0_2 = 0 "Reserved";
|
||||
DPLL_CLKOUT_DIV_1_2 = 1 "1, to be used for OPP100 and OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m2_dpll_abe addr(base, 0xF0) "This register provides controls over the M2 divider of the DPLL." {
|
||||
_ 20 mbz;
|
||||
st_dpll_clkoutx2 1 ro type(st_dpll_clkout_status) "DPLL CLKOUTX2 status";
|
||||
dpll_clkoutx2_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUTX2";
|
||||
st_dpll_clkout 1 ro type(st_dpll_clkout_status) "DPLL CLKOUT status";
|
||||
dpll_clkout_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUT";
|
||||
_ 2 mbz;
|
||||
dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect.";
|
||||
dpll_clkout_div 5 rw type(dpll_clkout_div_status2) "DPLL post-divider factor, M2, for internal clock generation (1 to 31). Divide value from 1 to 31";
|
||||
};
|
||||
|
||||
register cm_div_m3_dpll_abe addr(base, 0xF4) "This register provides controls over the M3 divider of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkouthif 1 ro type(st_dpll_clkout_status) "DPLL CLKOUTHIF status";
|
||||
dpll_clkouthif_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUTHIF";
|
||||
_ 2 mbz;
|
||||
dpll_clkouthif_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect.";
|
||||
dpll_clkouthif_div 5 rw type(dpll_clkout_div_status2) "DPLL post-divider factor, M3, for internal clock generation (1 to 31). Divide value from 1 to 31";
|
||||
};
|
||||
|
||||
register cm_ssc_deltamstep_dpll_abe addr(base, 0x108) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" {
|
||||
_ 12 mbz;
|
||||
deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part";
|
||||
};
|
||||
|
||||
register cm_ssc_modfreqdiv_dpll_abe addr(base, 0x10C) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" {
|
||||
_ 21 mbz;
|
||||
modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor";
|
||||
_ 1 mbz;
|
||||
modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor";
|
||||
};
|
||||
|
||||
constants dll_reset_status width(1) "" {
|
||||
DLL_RESET_0 = 0 "DLL is not reset during the frequency change hardware sequence";
|
||||
DLL_RESET_1 = 1 "DLL is reset automatically during the frequency change hardware sequence";
|
||||
};
|
||||
|
||||
register cm_shadow_freq_config1 addr(base, 0x160) "Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS. The PRCM h/w automatically applies the new configuration after EMIF/GPMC have been put in idle state." {
|
||||
_ 16 rsvd;
|
||||
dpll_core_m2_div 5 rw type(dpll_clkout_div_status) "Shadow register forCM_DIV_M2_DPLL_CORE.DPLL_CLKOUT_DIV. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. Divide value from 1 to 31.";
|
||||
dpll_core_dpll_en 3 rw type(dpll_en_status) "Shadow register forCM_CLKMODE_DPLL_CORE.DPLL_EN. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1.";
|
||||
_ 4 mbz;
|
||||
dll_reset 1 rw type(dll_reset_status) "Specify if DLL should be reset or not during the frequency change hardware sequence.";
|
||||
dll_override 1 rw type(dll_override_status) "Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1.";
|
||||
_ 1 mbz;
|
||||
freq_update 1 rw "Writing 1 indicates that a new configuration is available. It is automatically cleared by h/w after the configuration has been applied.";
|
||||
};
|
||||
|
||||
constants clksel_l3_status1 width(1) "" {
|
||||
CLKSEL_L3_0_1 = 0 "L3_CLK is CORE_CLK divided by 1";
|
||||
CLKSEL_L3_1_1 = 1 "L3_CLK is CORE_CLK divided by 2";
|
||||
};
|
||||
|
||||
constants clksel_core_status1 width(1) "" {
|
||||
CLKSEL_CORE_0_1 = 0 "CORE_CLK is CORE_X2_CLK divided by 1";
|
||||
CLKSEL_CORE_1_1 = 1 "CORE_CLK is CORE_X2_CLK divided by 2";
|
||||
};
|
||||
|
||||
constants gpmc_freq_update_status width(1) "" {
|
||||
GPMC_FREQ_UPDATE_0 = 0 "GPMC is not put automatically into idle during frequency change operation.";
|
||||
GPMC_FREQ_UPDATE_1 = 1 "GPMC is put automatically into idle during frequency change operation.";
|
||||
};
|
||||
|
||||
register cm_shadow_freq_config2 addr(base, 0x164) "Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS. The PRCM h/w automatically applies the new configuration after EMIF/GPMC have been put in idle state." {
|
||||
_ 24 mbz;
|
||||
dpll_core_m5_div 5 rw type(dpll_clkout_div_status) "Shadow register forCM_DIV_M5_DPLL_CORE.HSDIVIDER_CLKOUT2_DIV. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_UPDATE is set to 1. Divide value from 1 to 31.";
|
||||
clksel_l3 1 rw type(clksel_l3_status1) "Shadow register forCM_CLKSEL_CORE.CLKSEL_L3. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_UPDATE is set to 1.";
|
||||
clksel_core 1 rw type(clksel_core_status1) "Shadow register forCM_CLKSEL_CORE.CLKSEL_CORE. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_UPDATE is set to 1.";
|
||||
gpmc_freq_update 1 rw type(gpmc_freq_update_status) "Controls whether or not GPMC has to be put automatically into idle during the frequency change operation.";
|
||||
};
|
||||
|
||||
register cm_dyn_dep_prescal addr(base, 0x170) "Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)." {
|
||||
_ 26 mbz;
|
||||
prescal 6 rw "Time unit is equal to (PRESCAL + 1) L4 clock cycles.";
|
||||
};
|
||||
|
||||
register cm_restore_st addr(base, 0x180) "Automatic restore status. This register is used by the system DMA to write a predefined value at the end of end automatic restore phase. [warm reset insensitive]" {
|
||||
_ 29 mbz;
|
||||
phase2b_completed 1 rw "Indicates if restore phase 2b is completed. Must be cleared by software before going to device OFF mode.";
|
||||
phase2a_completed 1 rw "Indicates if restore phase 2a is completed. Must be cleared by software before going to device OFF mode.";
|
||||
phase1_completed 1 rw "Indicates if restore phase 1 is completed. Must be cleared by software before going to device OFF mode.";
|
||||
};
|
||||
};
|
||||
420
devices/omap/omap44xx_ckgen_cm2.dev
Normal file
420
devices/omap/omap44xx_ckgen_cm2.dev
Normal file
@ -0,0 +1,420 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_ckgen_cm2.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_ckgen_cm2 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants clksel_status width(1) "" {
|
||||
CLKSEL_0 = 0 "Root clock is sourced from CORE_CLK";
|
||||
CLKSEL_1 = 1 "Functional clock is sourced from DPLL_PER";
|
||||
};
|
||||
|
||||
register cm_clksel_mpu_m3_iss_root addr(base, 0x0) "MPU_A3/ISS root clock selection (MPU_A3_ISS_CLK)." {
|
||||
_ 31 mbz;
|
||||
clksel 1 rw type(clksel_status) "Select the source for the root clock of MPU_A3/ISS";
|
||||
};
|
||||
|
||||
constants clksel_status1 width(1) "" {
|
||||
CLKSEL_0_1 = 0 "Set the divider in bypass mode to support bypass clock from DPLL_USB to pass through without division.";
|
||||
CLKSEL_1_1 = 1 "Set the divider to divide the DPLL o/p (480 MHz typical) by 8 to generate 60-MHz clock, to be used for OPP100 and OPP50.";
|
||||
};
|
||||
|
||||
register cm_clksel_usb_60mhz addr(base, 0x4) "Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p." {
|
||||
_ 31 mbz;
|
||||
clksel 1 rw type(clksel_status1) "Select the configuration of the divider";
|
||||
};
|
||||
|
||||
constants scale_fclk_status width(1) "" {
|
||||
SCALE_FCLK_0 = 0 "The functional clocks run at their default frequencies";
|
||||
SCALE_FCLK_1 = 1 "The functional clocks run at half their typical frequencies";
|
||||
};
|
||||
|
||||
register cm_scale_fclk addr(base, 0x8) "This register can be used to scale PER_ABE_NC_FCLK, 96M_FCLK, 48M_FCLK, and 64M_FCLK to half their respective typical frequencies." {
|
||||
_ 31 mbz;
|
||||
scale_fclk 1 rw type(scale_fclk_status) "Enable or disable the functional clock scaling.";
|
||||
};
|
||||
|
||||
register cm_core_dvfs_perf1 addr(base, 0x10) "This register allows to system master #1 to specify which level of performance is required from CORE domain (mainly external memory throughput?)" {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_core_dvfs_perf2 addr(base, 0x14) "This register allows to system master #2 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_core_dvfs_perf3 addr(base, 0x18) "This register allows to system master #3 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_core_dvfs_perf4 addr(base, 0x1C) "This register allows to system master #4 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_core_dvfs_current addr(base, 0x24) "This register hold the current level of performance achievable by the CORE domain, according to the current OPP setting" {
|
||||
_ 24 mbz;
|
||||
perf_current 8 rw "Current achievable performance level. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_iva_dvfs_perf_dsp addr(base, 0x28) "This register allows to specify which level of performance is required from IVA domain for DSP to operate." {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_iva_dvfs_perf_ivahd addr(base, 0x2C) "This register allows to specify which level of performance is required from IVA domain for IVAHD to operate." {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_iva_dvfs_perf_abe addr(base, 0x30) "This register allows to specify which level of performance is required from IVA domain for ABE to operate." {
|
||||
_ 24 mbz;
|
||||
perf_req 8 rw "Current performance request. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
register cm_iva_dvfs_current addr(base, 0x38) "This register hold the current level of performance achievable by the IVA domain, according to the current OPP setting" {
|
||||
_ 24 mbz;
|
||||
perf_current 8 rw "Current achievable performance level. Unit to be defined by user.";
|
||||
};
|
||||
|
||||
constants dpll_ssc_downspread_status width(1) "" {
|
||||
DPLL_SSC_DOWNSPREAD_0 = 0 "When SSC is enabled, clock frequency is spread on both sides of the programmed frequency";
|
||||
DPLL_SSC_DOWNSPREAD_1 = 1 "When SSC is enabled, clock frequency is spread only on the lower side of the programmed frequency";
|
||||
};
|
||||
|
||||
constants dpll_ssc_ack_status width(1) "" {
|
||||
DPLL_SSC_ACK_0_r = 0 "SSC has been turned off on PLL o/ps";
|
||||
DPLL_SSC_ACK_1_r = 1 "SSC has been turned on on PLL o/ps";
|
||||
};
|
||||
|
||||
constants dpll_ssc_en_status width(1) "" {
|
||||
DPLL_SSC_EN_0 = 0 "SSC disabled";
|
||||
DPLL_SSC_EN_1 = 1 "SSC enabled";
|
||||
};
|
||||
|
||||
constants dpll_regm4xen_status width(1) "" {
|
||||
DPLL_REGM4XEN_0_r = 0 "REGM4XEN mode of the DPLL is disabled";
|
||||
};
|
||||
|
||||
constants dpll_lpmode_en_status width(1) "" {
|
||||
DPLL_LPMODE_EN_0 = 0 "Low-power mode of the DPLL is disabled";
|
||||
DPLL_LPMODE_EN_1 = 1 "Low-power mode of the DPLL is enabled";
|
||||
};
|
||||
|
||||
constants dpll_driftguard_en_status width(1) "" {
|
||||
DPLL_DRIFTGUARD_EN_0 = 0 "DRIFTGUARD feature is disabled";
|
||||
DPLL_DRIFTGUARD_EN_1 = 1 "DRIFTGUARD feature is enabled";
|
||||
};
|
||||
|
||||
constants dpll_en_status width(3) "" {
|
||||
DPLL_EN_0 = 0 "Reserved";
|
||||
DPLL_EN_1 = 1 "Reserved";
|
||||
DPLL_EN_2 = 2 "Reserved";
|
||||
DPLL_EN_3 = 3 "Reserved";
|
||||
DPLL_EN_4 = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode.";
|
||||
DPLL_EN_5 = 5 "Put the DPLL in idle bypass low-power mode.";
|
||||
DPLL_EN_6 = 6 "Put the DPLL in idle bypass fast-relock mode.";
|
||||
DPLL_EN_7 = 7 "Enables the DPLL in lock mode";
|
||||
};
|
||||
|
||||
register cm_clkmode_dpll_per addr(base, 0x40) "This register allows controlling the DPLL modes." {
|
||||
_ 17 mbz;
|
||||
dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required";
|
||||
dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature";
|
||||
dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking";
|
||||
dpll_regm4xen 1 ro type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled.";
|
||||
dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled.";
|
||||
_ 1 mbz;
|
||||
dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set.";
|
||||
_ 5 mbz;
|
||||
dpll_en 3 rw type(dpll_en_status) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode.";
|
||||
};
|
||||
|
||||
constants st_mn_bypass_status width(1) "" {
|
||||
ST_MN_BYPASS_1_r = 1 "DPLL is in MN_Bypass";
|
||||
ST_MN_BYPASS_0_r = 0 "DPLL is not in MN_Bypass";
|
||||
};
|
||||
|
||||
constants st_dpll_clk_status width(1) "" {
|
||||
ST_DPLL_CLK_1_r = 1 "DPLL is LOCKED";
|
||||
ST_DPLL_CLK_0_r = 0 "DPLL is either in bypass mode or in stop mode.";
|
||||
};
|
||||
|
||||
register cm_idlest_dpll_per addr(base, 0x44) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status";
|
||||
_ 7 mbz;
|
||||
st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status";
|
||||
};
|
||||
|
||||
constants auto_dpll_mode_status width(3) "" {
|
||||
AUTO_DPLL_MODE_0 = 0 "DPLL auto control disabled";
|
||||
AUTO_DPLL_MODE_1 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_2 = 2 "The DPLL is automatically put in fast-relock stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_3 = 3 "Reserved";
|
||||
AUTO_DPLL_MODE_4 = 4 "Reserved";
|
||||
AUTO_DPLL_MODE_5 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_6 = 6 "The DPLL is automatically put in idle bypass fast-relock mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_7 = 7 "Reserved";
|
||||
};
|
||||
|
||||
register cm_autoidle_dpll_per addr(base, 0x48) "This register provides automatic control over the DPLL activity." {
|
||||
_ 29 mbz;
|
||||
auto_dpll_mode 3 rw type(auto_dpll_mode_status) "DPLL automatic control;";
|
||||
};
|
||||
|
||||
register cm_clksel_dpll_per addr(base, 0x4C) "This register provides controls over the DPLL." {
|
||||
_ 8 mbz;
|
||||
dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2";
|
||||
_ 4 mbz;
|
||||
dpll_mult 11 rw type(dpll_en_status) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M).";
|
||||
_ 1 mbz;
|
||||
dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
constants st_dpll_clkoutx2_status width(1) "" {
|
||||
ST_DPLL_CLKOUTX2_0_r = 0 "The clock output is gated";
|
||||
ST_DPLL_CLKOUTX2_1_r = 1 "The clock output is enabled";
|
||||
};
|
||||
|
||||
constants dpll_clkout_div_status width(5) "" {
|
||||
DPLL_CLKOUT_DIV_0 = 0 "Reserved";
|
||||
DPLL_CLKOUT_DIV_4 = 4 "4, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 768 MHz)";
|
||||
DPLL_CLKOUT_DIV_8 = 8 "8, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 1536 MHz)";
|
||||
};
|
||||
|
||||
register cm_div_m2_dpll_per addr(base, 0x50) "This register provides controls over the M2 divider of the DPLL." {
|
||||
_ 20 mbz;
|
||||
st_dpll_clkoutx2 1 ro type(st_dpll_clkoutx2_status) "DPLL CLKOUTX2 status";
|
||||
dpll_clkoutx2_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUTX2";
|
||||
st_dpll_clkout 1 ro type(st_dpll_clkoutx2_status) "DPLL CLKOUT status";
|
||||
dpll_clkout_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUT";
|
||||
_ 2 mbz;
|
||||
dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect.";
|
||||
dpll_clkout_div 5 rw type(dpll_clkout_div_status) "DPLL post-divider factor, M2, for internal clock generation (1 to 31)";
|
||||
};
|
||||
|
||||
constants st_dpll_clkouthif_status width(1) "" {
|
||||
ST_DPLL_CLKOUTHIF_0_r = 0 "The clock output is gated.";
|
||||
ST_DPLL_CLKOUTHIF_1_r = 1 "The clock output is enabled.";
|
||||
};
|
||||
|
||||
constants dpll_clkouthif_div_status width(5) "" {
|
||||
DPLL_CLKOUTHIF_DIV_0 = 0 "Reserved";
|
||||
DPLL_CLKOUTHIF_DIV_3 = 3 "3, to be used for OPP100 (when DPLL_PER is locked at 768 MHz)";
|
||||
DPLL_CLKOUTHIF_DIV_4 = 4 "4, to be used for OPP50 (when DPLL_PER is locked at 768 MHz)";
|
||||
DPLL_CLKOUTHIF_DIV_6 = 6 "6, to be used for OPP100 (when DPLL_PER is locked at 1536 MHz)";
|
||||
DPLL_CLKOUTHIF_DIV_8 = 8 "8, to be used for OPP50 (when DPLL_PER is locked at 1536 MHz)";
|
||||
};
|
||||
|
||||
register cm_div_m3_dpll_per addr(base, 0x54) "This register provides controls over the M3 divider of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkouthif 1 ro type(st_dpll_clkouthif_status) "DPLL CLKOUTHIF status";
|
||||
dpll_clkouthif_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUTHIF";
|
||||
_ 2 mbz;
|
||||
dpll_clkouthif_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect.";
|
||||
dpll_clkouthif_div 5 rw type(dpll_clkouthif_div_status) "DPLL post-divider factor, M3, for internal clock generation (1 to 31). The values listed below (3, 4, 6 and 8) are used for maximum supported frequency at each OPP. Higher dividers (max 31), thus lower frequencies, are also supported.";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout1_pwdn_status width(1) "" {
|
||||
HSDIVIDER_CLKOUT1_PWDN_0 = 0 "Divider is powered up";
|
||||
HSDIVIDER_CLKOUT1_PWDN_1 = 1 "Divider is powered down";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout1_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT1_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT1_DIV_6 = 6 "6, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 768 MHz)";
|
||||
HSDIVIDER_CLKOUT1_DIV_12 = 12 "12, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 1536 MHz)";
|
||||
};
|
||||
|
||||
register cm_div_m4_dpll_per addr(base, 0x58) "This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout1_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M4 divider and CLKOUT1 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout1 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT1 status";
|
||||
hsdivider_clkout1_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT1";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout1_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect.";
|
||||
hsdivider_clkout1_div 5 rw type(hsdivider_clkout1_div_status) "DPLL M4 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout2_pwdn_status width(1) "" {
|
||||
HSDIVIDER_CLKOUT2_PWDN_0 = 0 "Divider is powered up.";
|
||||
HSDIVIDER_CLKOUT2_PWDN_1 = 1 "Divider is powered down.";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout2_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT2_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT2_DIV_5 = 5 "5, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 768 MHz)";
|
||||
HSDIVIDER_CLKOUT2_DIV_9 = 9 "9, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 1536 MHz)";
|
||||
};
|
||||
|
||||
register cm_div_m5_dpll_per addr(base, 0x5C) "This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout2_pwdn 1 rw type(hsdivider_clkout2_pwdn_status) "Direct power down control for HSDIVIDER M5 divider and CLKOUT2 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout2 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT2 status";
|
||||
hsdivider_clkout2_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT2";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout2_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect.";
|
||||
hsdivider_clkout2_div 5 rw type(hsdivider_clkout2_div_status) "DPLL M5 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout3_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT3_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT3_DIV_2 = 2 "2, to be used for OPP100 (when DPLL_PER is locked at 768 MHz)";
|
||||
HSDIVIDER_CLKOUT3_DIV_4 = 4 "4, to be used for OPP100 (when DPLL_PER is locked at 1536 MHz) and for OPP50 (when DPLL_PER is locked at 768 MHz)";
|
||||
HSDIVIDER_CLKOUT3_DIV_8 = 8 "8, to be used for OPP50 (when DPLL_PER is locked at 1536 MHz)";
|
||||
};
|
||||
|
||||
register cm_div_m6_dpll_per addr(base, 0x60) "This register provides controls over the CLKOUT3 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout3_pwdn 1 rw type(hsdivider_clkout2_pwdn_status) "Direct power down control for HSDIVIDER M6 divider and CLKOUT3 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout3 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT3 status";
|
||||
hsdivider_clkout3_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT3";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout3_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect.";
|
||||
hsdivider_clkout3_div 5 rw type(hsdivider_clkout3_div_status) "DPLL M6 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
constants hsdivider_clkout4_div_status width(5) "" {
|
||||
HSDIVIDER_CLKOUT4_DIV_0 = 0 "Reserved";
|
||||
HSDIVIDER_CLKOUT4_DIV_3 = 3 "3, to be used for OPP100 (when DPLL_PER is locked at 768 MHz)";
|
||||
HSDIVIDER_CLKOUT4_DIV_5 = 5 "5, to be used for OPP100 (when DPLL_PER is locked at 1536 MHz)";
|
||||
HSDIVIDER_CLKOUT4_DIV_6 = 6 "6, to be used for OPP50 (when DPLL_PER is locked at 768 MHz)";
|
||||
HSDIVIDER_CLKOUT4_DIV_10 = 10 "10, to be used for OPP50 (when DPLL_PER is locked at 1536 MHz)";
|
||||
};
|
||||
|
||||
register cm_div_m7_dpll_per addr(base, 0x64) "This register provides controls over the CLKOUT4 o/p of the HSDIVIDER." {
|
||||
_ 19 mbz;
|
||||
hsdivider_clkout4_pwdn 1 rw type(hsdivider_clkout2_pwdn_status) "Direct power down control for HSDIVIDER M7 divider and CLKOUT4 output. Power down should be enabled only when clock is first gated.";
|
||||
_ 2 mbz;
|
||||
st_hsdivider_clkout4 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT4 status";
|
||||
hsdivider_clkout4_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT4";
|
||||
_ 2 mbz;
|
||||
hsdivider_clkout4_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect.";
|
||||
hsdivider_clkout4_div 5 rw type(hsdivider_clkout4_div_status) "DPLL M7 post-divider factor (1 to 31)";
|
||||
};
|
||||
|
||||
register cm_ssc_deltamstep_dpll_per addr(base, 0x68) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" {
|
||||
_ 12 mbz;
|
||||
deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part";
|
||||
};
|
||||
|
||||
register cm_ssc_modfreqdiv_dpll_per addr(base, 0x6C) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" {
|
||||
_ 21 mbz;
|
||||
modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor";
|
||||
_ 1 mbz;
|
||||
modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor";
|
||||
};
|
||||
|
||||
constants dpll_en_status1 width(3) "" {
|
||||
DPLL_EN_0_1 = 0 "Reserved";
|
||||
DPLL_EN_1_1 = 1 "Put the DPLL in low-power stop mode";
|
||||
DPLL_EN_2_1 = 2 "Reserved2";
|
||||
DPLL_EN_3_1 = 3 "Reserved";
|
||||
DPLL_EN_4_1 = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode.";
|
||||
DPLL_EN_5_1 = 5 "Put the DPLL in idle bypass low-power mode.";
|
||||
DPLL_EN_6_1 = 6 "Reserved";
|
||||
DPLL_EN_7_1 = 7 "Enables the DPLL in lock mode";
|
||||
};
|
||||
|
||||
register cm_clkmode_dpll_usb addr(base, 0x80) "This register allows controlling the DPLL modes." {
|
||||
_ 17 mbz;
|
||||
dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required";
|
||||
dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature";
|
||||
dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking";
|
||||
_ 9 mbz;
|
||||
dpll_en 3 rw type(dpll_en_status1) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect DPLL low-power stop mode.";
|
||||
};
|
||||
|
||||
register cm_idlest_dpll_usb addr(base, 0x84) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" {
|
||||
_ 23 mbz;
|
||||
st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status";
|
||||
_ 7 mbz;
|
||||
st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status";
|
||||
};
|
||||
|
||||
constants auto_dpll_mode_status1 width(3) "" {
|
||||
AUTO_DPLL_MODE_0_1 = 0 "DPLL auto control disabled";
|
||||
AUTO_DPLL_MODE_1_1 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_2_1 = 2 "Reserved";
|
||||
AUTO_DPLL_MODE_3_1 = 3 "Reserved";
|
||||
AUTO_DPLL_MODE_4_1 = 4 "Reserved";
|
||||
AUTO_DPLL_MODE_5_1 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically.";
|
||||
AUTO_DPLL_MODE_6_1 = 6 "Reserved";
|
||||
AUTO_DPLL_MODE_7_1 = 7 "Reserved";
|
||||
};
|
||||
|
||||
register cm_autoidle_dpll_usb addr(base, 0x88) "This register provides automatic control over the DPLL activity." {
|
||||
_ 29 mbz;
|
||||
auto_dpll_mode 3 rw type(auto_dpll_mode_status1) "DPLL automatic control;";
|
||||
};
|
||||
|
||||
register cm_clksel_dpll_usb addr(base, 0x8C) "This register provides controls over the DPLL." {
|
||||
dpll_sd_div 8 rw type(dpll_en_status) "Sigma-Delta divider select (2-255). This factor must be set by s/w to ensure optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP / 250), where CLKINP is the input clock of the DPLL in MHz). Must be set with M and N factors, and must not be changed once DPLL is locked.";
|
||||
dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT";
|
||||
_ 3 mbz;
|
||||
dpll_mult 12 rw type(dpll_en_status) "DPLL multiplier factor (2 to 4095). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 4095 = DPLL multiplies by M).";
|
||||
dpll_div 8 rw "DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1).";
|
||||
};
|
||||
|
||||
constants dpll_clkout_div_status1 width(7) "" {
|
||||
DPLL_CLKOUT_DIV_0_1 = 0 "Reserved";
|
||||
DPLL_CLKOUT_DIV_2 = 2 "2, to be used for OPP100 and OPP50";
|
||||
};
|
||||
|
||||
register cm_div_m2_dpll_usb addr(base, 0x90) "This register provides controls over the M2 divider of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkout 1 ro type(st_dpll_clkouthif_status) "DPLL CLKOUT status";
|
||||
dpll_clkout_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUT";
|
||||
dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect.";
|
||||
dpll_clkout_div 7 rw type(dpll_clkout_div_status1) "DPLL post-divider factor, M2, for internal clock generation (1 to 127)";
|
||||
};
|
||||
|
||||
register cm_ssc_deltamstep_dpll_usb addr(base, 0xA8) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" {
|
||||
_ 11 mbz;
|
||||
deltamstep 21 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [20:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part";
|
||||
};
|
||||
|
||||
register cm_ssc_modfreqdiv_dpll_usb addr(base, 0xAC) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" {
|
||||
_ 21 mbz;
|
||||
modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor";
|
||||
_ 1 mbz;
|
||||
modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor";
|
||||
};
|
||||
|
||||
register cm_clkdcoldo_dpll_usb addr(base, 0xB4) "This register provides controls over the CLKDCOLDO output of the DPLL." {
|
||||
_ 22 mbz;
|
||||
st_dpll_clkdcoldo 1 ro type(st_dpll_clkoutx2_status) "DPLL CLKDCOLDO status";
|
||||
dpll_clkdcoldo_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKDCOLDO";
|
||||
_ 8 mbz;
|
||||
};
|
||||
};
|
||||
76
devices/omap/omap44xx_ckgen_prm.dev
Normal file
76
devices/omap/omap44xx_ckgen_prm.dev
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_ckgen_prm.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_ckgen_prm msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants clksel_status width(1) "" {
|
||||
CLKSEL_0 = 0 "Select SYS_CLK divided by 1";
|
||||
CLKSEL_1 = 1 "Select SYS_CLK divided by 2 Must be used for SYS_CLK > 26 MHz";
|
||||
};
|
||||
|
||||
register cm_abe_dss_sys_clksel addr(base, 0x0) "Select the SYS CLK for ABE and DSS subsystems. [warm reset insensitive]" {
|
||||
_ 31 mbz;
|
||||
clksel 1 rw type(clksel_status) "Selects the divider value";
|
||||
};
|
||||
|
||||
constants clksel_status1 width(1) "" {
|
||||
CLKSEL_0_1 = 0 "Selects SYS_CLK for L4WKUP_ICLK Selects SYS_CLK for ABE_DPLL_BYPASS_CLK";
|
||||
CLKSEL_1_1 = 1 "Selects ABE_LP_CLK for L4WKUP_ICLK Selects 32K_FCLK for ABE_DPLL_BYPASS_CLK";
|
||||
};
|
||||
|
||||
register cm_l4_wkup_clksel addr(base, 0x8) "Control the functional clock source of L4_WKUP, PRM and Smart Reflex functional clock." {
|
||||
_ 31 mbz;
|
||||
clksel 1 rw type(clksel_status1) "Select the clock source for L4WKUP_ICLK and for ABE_DPLL_BYPASS_CLK clocks.";
|
||||
};
|
||||
|
||||
constants clksel_status2 width(1) "" {
|
||||
CLKSEL_0_2 = 0 "Selects SYS_CLK";
|
||||
CLKSEL_1_2 = 1 "Selects SYS_32K";
|
||||
};
|
||||
|
||||
register cm_abe_pll_ref_clksel addr(base, 0xC) "Control the source of the reference clock for DPLL_ABE" {
|
||||
_ 31 mbz;
|
||||
clksel 1 rw type(clksel_status2) "Select the source for the DPLL_ABE reference clock.";
|
||||
};
|
||||
|
||||
constants sys_clksel_status width(3) "" {
|
||||
SYS_CLKSEL_0 = 0 "Uninitialized";
|
||||
SYS_CLKSEL_1 = 1 "Input clock is 12 MHz";
|
||||
SYS_CLKSEL_2 = 2 "Reserved";
|
||||
SYS_CLKSEL_3 = 3 "Input clock is 16.8 MHz";
|
||||
SYS_CLKSEL_4 = 4 "Input clock is 19.2 MHz";
|
||||
SYS_CLKSEL_5 = 5 "Input clock is 26 MHz";
|
||||
SYS_CLKSEL_6 = 6 "Reserved";
|
||||
SYS_CLKSEL_7 = 7 "Input clock is 38.4 MHz";
|
||||
};
|
||||
|
||||
register cm_sys_clksel addr(base, 0x10) "Software sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK. [warm reset insensitive]" {
|
||||
_ 29 mbz;
|
||||
sys_clksel 3 rw type(sys_clksel_status) "System clock input selection.";
|
||||
};
|
||||
};
|
||||
115
devices/omap/omap44xx_clk1_clk1_targ_pwr_disc_clk2.dev
Normal file
115
devices/omap/omap44xx_clk1_clk1_targ_pwr_disc_clk2.dev
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk1_clk1_targ_pwr_disc_clk2.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk1_clk1_targ_pwr_disc_clk2 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x38.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stdhosthdr_mainctlreg addr(base, 0x8) "" {
|
||||
_ 27 mbz;
|
||||
_ 1 mbz;
|
||||
stdhosthdr_mainctlreg_cm 1 ro "Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0.";
|
||||
stdhosthdr_mainctlreg_flt 1 ro "Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
};
|
||||
|
||||
constants stderrlog_svrtstdlvl_0_status width(2) "" {
|
||||
STDERRLOG_SVRTSTDLVL_0_0 = 0 "Error logging is disabled.";
|
||||
STDERRLOG_SVRTSTDLVL_0_1 = 1 "Errors are logged with severity level Error.";
|
||||
STDERRLOG_SVRTSTDLVL_0_2 = 2 "Errors are logged with severity level Fault.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_svrtstdlvl addr(base, 0x40) "" {
|
||||
_ 30 mbz;
|
||||
stderrlog_svrtstdlvl_0 2 rw type(stderrlog_svrtstdlvl_0_status) "Severity level parameters Type: Control. Reset value: 0x2.";
|
||||
};
|
||||
|
||||
constants stderrlog_main_errtype_status width(1) "" {
|
||||
STDERRLOG_MAIN_ERRTYPE_0_r = 0 "Logged Error format is standard (header and necker recorded).";
|
||||
STDERRLOG_MAIN_ERRTYPE_1_r = 1 "Logged Error format is module dependent. CustomInfo register(s) may be implemented to store additional information.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_main addr(base, 0x48) "" {
|
||||
stderrlog_main_clrlog 1 rw "Clears Error Logging Valid bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0.";
|
||||
_ 11 mbz;
|
||||
stderrlog_main_fltcnt 1 rw "Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0.";
|
||||
stderrlog_main_errcnt 1 rw "Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0.";
|
||||
_ 16 mbz;
|
||||
stderrlog_main_errtype 1 ro type(stderrlog_main_errtype_status) "Indicates logging type. Type: Status. Reset value: X.";
|
||||
stderrlog_main_errlogvld 1 ro "Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_hdr addr(base, 0x4C) "" {
|
||||
_ 8 mbz;
|
||||
stderrlog_hdr_len1 6 ro "This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
stderrlog_hdr_stopofswrpsz 4 ro "StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X.";
|
||||
stderrlog_hdr_err 1 ro "Err bit of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 4 mbz;
|
||||
stderrlog_hdr_pressure 1 ro "Pressure field of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
stderrlog_hdr_opcode 4 ro "Opcode of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_mstaddr addr(base, 0x50) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_mstaddr 8 ro "Master Address field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_slvaddr addr(base, 0x54) "" {
|
||||
_ 27 mbz;
|
||||
stderrlog_slvaddr 5 ro "Slave Address field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_info addr(base, 0x58) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_info 8 ro "Info field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_pwr_disc_stderrlog_slvofslsb ro addr(base, 0x5C) "" type(uint32);
|
||||
|
||||
register l3_pwr_disc_stderrlog_slvofsmsb addr(base, 0x60) "" {
|
||||
_ 31 mbz;
|
||||
stderrlog_slvofsmsb 1 ro "MSB of the slave offset field of the logged packet (according to NTTP packet format, this register field may exceed the actual slave offset size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X.";
|
||||
};
|
||||
};
|
||||
146
devices/omap/omap44xx_clk1_dmm1_targ.dev
Normal file
146
devices/omap/omap44xx_clk1_dmm1_targ.dev
Normal file
@ -0,0 +1,146 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk1_dmm1_targ.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk1_dmm1_targ msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_targ_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_targ_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_targ_stdhosthdr_mainctlreg addr(base, 0x8) "" {
|
||||
_ 27 mbz;
|
||||
_ 1 mbz;
|
||||
stdhosthdr_mainctlreg_cm 1 ro "Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0.";
|
||||
stdhosthdr_mainctlreg_flt 1 ro "Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X.";
|
||||
_ 1 mbz;
|
||||
stdhosthdr_mainctlreg_en 1 rw "Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_targ_stdhosthdr_nttpaddr_0 addr(base, 0x10) "" {
|
||||
_ 27 mbz;
|
||||
stdhosthdr_nttpaddr_0 5 ro "Sets the RX port address. Type: Control. Reset value: 0x15.";
|
||||
};
|
||||
|
||||
constants stderrlog_svrtstdlvl_0_status width(2) "" {
|
||||
STDERRLOG_SVRTSTDLVL_0_0 = 0 "Error logging is disabled.";
|
||||
STDERRLOG_SVRTSTDLVL_0_1 = 1 "Errors are logged with severity level Error.";
|
||||
STDERRLOG_SVRTSTDLVL_0_2 = 2 "Errors are logged with severity level Fault.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_svrtstdlvl addr(base, 0x40) "" {
|
||||
_ 30 mbz;
|
||||
stderrlog_svrtstdlvl_0 2 rw type(stderrlog_svrtstdlvl_0_status) "Severity level parameters Type: Control. Reset value: 0x2.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_svrtcustomlvl addr(base, 0x44) "" {
|
||||
_ 30 mbz;
|
||||
stderrlog_svrtcustomlvl_0 2 rw type(stderrlog_svrtstdlvl_0_status) "Severity level parameters Type: Control. Reset value: 0x2.";
|
||||
};
|
||||
|
||||
constants stderrlog_main_errtype_status width(1) "" {
|
||||
STDERRLOG_MAIN_ERRTYPE_0_r = 0 "Logged Error format is standard (header and necker recorded).";
|
||||
STDERRLOG_MAIN_ERRTYPE_1_r = 1 "Logged Error format is module dependent. CustomInfo register(s) may be implemented to store additional information.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_main addr(base, 0x48) "" {
|
||||
stderrlog_main_clrlog 1 rw "Clears Error Logging Valid bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0.";
|
||||
_ 11 mbz;
|
||||
stderrlog_main_fltcnt 1 rw "Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0.";
|
||||
stderrlog_main_errcnt 1 rw "Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0.";
|
||||
_ 16 mbz;
|
||||
stderrlog_main_errtype 1 ro type(stderrlog_main_errtype_status) "Indicates logging type. Type: Status. Reset value: X.";
|
||||
stderrlog_main_errlogvld 1 ro "Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_hdr addr(base, 0x4C) "" {
|
||||
_ 8 mbz;
|
||||
stderrlog_hdr_len1 6 ro "This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
stderrlog_hdr_stopofswrpsz 4 ro "StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X.";
|
||||
stderrlog_hdr_err 1 ro "Err bit of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 4 mbz;
|
||||
stderrlog_hdr_pressure 1 ro "Pressure field of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
stderrlog_hdr_opcode 4 ro "Opcode of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_mstaddr addr(base, 0x50) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_mstaddr 8 ro "Master Address field of the logged packet. (see) Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_slvaddr addr(base, 0x54) "" {
|
||||
_ 27 mbz;
|
||||
stderrlog_slvaddr 5 ro "Slave Address field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_info addr(base, 0x58) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_info 8 ro "Info field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_slvofslsb ro addr(base, 0x5C) "" type(uint32);
|
||||
|
||||
register l3_targ_stderrlog_slvofsmsb addr(base, 0x60) "" {
|
||||
_ 31 mbz;
|
||||
stderrlog_slvofsmsb 1 ro "MSB of the slave offset field of the logged packet (according to NTTP packet format, this register field may exceed the actual slave offset size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_custominfo_info addr(base, 0x64) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_custominfo_info 8 ro "Info field of the response packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_custominfo_mstaddr addr(base, 0x68) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_custominfo_mstaddr 8 ro "MstAddr field of the response packet. (see) Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_stderrlog_custominfo_opcode addr(base, 0x6C) "" {
|
||||
_ 30 mbz;
|
||||
stderrlog_custominfo_opcode 2 ro "Opcode of the response packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_targ_addrspacesizelog addr(base, 0x80) "" {
|
||||
_ 27 mbz;
|
||||
addrspacesizelog 5 rw "The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F.";
|
||||
};
|
||||
};
|
||||
68
devices/omap/omap44xx_clk1_dss_bw_regulator.dev
Normal file
68
devices/omap/omap44xx_clk1_dss_bw_regulator.dev
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk1_dss_bw_regulator.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk1_dss_bw_regulator msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_bw_r_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_bw_r_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_bw_r_bandwidth addr(base, 0x8) "" {
|
||||
_ 16 mbz;
|
||||
bandwidth 16 rw "Bandwidth, in bytes per second. Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_bw_r_watermark addr(base, 0xC) "" {
|
||||
_ 20 mbz;
|
||||
watermark 12 rw "Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_bw_r_press addr(base, 0x10) "" {
|
||||
_ 30 mbz;
|
||||
press_low 1 ro "Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0.";
|
||||
press_high 1 ro "Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_bw_r_clearhistory addr(base, 0x14) "" {
|
||||
_ 31 mbz;
|
||||
clearhistory 1 rw "Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0.";
|
||||
};
|
||||
};
|
||||
67
devices/omap/omap44xx_clk1_flagmux_clk1.dev
Normal file
67
devices/omap/omap44xx_clk1_flagmux_clk1.dev
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk1_flagmux_clk1.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk1_flagmux_clk1 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_flagmux_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_flagmux_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_flagmux_mask0 addr(base, 0x8) "" {
|
||||
_ 14 mbz;
|
||||
mask0 18 rw "Mask flag inputs 0 Type: Control. Reset value: 0x3FFFF.";
|
||||
};
|
||||
|
||||
register l3_flagmux_regerr0 addr(base, 0xC) "" {
|
||||
_ 14 mbz;
|
||||
regerr0 18 ro "Flag inputs 0 Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_flagmux_mask1 addr(base, 0x10) "" {
|
||||
_ 14 mbz;
|
||||
mask1 18 rw "Mask flag inputs 1 Type: Control. Reset value: 0x3FFFF.";
|
||||
};
|
||||
|
||||
register l3_flagmux_regerr1 addr(base, 0x14) "" {
|
||||
_ 14 mbz;
|
||||
regerr1 18 ro "Flag inputs 1 Type: Status. Reset value: X.";
|
||||
};
|
||||
};
|
||||
143
devices/omap/omap44xx_clk1_host_clk1.dev
Normal file
143
devices/omap/omap44xx_clk1_host_clk1.dev
Normal file
@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk1_host_clk1.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk1_host_clk1 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_host_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_host_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_host_stdhosthdr_mainctlreg addr(base, 0x8) "" {
|
||||
_ 29 mbz;
|
||||
stdhosthdr_mainctlreg_flt 1 ro "Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
};
|
||||
|
||||
constants stderrlog_svrtstdlvl_0_status width(2) "" {
|
||||
STDERRLOG_SVRTSTDLVL_0_0 = 0 "Error logging is disabled.";
|
||||
STDERRLOG_SVRTSTDLVL_0_1 = 1 "Errors are logged with severity level Error.";
|
||||
STDERRLOG_SVRTSTDLVL_0_2 = 2 "Errors are logged with severity level Fault.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_svrtstdlvl addr(base, 0x40) "" {
|
||||
_ 30 mbz;
|
||||
stderrlog_svrtstdlvl_0 2 rw type(stderrlog_svrtstdlvl_0_status) "Severity level parameters Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_svrtcustomlvl addr(base, 0x44) "" {
|
||||
_ 30 mbz;
|
||||
stderrlog_svrtcustomlvl_0 2 rw type(stderrlog_svrtstdlvl_0_status) "Severity level parameters Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants stderrlog_main_errtype_status width(1) "" {
|
||||
STDERRLOG_MAIN_ERRTYPE_0_r = 0 "Logged Error format is standard (header and necker recorded).";
|
||||
STDERRLOG_MAIN_ERRTYPE_1_r = 1 "Logged Error format is module dependent. CustomInfo register(s) may be implemented to store additional information.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_main addr(base, 0x48) "" {
|
||||
stderrlog_main_clrlog 1 rw "Clears Error Logging Valid bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0.";
|
||||
_ 11 mbz;
|
||||
stderrlog_main_fltcnt 1 rw "Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0.";
|
||||
stderrlog_main_errcnt 1 rw "Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0.";
|
||||
_ 16 mbz;
|
||||
stderrlog_main_errtype 1 ro type(stderrlog_main_errtype_status) "Indicates logging type. Type: Status. Reset value: X.";
|
||||
stderrlog_main_errlogvld 1 ro "Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_hdr addr(base, 0x4C) "" {
|
||||
_ 8 mbz;
|
||||
stderrlog_hdr_len1 6 ro "This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
stderrlog_hdr_stopofswrpsz 4 ro "StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X.";
|
||||
stderrlog_hdr_err 1 ro "Err bit of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 4 mbz;
|
||||
stderrlog_hdr_pressure 1 ro "Pressure field of the logged packet. Type: Status. Reset value: X.";
|
||||
_ 2 mbz;
|
||||
stderrlog_hdr_opcode 4 ro "Opcode of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_mstaddr addr(base, 0x50) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_mstaddr 8 ro "Master Address field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_slvaddr addr(base, 0x54) "" {
|
||||
_ 27 mbz;
|
||||
stderrlog_slvaddr 5 ro "Slave Address field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_info addr(base, 0x58) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_info 8 ro "Info field of the logged packet. Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_slvofslsb ro addr(base, 0x5C) "" type(uint32);
|
||||
|
||||
register l3_host_stderrlog_slvofsmsb addr(base, 0x60) "" {
|
||||
_ 31 mbz;
|
||||
stderrlog_slvofsmsb 1 ro "MSB of the slave offset field of the logged packet (according to NTTP packet format, this register field may exceed the actual slave offset size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_custominfo_mstaddr addr(base, 0x64) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_custominfo_mstaddr 8 ro "Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_custominfo_info addr(base, 0x68) "" {
|
||||
_ 24 mbz;
|
||||
stderrlog_custominfo_info 8 ro "Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_custominfo_wr addr(base, 0x6C) "" {
|
||||
_ 31 mbz;
|
||||
stderrlog_custominfo_wr 1 ro "Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_custominfo_addr addr(base, 0x70) "" {
|
||||
_ 11 mbz;
|
||||
stderrlog_custominfo_addr 21 ro "Type: Status. Reset value: X.";
|
||||
};
|
||||
|
||||
register l3_host_stderrlog_custominfo_decerr addr(base, 0x74) "" {
|
||||
_ 31 mbz;
|
||||
stderrlog_custominfo_decerr 1 ro "Type: Status. Reset value: X.";
|
||||
};
|
||||
};
|
||||
53
devices/omap/omap44xx_clk1_rate_adapt_resp_32to128_clk1.dev
Normal file
53
devices/omap/omap44xx_clk1_rate_adapt_resp_32to128_clk1.dev
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk1_rate_adapt_resp_32to128_clk1.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk1_rate_adapt_resp_32to128_clk1 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_ra_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2D.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_ra_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_ra_cnf addr(base, 0x8) "" {
|
||||
_ 27 mbz;
|
||||
cnf_rate 4 rw "Indicates the throughput ratio between input and output (Rate = [16 x (Incoming_Throughput/Outgoing_Throuput)] - 1), when bit StAndFwd bit is reset. Ignored when StAndFwd bit is set. Type: Control. Reset value: 0x3.";
|
||||
cnf_standfwd 1 rw "When this bit is set, the Packet Transport Unit stores the entire NTTP packet, then forwards it on TX port. Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
};
|
||||
224
devices/omap/omap44xx_clk3_statcoll_lat0.dev
Normal file
224
devices/omap/omap44xx_clk3_statcoll_lat0.dev
Normal file
@ -0,0 +1,224 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk3_statcoll_lat0.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk3_statcoll_lat0 msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_stcol_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_stcol_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_stcol_en addr(base, 0x8) "" {
|
||||
_ 31 mbz;
|
||||
en 1 rw "Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_soften addr(base, 0xC) "" {
|
||||
_ 31 mbz;
|
||||
soften 1 rw "Software enable for performance monitoring Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_trigen addr(base, 0x14) "" {
|
||||
_ 31 mbz;
|
||||
trigen 1 rw "TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants reqevt_status width(4) "" {
|
||||
REQEVT_0 = 0 "Collect is disabled default value";
|
||||
REQEVT_1 = 1 "Collect all event: hit always (cycle)";
|
||||
REQEVT_2 = 2 "Collect transfers: actually used cycle for transferring aN NTTP word";
|
||||
REQEVT_3 = 3 "Collect wait cycle: transfer has been delayed by source";
|
||||
REQEVT_4 = 4 "Collect busy: transfer has been delayed by destination";
|
||||
REQEVT_5 = 5 "Collect packet: new packet start";
|
||||
REQEVT_6 = 6 "Collect data: data cycle transfer, write for requests, read for responses";
|
||||
REQEVT_7 = 7 "Collect idles: transfer is not initiated by source";
|
||||
REQEVT_8 = 8 "Collect latency: hit when actually detecting debug bit on response links";
|
||||
};
|
||||
|
||||
register l3_stcol_reqevt addr(base, 0x18) "" {
|
||||
_ 28 mbz;
|
||||
reqevt 4 rw type(reqevt_status) "Req event select Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_rspevt addr(base, 0x1C) "" {
|
||||
_ 28 mbz;
|
||||
rspevt 4 rw type(reqevt_status) "Rsp event select Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel0 addr(base, 0x20) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel0 3 rw "The select of the mux 0 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel1 addr(base, 0x24) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel1 3 rw "The select of the mux 1 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel2 addr(base, 0x28) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel2 3 rw "The select of the mux 2 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel3 addr(base, 0x2C) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel3 3 rw "The select of the mux 3 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_identifier addr(base, 0x40) "" {
|
||||
_ 30 mbz;
|
||||
dump_identifier 2 ro "Probe identifier Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_collecttime addr(base, 0x44) "" {
|
||||
_ 16 mbz;
|
||||
dump_collecttime 16 rw "Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_slvaddr addr(base, 0x48) "" {
|
||||
_ 27 mbz;
|
||||
dump_slvaddr 5 ro "Dump slave address Type: Control. Reset value: 0x19.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_mstaddr addr(base, 0x4C) "" {
|
||||
_ 24 mbz;
|
||||
dump_mstaddr 8 ro "Dump master address Type: Control. Reset value: 0xE0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_slvofs rw addr(base, 0x50) "" type(uint32);
|
||||
|
||||
register l3_stcol_dump_manual addr(base, 0x54) "" {
|
||||
_ 31 mbz;
|
||||
dump_manual 1 rw "Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_send addr(base, 0x58) "" {
|
||||
_ 31 mbz;
|
||||
dump_send 1 rw "In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_globalen addr(base, 0xAC) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_globalen 1 rw "Filter global enable Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_en_k addr(base, 0xBC) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_en0 1 rw "Enable filter stage 0 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_rd addr(base, 0xC0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_mask_m_rd 1 rw "Mask/Match of Rd Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_wr addr(base, 0xC4) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_mask_m_wr 1 rw "Mask/Match of Wr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_mstaddr addr(base, 0xC8) "" {
|
||||
_ 24 mbz;
|
||||
filter_i_mask_m_mstaddr 8 rw "Mask/Match of MstAddr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_err addr(base, 0xD0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_mask_m_err 1 rw "Mask/Match of Err Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_rd addr(base, 0xE0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_match_m_rd 1 rw "Mask/Match of Rd Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_wr addr(base, 0xE4) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_match_m_wr 1 rw "Mask/Match of Wr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_mstaddr addr(base, 0xE8) "" {
|
||||
_ 24 mbz;
|
||||
filter_i_match_m_mstaddr 8 rw "Mask/Match of MstAddr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_err addr(base, 0xF0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_match_m_err 1 rw "Mask/Match of Err Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_threshold_minval addr(base, 0x1F0) "" {
|
||||
_ 20 mbz;
|
||||
op_i_threshold_minval 12 rw "Min value Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_threshold_maxval addr(base, 0x1F4) "" {
|
||||
_ 20 mbz;
|
||||
op_i_threshold_maxval 12 rw "Max value Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants op_i_evtinfosel_status width(2) "" {
|
||||
OP_i_EVTINFOSEL_0 = 0 "Select len from event info list";
|
||||
OP_i_EVTINFOSEL_1 = 1 "Select pressure if available from event info list";
|
||||
OP_i_EVTINFOSEL_2 = 2 "Select latency if available from event info list";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_evtinfosel addr(base, 0x1F8) "" {
|
||||
_ 30 mbz;
|
||||
op_i_evtinfosel 2 rw type(op_i_evtinfosel_status) "Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants op_i_sel_status width(4) "" {
|
||||
OP_i_SEL_0 = 0 "Increment counter on each mask/match filter hit";
|
||||
OP_i_SEL_1 = 1 "Increment counter on each min/max level hit";
|
||||
OP_i_SEL_2 = 2 "Add to counter the selected event info value (len/press or latency)";
|
||||
OP_i_SEL_3 = 3 "increment counter when all filter event hits (And(Fi))";
|
||||
OP_i_SEL_4 = 4 "Increment counter if any of filter event hits (Or(Fi))";
|
||||
OP_i_SEL_5 = 5 "Add to counter the number of current request event that hit";
|
||||
OP_i_SEL_6 = 6 "Add to counter the number of current response event that hit";
|
||||
OP_i_SEL_7 = 7 "Add to counter the number of all event that hit";
|
||||
OP_i_SEL_8 = 8 "Increment counter on each selected external event hit";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_sel addr(base, 0x1FC) "" {
|
||||
_ 28 mbz;
|
||||
op_i_sel 4 rw type(op_i_sel_status) "Select logical operation Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
};
|
||||
254
devices/omap/omap44xx_clk3_statcoll_sdram.dev
Normal file
254
devices/omap/omap44xx_clk3_statcoll_sdram.dev
Normal file
@ -0,0 +1,254 @@
|
||||
/*
|
||||
* Copyright (c) 2013 ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
|
||||
* Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_clk3_statcoll_sdram.dev
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* NOTE: This file has been automatically generated based on the
|
||||
* XML files extracted from the TI RDT v1.0.0.4p Tool.
|
||||
* Download from here: http://www.ti.com/product/omap4460
|
||||
* This means that the file might not be optimal in terms of naming
|
||||
* conventions for constants and registers (duplicated
|
||||
* namespaces in register and device name etc.).
|
||||
* Also, because of the underlying structure from the original XML
|
||||
* it's possible that some constants appear multiple times (if they
|
||||
* have slightly different descriptions for example).
|
||||
*
|
||||
* You want to clean that up before using the files for the first time!
|
||||
*/
|
||||
|
||||
device omap44xx_clk3_statcoll_sdram msbfirst ( addr base ) "" {
|
||||
|
||||
|
||||
constants stdhosthdr_corereg_vendorcode_status width(1) "" {
|
||||
STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor.";
|
||||
STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 "";
|
||||
};
|
||||
|
||||
register l3_stcol_stdhosthdr_corereg addr(base, 0x0) "" {
|
||||
_ 10 mbz;
|
||||
stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A.";
|
||||
_ 15 mbz;
|
||||
stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1.";
|
||||
};
|
||||
|
||||
register l3_stcol_stdhosthdr_versionreg addr(base, 0x4) "" {
|
||||
stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0.";
|
||||
stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved.";
|
||||
};
|
||||
|
||||
register l3_stcol_en addr(base, 0x8) "" {
|
||||
_ 31 mbz;
|
||||
en 1 rw "Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_soften addr(base, 0xC) "" {
|
||||
_ 31 mbz;
|
||||
soften 1 rw "Software enable for performance monitoring Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_trigen addr(base, 0x14) "" {
|
||||
_ 31 mbz;
|
||||
trigen 1 rw "TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants reqevt_status width(4) "" {
|
||||
REQEVT_0 = 0 "Collect is disabled default value";
|
||||
REQEVT_1 = 1 "Collect all event: hit always (cycle)";
|
||||
REQEVT_2 = 2 "Collect transfers: actually used cycle for transferring aN NTTP word";
|
||||
REQEVT_3 = 3 "Collect wait cycle: transfer has been delayed by source";
|
||||
REQEVT_4 = 4 "Collect busy: transfer has been delayed by destination";
|
||||
REQEVT_5 = 5 "Collect packet: new packet start";
|
||||
REQEVT_6 = 6 "Collect data: data cycle transfer, write for requests, read for responses";
|
||||
REQEVT_7 = 7 "Collect idles: transfer is not initiated by source";
|
||||
REQEVT_8 = 8 "Collect latency: hit when actually detecting debug bit on response links";
|
||||
};
|
||||
|
||||
register l3_stcol_reqevt addr(base, 0x18) "" {
|
||||
_ 28 mbz;
|
||||
reqevt 4 rw type(reqevt_status) "Req event select Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_rspevt addr(base, 0x1C) "" {
|
||||
_ 28 mbz;
|
||||
rspevt 4 rw type(reqevt_status) "Rsp event select Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel0 addr(base, 0x20) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel0 3 rw "The select of the mux 0 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel1 addr(base, 0x24) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel1 3 rw "The select of the mux 1 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel2 addr(base, 0x28) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel2 3 rw "The select of the mux 2 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel3 addr(base, 0x2C) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel3 3 rw "The select of the mux 3 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_evtmux_sel4 addr(base, 0x30) "" {
|
||||
_ 29 mbz;
|
||||
evtmux_sel4 3 rw "The select of the mux 4 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_identifier addr(base, 0x40) "" {
|
||||
_ 30 mbz;
|
||||
dump_identifier 2 ro "Probe identifier Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_collecttime addr(base, 0x44) "" {
|
||||
_ 16 mbz;
|
||||
dump_collecttime 16 rw "Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_slvaddr addr(base, 0x48) "" {
|
||||
_ 27 mbz;
|
||||
dump_slvaddr 5 ro "Dump slave address Type: Control. Reset value: 0x19.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_mstaddr addr(base, 0x4C) "" {
|
||||
_ 24 mbz;
|
||||
dump_mstaddr 8 ro "Dump master address Type: Control. Reset value: 0xE0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_slvofs rw addr(base, 0x50) "" type(uint32);
|
||||
|
||||
register l3_stcol_dump_manual addr(base, 0x54) "" {
|
||||
_ 31 mbz;
|
||||
dump_manual 1 rw "Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_dump_send addr(base, 0x58) "" {
|
||||
_ 31 mbz;
|
||||
dump_send 1 rw "In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_globalen addr(base, 0xAC) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_globalen 1 rw "Filter global enable Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_addrmin addr(base, 0xB0) "" {
|
||||
_ 9 rsvd;
|
||||
filter1_addrmin 23 rw "min addr range Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_addrmax addr(base, 0xB4) "" {
|
||||
_ 9 rsvd;
|
||||
filter1_addrmax 23 rw "max addr range Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_addren addr(base, 0xB8) "" {
|
||||
_ 31 rsvd;
|
||||
filter1_addren 1 rw "max filtering enable Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_en_k addr(base, 0xBC) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_en0 1 rw "Enable filter stage 0 Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_rd addr(base, 0xC0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_mask_m_rd 1 rw "Mask/Match of Rd Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_wr addr(base, 0xC4) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_mask_m_wr 1 rw "Mask/Match of Wr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_mstaddr addr(base, 0xC8) "" {
|
||||
_ 24 mbz;
|
||||
filter_i_mask_m_mstaddr 8 rw "Mask/Match of MstAddr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_err addr(base, 0xD0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_mask_m_err 1 rw "Mask/Match of Err Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_mask_m_userinfo addr(base, 0xD4) "" {
|
||||
_ 14 mbz;
|
||||
filter_i_mask_m_userinfo 18 rw "Mask/Match of UserInfo Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_rd addr(base, 0xE0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_match_m_rd 1 rw "Mask/Match of Rd Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_wr addr(base, 0xE4) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_match_m_wr 1 rw "Mask/Match of Wr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_mstaddr addr(base, 0xE8) "" {
|
||||
_ 24 mbz;
|
||||
filter_i_match_m_mstaddr 8 rw "Mask/Match of MstAddr Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_err addr(base, 0xF0) "" {
|
||||
_ 31 mbz;
|
||||
filter_i_match_m_err 1 rw "Mask/Match of Err Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_filter_i_match_m_userinfo addr(base, 0xF4) "" {
|
||||
_ 14 mbz;
|
||||
filter_i_match_m_userinfo 18 rw "Mask/Match of UserInfo Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_threshold_minval addr(base, 0x1F0) "" {
|
||||
_ 20 mbz;
|
||||
op_i_threshold_minval 12 rw "Min value Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_threshold_maxval addr(base, 0x1F4) "" {
|
||||
_ 20 mbz;
|
||||
op_i_threshold_maxval 12 rw "Max value Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants op_i_evtinfosel_status width(2) "" {
|
||||
OP_i_EVTINFOSEL_0 = 0 "Select len from event info list";
|
||||
OP_i_EVTINFOSEL_1 = 1 "Select pressure if available from event info list";
|
||||
OP_i_EVTINFOSEL_2 = 2 "Select latency if available from event info list";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_evtinfosel addr(base, 0x1F8) "" {
|
||||
_ 30 mbz;
|
||||
op_i_evtinfosel 2 rw type(op_i_evtinfosel_status) "Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
|
||||
constants op_i_sel_status width(4) "" {
|
||||
OP_i_SEL_0 = 0 "Increment counter on each mask/match filter hit";
|
||||
OP_i_SEL_1 = 1 "Increment counter on each min/max level hit";
|
||||
OP_i_SEL_2 = 2 "Add to counter the selected event info value (len/press or latency)";
|
||||
OP_i_SEL_3 = 3 "increment counter when all filter event hits (And(Fi))";
|
||||
OP_i_SEL_4 = 4 "Increment counter if any of filter event hits (Or(Fi))";
|
||||
OP_i_SEL_5 = 5 "Add to counter the number of current request event that hit";
|
||||
OP_i_SEL_6 = 6 "Add to counter the number of current response event that hit";
|
||||
OP_i_SEL_7 = 7 "Add to counter the number of all event that hit";
|
||||
OP_i_SEL_8 = 8 "Increment counter on each selected external event hit";
|
||||
};
|
||||
|
||||
register l3_stcol_op_i_sel addr(base, 0x1FC) "" {
|
||||
_ 28 mbz;
|
||||
op_i_sel 4 rw type(op_i_sel_status) "Select logical operation Type: Control. Reset value: 0x0.";
|
||||
};
|
||||
};
|
||||
76
devices/omap/omap44xx_cm2.dev
Normal file
76
devices/omap/omap44xx_cm2.dev
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2012, ETH Zurich. All rights reserved.
|
||||
*
|
||||
* This file is distributed under the terms in the attached LICENSE file.
|
||||
* If you do not find this file, copies can be found by writing to:
|
||||
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
|
||||
*/
|
||||
|
||||
/*
|
||||
* omap44xx_cm2.dev
|
||||
*
|
||||
* DESCRIPTION: Power Management Framework (PandaBoard)
|
||||
*
|
||||
* See:
|
||||
* OMAP4430 Multimedia Device Silicon Revision 2.x Technical Reference Manual (Rev. 0)
|
||||
* Chapter: 3.6.3.2.4 and 3.11.29 - 3.11.40
|
||||
* Registers: Table 3-1286 on page 918
|
||||
*
|
||||
*/
|
||||
|
||||
device omap44xx_cm2 msbfirst (addr cm2_base, addr cm2_clkgen_base, addr l4per_base) "TI CM2 Clock Generator" {
|
||||
|
||||
/*
|
||||
* Ignoring the remaining bits, since we don't use them ..
|
||||
* see table 3-1287, page 918
|
||||
* XXX need to add output for L{3,4}_ICLK to see if it is turned on
|
||||
*/
|
||||
register CM_L3INIT_CLKSTCTRL addr(cm2_base, 0x0) "Enable power state transitions" {
|
||||
_ 14;
|
||||
CLKACTIVITY_INIT_HSMMC1_FCLK 1 ro "State of functional clock for MMC1";
|
||||
_ 15;
|
||||
CLKTRCTRL 2 rw "Clock state transition of L3INIT clock domain";
|
||||
};
|
||||
|
||||
register CM_L3INIT_HSMMC1_CLKCTRL addr(cm2_base, 0x28) "management of MMC1 clocks" {
|
||||
_ 7;
|
||||
CLKSEL 1 rw "Source of functional clock";
|
||||
_ 5;
|
||||
STBYST 1 ro "Standby status";
|
||||
IDLEST 2 ro "Idel status";
|
||||
_ 14;
|
||||
MODULEMODE 2 rw "Clock management mode";
|
||||
};
|
||||
|
||||
register CM_DIV_M4_DPLL_PER addr(cm2_clkgen_base, 0x58) "Control over CLKOUT1 of HSDIVIDER" {
|
||||
_ 19;
|
||||
HSDIVIDER_CLKOUT1_PWDN 1 rw "Power control for M4 divider";
|
||||
_ 2;
|
||||
ST_HSDIVIDER_CLKOUT1 1 ro "Status of HSDIVIDER CLKOUT1";
|
||||
HSDIVIDER_CLKOUT1_GATE_CTRL 1 rw "Control gating of HSDIVIDER CLKOUT1";
|
||||
_ 2;
|
||||
HSDIVIDER_CLKOUT1_DIVCHACK 1 ro "Toggle on this status bit after changing CLKOUT1_DIV";
|
||||
HSDIVIDER_CLKOUT1_DIV 5 rw "DPLL M4 post-divider factor";
|
||||
};
|
||||
|
||||
constants idlest "Idle Status" {
|
||||
idlest_functional = 0b00 "Module is fully functional";
|
||||
idlest_transition = 0b01 "Module is performing transition";
|
||||
idlest_idle = 0b10 "Module is in idle mode. It's functional when using separate FCLK.";
|
||||
idlest_disabled = 0b11 "Module is disabled";
|
||||
};
|
||||
constants modmode "Module mandatory clock control" {
|
||||
modmode_swdisabled = 0b00 "Module is disabled by software";
|
||||
modmode_swenabled = 0b10 "Module is explicitly enabled";
|
||||
};
|
||||
regtype clkctrl "clock control" {
|
||||
_ 14 rsvd;
|
||||
idlest 2 type(idlest) "Module idle status";
|
||||
_ 14 rsvd;
|
||||
modulemode 2 type(modmode) "Mandatory clock control";
|
||||
};
|
||||
register l4per_i2c1_clkctrl addr(l4per_base, 0xa0) type(clkctrl);
|
||||
register l4per_i2c2_clkctrl addr(l4per_base, 0xa8) type(clkctrl);
|
||||
register l4per_i2c3_clkctrl addr(l4per_base, 0xb0) type(clkctrl);
|
||||
register l4per_i2c4_clkctrl addr(l4per_base, 0xb8) type(clkctrl);
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user