96 lines
2.7 KiB
Plaintext
96 lines
2.7 KiB
Plaintext
/*
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* Copyright (c) 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* ac97_ext_codec.dev
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*
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* DESCRIPTION: AC'97 Extended Codec Register Set
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*
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* Numbers in comments refer to the Intel Audio Codec '97 specification,
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* revision 2.3 revision 1.0, April, 2002
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*/
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device ac97_ext_codec msbfirst ( io base ) "AC97 Extended Codec" {
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// 5.9.1
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register classrev ro io( base, 0x60 ) "Codec class/rev" {
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rv 8 "Revision ID";
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cl 5 "Codec compatibility class";
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_ 3 rsvd;
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};
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register pcisvid ro io( base, 0x62 ) "PCI SVID" type(uint16);
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register pcisid ro io( base, 0x64 ) "PCI SID" type(uint16);
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// 5.9.2
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constants fncode "Function code" {
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dac1 = 0 "DAC 1 (master out)";
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dac2 = 1 "DAC 2 (aux out)";
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dac3 = 2 "DAC 3 (C/LFE)";
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spdif = 3 "S/PDIF out";
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phone = 4 "Phone in";
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mic1 = 5 "Mic 1 (mic select=0)";
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mic2 = 6 "Mic 2 (mic select=1)";
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line = 7 "Line in";
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cd = 8 "CD in";
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video = 9 "Video in";
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aux = 10 "Aux in";
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mono = 11 "Mono out";
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};
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register fnsel io( base, 0x66 ) "Function select" {
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tr 1 "Tip or ring select";
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fc 4 type(fncode) "Function code";
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_ 11 rsvd;
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};
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register fninf io( base, 0x68 ) "Function information" {
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fip 1 "Function information present";
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_ 3 rsvd;
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iv 1 "Information valid";
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dl 5 "Buffer delays in 20.84us units";
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inv 1 "Inversion";
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g 5 "Gain or attenuation";
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};
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constants jackloc "Connector/jack location" {
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rear = 0 "Rear I/O panel";
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front = 1 "Front panel";
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mother = 2 "Motherboard";
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dock = 3 "Dock/External";
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none = 7 "No connection";
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};
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register sensedet io( base, 0x6a ) "Sense details" {
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sr 6 ro "Sense result";
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or 2 rw "Sense result order bits";
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// XXX These have complicated meanings not specified here (yet)
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s 5 ro "Sensed bits";
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st 3 rw type(jackloc) "Connector/jack location";
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};
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// 5.9.3
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constants slot "Slot mapping descriptor" {
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s0 = 0 "None/not implemented";
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s34 = 3 "Slot 3/4 (3 for mono)";
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s69 = 6 "Slot 6/9 (6 for mono)";
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s7 = 7 "Slot 7,8 (7 for mono)";
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sa = 10 "Slot 10/11 (10 for mono)";
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};
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register dacslot io ( base, 0x6c ) "DAC slot mapping" {
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_ 4;
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cld 4 type(slot) "DAC 3 (center/LFE)";
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sd 4 type(slot) "DAC 2 (surround)";
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fd 4 type(slot) "DAC 1 (front/headphone)";
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};
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register adcslot io ( base, 0x6e ) "ADC slot mapping" {
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mv 1 "Mapping valid";
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_ 7;
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ima 4 type(slot) "Independent mic";
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lia 4 type(slot) "Line in";
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};
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};
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