77 lines
3.4 KiB
Plaintext
77 lines
3.4 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* omap44xx_cm2.dev
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*
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* DESCRIPTION: Power Management Framework (PandaBoard)
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*
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* See:
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* OMAP4430 Multimedia Device Silicon Revision 2.x Technical Reference Manual (Rev. 0)
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* Chapter: 3.6.3.2.4 and 3.11.29 - 3.11.40
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* Registers: Table 3-1286 on page 918
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*
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*/
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device omap44xx_cm2 msbfirst (addr cm2_base, addr cm2_clkgen_base, addr l4per_base) "TI CM2 Clock Generator" {
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/*
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* Ignoring the remaining bits, since we don't use them ..
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* see table 3-1287, page 918
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* XXX need to add output for L{3,4}_ICLK to see if it is turned on
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*/
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register CM_L3INIT_CLKSTCTRL addr(cm2_base, 0x0) "Enable power state transitions" {
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_ 14;
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CLKACTIVITY_INIT_HSMMC1_FCLK 1 ro "State of functional clock for MMC1";
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_ 15;
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CLKTRCTRL 2 rw "Clock state transition of L3INIT clock domain";
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};
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register CM_L3INIT_HSMMC1_CLKCTRL addr(cm2_base, 0x28) "management of MMC1 clocks" {
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_ 7;
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CLKSEL 1 rw "Source of functional clock";
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_ 5;
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STBYST 1 ro "Standby status";
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IDLEST 2 ro "Idel status";
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_ 14;
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MODULEMODE 2 rw "Clock management mode";
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};
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register CM_DIV_M4_DPLL_PER addr(cm2_clkgen_base, 0x58) "Control over CLKOUT1 of HSDIVIDER" {
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_ 19;
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HSDIVIDER_CLKOUT1_PWDN 1 rw "Power control for M4 divider";
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_ 2;
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ST_HSDIVIDER_CLKOUT1 1 ro "Status of HSDIVIDER CLKOUT1";
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HSDIVIDER_CLKOUT1_GATE_CTRL 1 rw "Control gating of HSDIVIDER CLKOUT1";
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_ 2;
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HSDIVIDER_CLKOUT1_DIVCHACK 1 ro "Toggle on this status bit after changing CLKOUT1_DIV";
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HSDIVIDER_CLKOUT1_DIV 5 rw "DPLL M4 post-divider factor";
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};
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constants idlest "Idle Status" {
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idlest_functional = 0b00 "Module is fully functional";
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idlest_transition = 0b01 "Module is performing transition";
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idlest_idle = 0b10 "Module is in idle mode. It's functional when using separate FCLK.";
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idlest_disabled = 0b11 "Module is disabled";
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};
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constants modmode "Module mandatory clock control" {
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modmode_swdisabled = 0b00 "Module is disabled by software";
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modmode_swenabled = 0b10 "Module is explicitly enabled";
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};
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regtype clkctrl "clock control" {
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_ 14 rsvd;
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idlest 2 type(idlest) "Module idle status";
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_ 14 rsvd;
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modulemode 2 type(modmode) "Mandatory clock control";
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};
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register l4per_i2c1_clkctrl addr(l4per_base, 0xa0) type(clkctrl);
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register l4per_i2c2_clkctrl addr(l4per_base, 0xa8) type(clkctrl);
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register l4per_i2c3_clkctrl addr(l4per_base, 0xb0) type(clkctrl);
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register l4per_i2c4_clkctrl addr(l4per_base, 0xb8) type(clkctrl);
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};
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