69 lines
2.1 KiB
Plaintext
69 lines
2.1 KiB
Plaintext
/*
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* Copyright (c) 2015, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* apm88xxxx/apm88xxxx_pc16550.dev
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*
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* DESCRIPTION: APM88xxxx PC16550 UART
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*
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* This is derived from:
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*
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* APM88xx0x Processor Family Register Reference -- Volume 1
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* Document Issue 0.98 (APM 2012-0052-1)
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*
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* This file only incorporates the parts relevant for UART operation.
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* Registers relevant for IrDA, CIR, and other modes are not yet
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* described.
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*/
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device apm88xxxx_pc16550 msbfirst (addr base) "APM88xxxx UART" {
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constants data_len "Data Length" {
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bits5 = 0b00 "5 Bits";
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bits6 = 0b01 "6 Bits";
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bits7 = 0b10 "7 Bits";
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bits8 = 0b11 "8 Bits";
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};
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register RBR ro addr (base, 0x0) "Receive Buffer" {
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_ 24;
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rbr 8 ro "Receive buffer register";
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};
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register THR wo also addr (base, 0x0) "Transmit Register" {
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_ 24;
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thr 8 wo "Transmit register";
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};
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register IIR ro addr (base, 0x8) "Interrupt Identity" type(uint32);
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register lcr rw addr (base, 0xc) "Line control" {
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_ 24;
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dlab 1 "Divisor latch access bit";
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bc 1 "Break control bit";
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sp 1 rsvd "Stick parity";
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eps 1 "Even parity select";
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pen 1 "Parity enable";
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stop 1 "stop bit";
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dls 2 type(data_len) "Data length select";
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};
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register LSR ro addr (base, 0x14) "Line Status" {
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_ 24;
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rfe 1 "Receive FIFO error";
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temt 1 "Transmitter empty";
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thre 1 "Transmit holding register empty";
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bi 1 "Break interrupt";
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fe 1 "Framing error";
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pe 1 "Parity error";
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oe 1 "Overrun error";
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dr 1 "Data ready";
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};
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};
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