67 lines
3.0 KiB
Plaintext
67 lines
3.0 KiB
Plaintext
/*
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* Copyright (c) 2014, University of Washington. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* megaraid.dev
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*
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* DESCRIPTION: LSI MegaRAID Controller
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*
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* From the FreeBSD driver.
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*/
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device megaraid msbfirst ( addr base ) "LSI MegaRAID Controller" {
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register doorbell rw addr(base, 0x0) "Doorbell" type(uint32);
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register fusion_seq_offset rw addr(base, 0x4) "Fusion SEQ Offset" type (uint32);
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register fusion_host_diag rw addr(base, 0x8) "Fusion Host Diag" type (uint32);
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register inbound_msg_0 rw addr(base, 0x10) "Inbound msg 0" type (uint32);
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register inbound_msg_1 rw addr(base, 0x14) "Inbound msg 0" type (uint32);
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register outbound_msg_0 rw addr(base, 0x18) "Outbound msg 0" type (uint32);
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register outbound_msg_1 rw addr(base, 0x1c) "Outbound msg 1" type (uint32);
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register inbound_doorbell rw addr(base, 0x20) "Inbound doorbell" type (uint32);
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register inbound_intr_status rw addr(base, 0x24) "Inbound interrupt status" type (uint32);
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register inbound_intr_mask rw addr(base, 0x28) "Inbound interrupt mask" type (uint32);
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register outbound_doorbell rw addr(base, 0x2c) "Outbound doorbell" type (uint32);
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register outbound_intr_status rw addr(base, 0x30) "Outbound interrupt status" type (uint32);
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register outbound_intr_mask rw addr(base, 0x34) "Outbound interrupt mask" type (uint32);
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register inbound_queue_port rw addr(base, 0x40) "Inbound queue port" type (uint32);
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register outbound_queue_port rw addr(base, 0x44) "Outbound queue port" type (uint32);
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register reply_post_host_index rw addr(base, 0x6c) "Reply post host index" type (uint32);
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register outbound_doorbell_clear rw addr(base, 0xa0) "Outbound doorbell clear" type (uint32);
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constants state "Controller state" {
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state_undefined = 0x0 "Undefined";
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state_bb_init = 0x1 "BB Init";
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state_fw_init = 0x4 "FW Init";
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state_wait_handshake = 0x6 "Wait handshake";
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state_fw_init_2 = 0x7 "FW Init 2";
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state_device_scane = 0x8 "Device scan";
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state_boot_msg_pending = 0x9 "Boot message pending";
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state_flush_cache = 0xa "Flush cache";
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state_ready = 0xb "Ready";
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state_operational = 0xc "Operational";
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state_fault = 0xf "Fault";
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};
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register status ro addr(base, 0xb0) "Device status" {
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state 4 type(state) "Controller status";
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_ 4;
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sge 8;
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max_cmds 16 "Max. # of commands";
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};
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register outbound_scratch_pad_2 rw addr(base, 0xb4) "Outbound scratch pad #2" type (uint32);
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register inbound_low_queue_port rw addr(base, 0xc0) "Inbound low queue port" type (uint32);
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register inbound_high_queue_port rw addr(base, 0xc4) "Inbound high queue port" type (uint32);
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};
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