71 lines
2.1 KiB
Plaintext
71 lines
2.1 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* cortex_a9_pit.dev
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*
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* DESCRIPTION: Cortex A9 Private Timer and watchdog
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*
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* This is derived from:
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*
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* Cortex-A9 MPCore Technical Reference Manual
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* (DDI0407G_cortex_a9_mpcore_r3p0_trm.pdf)
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*
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* This implements private timers and watchdogs
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*/
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device cortex_a9_pit msbfirst ( addr base ) "Cortex A9 Private Timer and watchdog" {
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register TimerLoad addr(base, 0x0) "Private Timer Load Register" type(uint32);
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register TimerCounter addr(base, 0x4) "Private Timer Counter Register" type(uint32);
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register TimerControl addr(base, 0x8) "Private Timer Control Register" {
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_ 16 mbz;
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prescale 8 rw "Prescale factor";
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_ 5 mbz;
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int_enable 1 rw "Interrupt enable bit";
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auto_reload 1 rw "Single shot or reload mode";
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timer_enable 1 rw "Timer enable bit";
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};
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register TimerIntStat addr(base, 0xc) "Private Timer Interrupt Status Register" {
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_ 31 mbz;
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event_flag 1 rw1c;
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};
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register WatchdogLoad addr(base, 0x20) "Watchdog Load Register" type(uint32);
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register WatchdogCounter addr(base, 0x24) "Watchdog Counter Register" type(uint32);
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register WatchdogControl addr(base, 0x28) "Watchdog Control Register" {
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_ 16 mbz;
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prescale 8 rw "Prescale factor";
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_ 4 mbz;
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wd_mode 1 rw "Selects Watchdog or Timer mode";
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int_enable 1 rw "Interrupt enable bit";
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auto_reload 1 rw "Single shot or reload mode";
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wd_enable 1 rw "Timer enable bit";
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};
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register WatchdogIntStat addr(base, 0x2c) "Watchdog Interrupt Status Register" {
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_ 31 mbz;
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event_flag 1 rw1c;
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};
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register WatchdogResStat addr(base, 0x30) "Watchdog Reset Status Register" {
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_ 31 mbz;
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reset_flag 1 rw1c;
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};
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// Write 0x12345678 then 0x87654321 to this register to disable watchdog mode
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register WatchdogDisable wo addr(base, 0x34) "Watchdog Disable Register" type(uint32);
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};
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