76 lines
3.0 KiB
Plaintext
76 lines
3.0 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_ckgen_prm.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_ckgen_prm msbfirst ( addr base ) "" {
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constants clksel_status width(1) "" {
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CLKSEL_0 = 0 "Select SYS_CLK divided by 1";
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CLKSEL_1 = 1 "Select SYS_CLK divided by 2 Must be used for SYS_CLK > 26 MHz";
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};
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register cm_abe_dss_sys_clksel addr(base, 0x0) "Select the SYS CLK for ABE and DSS subsystems. [warm reset insensitive]" {
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_ 31 mbz;
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clksel 1 rw type(clksel_status) "Selects the divider value";
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};
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constants clksel_status1 width(1) "" {
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CLKSEL_0_1 = 0 "Selects SYS_CLK for L4WKUP_ICLK Selects SYS_CLK for ABE_DPLL_BYPASS_CLK";
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CLKSEL_1_1 = 1 "Selects ABE_LP_CLK for L4WKUP_ICLK Selects 32K_FCLK for ABE_DPLL_BYPASS_CLK";
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};
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register cm_l4_wkup_clksel addr(base, 0x8) "Control the functional clock source of L4_WKUP, PRM and Smart Reflex functional clock." {
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_ 31 mbz;
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clksel 1 rw type(clksel_status1) "Select the clock source for L4WKUP_ICLK and for ABE_DPLL_BYPASS_CLK clocks.";
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};
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constants clksel_status2 width(1) "" {
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CLKSEL_0_2 = 0 "Selects SYS_CLK";
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CLKSEL_1_2 = 1 "Selects SYS_32K";
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};
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register cm_abe_pll_ref_clksel addr(base, 0xC) "Control the source of the reference clock for DPLL_ABE" {
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_ 31 mbz;
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clksel 1 rw type(clksel_status2) "Select the source for the DPLL_ABE reference clock.";
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};
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constants sys_clksel_status width(3) "" {
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SYS_CLKSEL_0 = 0 "Uninitialized";
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SYS_CLKSEL_1 = 1 "Input clock is 12 MHz";
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SYS_CLKSEL_2 = 2 "Reserved";
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SYS_CLKSEL_3 = 3 "Input clock is 16.8 MHz";
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SYS_CLKSEL_4 = 4 "Input clock is 19.2 MHz";
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SYS_CLKSEL_5 = 5 "Input clock is 26 MHz";
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SYS_CLKSEL_6 = 6 "Reserved";
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SYS_CLKSEL_7 = 7 "Input clock is 38.4 MHz";
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};
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register cm_sys_clksel addr(base, 0x10) "Software sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK. [warm reset insensitive]" {
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_ 29 mbz;
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sys_clksel 3 rw type(sys_clksel_status) "System clock input selection.";
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};
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}; |