60 lines
1.7 KiB
Plaintext
60 lines
1.7 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* arm_icp_pit.dev
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*
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* DESCRIPTION: Timers for for integrator/cp
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*
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* This is derived from:
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*
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* This is derived from the Intel IXP2400/IXP2800 Network Processor
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* Programmer's Reference Manual (November 2003), p. 352ff
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*
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*/
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device ixp2800_icp_pit msbfirst ( addr base ) "IXP2800 Integrator timer"
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{
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// p.352, section 5.6.5.1
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constants scale "Timer scaling factors" {
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none = 0b00 "Use clock to trigger counter";
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div16 = 0b01 "Use clock devided by 16 to trigger counter";
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div256 = 0b10 "Use clock devided by 256 to trigger counter";
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gpio = 0b11 "Use GPIO pins";
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};
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register CONTROL addr(base, 0x00) "Control register" {
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_ 24 ro "Reserved";
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ACT 1 rw "Activate timer";
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_ 3 ro "Reserved";
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PSS 2 rw type(scale) "Select the pre-scalar";
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_ 2 ro "Reserved";
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};
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register LOADING addr(base, 0x10) "Load value for timer" {
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CLV 32 rw "Counter initial value";
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};
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register STATUS addr(base, 0x20) "Current value for timer" {
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CSV 32 rw "Current counter value";
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};
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register CLEAR addr(base, 0x30) "Interrupt clear" {
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_ 31 ro "Reserved";
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ICL 1 rw "Write one to clear interrupt";
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};
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register WATCHDOG addr(base, 0x40) "Enable timer 4 to be a watchdog timer" {
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_ 31 ro "Reserved";
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WDE 1 rw "Write one to enable watchdog";
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};
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};
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