151 lines
6.9 KiB
Plaintext
151 lines
6.9 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_c2c_master_niu_firewall.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_c2c_master_niu_firewall msbfirst ( addr base ) "" {
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register error_log_k addr(base, 0x0) "Error log register for port k" {
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_ 8 mbz;
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blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
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_ 1 mbz;
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region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
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region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
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reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
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};
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register logical_addr_errlog_k ro addr(base, 0x4) "Logical Physical Address Error log register for port k" type(uint32);
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register regupdate_control addr(base, 0x40) "Register update control register" {
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_ 30 mbz;
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fw_load_req 1 ro "Hadrdware set/Software clear";
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busy_req 1 rw "Busy request";
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};
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register start_region_i_1 addr(base, 0x90) "Start physical address of region i" {
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start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
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_ 12 mbz;
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};
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register start_region_i_2 addr(base, 0xA0) "Start physical address of region i" {
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start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
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_ 12 mbz;
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};
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register start_region_i_3 addr(base, 0xB0) "Start physical address of region i" {
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start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
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_ 12 mbz;
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};
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register end_region_i_1 addr(base, 0x94) "End physical address of region i" {
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end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
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_ 9 mbz;
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region_enable_port2 1 rw "Enable this region for port 2.";
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region_enable_port1 1 rw "Enable this region for port 1.";
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region_enable_port0 1 rw "Enable this region for port 0.";
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};
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register end_region_i_2 addr(base, 0xA4) "End physical address of region i" {
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end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
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_ 9 mbz;
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region_enable_port2 1 rw "Enable this region for port 2.";
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region_enable_port1 1 rw "Enable this region for port 1.";
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region_enable_port0 1 rw "Enable this region for port 0.";
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};
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register end_region_i_3 addr(base, 0xB4) "End physical address of region i" {
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end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See.";
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_ 9 mbz;
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region_enable_port2 1 rw "Enable this region for port 2.";
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region_enable_port1 1 rw "Enable this region for port 1.";
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region_enable_port0 1 rw "Enable this region for port 0.";
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};
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register mrm_permission_region_low_j addr(base, 0x88) "Region j Permission Low" {
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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pub_prv_debug 1 rw "Public Privilege Debug Allowed";
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pub_usr_debug 1 rw "Public User Debug Allowed";
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_ 1 rsvd;
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_ 1 rsvd;
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pub_prv_write 1 rw "Public Privilege Write Allowed";
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pub_prv_read 1 rw "Public Privilege Read Allowed";
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pub_prv_exe 1 rw "Public Privilege Exe Allowed";
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pub_usr_write 1 rw "Public User Write Access Allowed";
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pub_usr_read 1 rw "Public User Read Access Allowed";
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pub_usr_exe 1 rw "Public User Exe Access Allowed";
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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_ 1 rsvd;
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};
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register mrm_permission_region_high_j addr(base, 0x8C) "Region j Permission High" {
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_ 6 rsvd;
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w12 1 rw "Master NIU ConnID = 12 write permission";
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r12 1 rw "Master NIU ConnID = 12 read permission";
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_ 1 rsvd;
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_ 1 rsvd;
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w10 1 rw "Master NIU ConnID = 10 write permission";
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r10 1 rw "Master NIU ConnID = 10 read permission";
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w9 1 rw "Master NIU ConnID = 9 write permission";
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r9 1 rw "Master NIU ConnID = 9 read permission";
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w8 1 rw "Master NIU ConnID = 8 write permission";
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r8 1 rw "Master NIU ConnID = 8 read permission";
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w7 1 rw "Master NIU ConnID = 7 write permission";
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r7 1 rw "Master NIU ConnID = 7 read permission";
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w6 1 rw "Master NIU ConnID = 6 write permission";
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r6 1 rw "Master NIU ConnID = 6 read permission";
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w5 1 rw "Master NIU ConnID = 5 write permission";
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r5 1 rw "Master NIU ConnID = 5 read permission";
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w4 1 rw "Master NIU ConnID = 4 write permission";
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r4 1 rw "Master NIU ConnID = 4 read permission";
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w3 1 rw "Master NIU ConnID = 3 write permission";
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r3 1 rw "Master NIU ConnID = 3 read permission";
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w2 1 rw "Master NIU ConnID = 2 write permission";
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r2 1 rw "Master NIU ConnID = 2 read permission";
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w1 1 rw "Master NIU ConnID = 1 write permission";
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r1 1 rw "Master NIU ConnID = 1 read permission";
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w0 1 rw "Master NIU ConnID = 0 write permission";
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r0 1 rw "Master NIU ConnID = 0 read permission";
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};
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}; |