160 lines
6.5 KiB
Plaintext
160 lines
6.5 KiB
Plaintext
/*
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* Copyright (c) 2018, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* gic_v3.dev
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*
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* DESCRIPTION: GIC v3 architecture definitions
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*
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* See:
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* GIC v3 Architecture Specification
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*/
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device gic_v3_dist msbfirst (addr dist) "GIC v3 Distributor" {
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register GICD_CTLR_secure addr(dist, 0x0) "Distributor Control Register" {
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RWP 1 ro "Register Write Pending";
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_ 23;
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E1NWF 1 "Enable 1 of N Wakeup Functionality";
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DS 1 "Disable Security";
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ARE_NS 1 "Affinity Routing Enable, Non-secure state";
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ARE_S 1 "Affinity Routing Enable, Secure state";
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_ 1 mbz;
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EnableGrp1S 1 "Enable Secure Group 1 interrupts";
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EnableGrp1NS 1 "Enable Non-secure Group 1 interrupts";
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EnableGrp0 1 "Enable Group 0 interrupts";
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};
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register GICD_CTLR also addr(dist, 0x0) "Distributor Control Register" {
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RWP 1 ro "Register Write Pending";
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_ 26;
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ARE_NS 1 "Affinity Routing Enable, Non-secure state";
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_ 2 mbz;
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EnableGrp1A 1 "ARE_NS=1 -> Enable Secure Group 1 interrupts";
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EnableGrp1 1 "ARE_NS=1 -> Enable Non-secure Group 1 interrupts";
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};
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register GICD_TYPER rw addr(dist, 0x4) "Interrupt Controller Type Register" {
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_ 6 mbz;
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No1N 1 "1 of N SPI interrupts not supported";
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A3V 1 "Affinity 3 valid";
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IDbits 5 "The number of interrupt identifier bits supported, minus one";
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DVIS 1 "Implementation supports Direct Virtual LPI injection";
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LPIS 1 "Implementation supports LPIs";
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MBIS 1 "Implementation supports message-based interrupts";
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LSPI 5 "maximum number of implemented lockable SPI";
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SecurityExtn 1 "Indicates whether the GIC implementation supports two Security states";
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_ 2 mbz;
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CPUNumber 3 "Number of PEs that can be used with affinity routing not enabled, minus one";
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ITLinesNumber 5 "Maximum SPI INTID supported";
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};
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register GICD_IIDR ro addr(dist, 0x8) "Distributor Implementer Identification Register" {
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ProductID 8 "Product identifier";
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_ 4 mbz;
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Variant 4 "Variant number";
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Revision 4 "Revision number";
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Implementer 12 "JEP106 code of implementing company";
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};
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register GICD_STATUSR rw addr(dist, 0x10) "Error Reporting Status Register" {
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_ 28 mbz;
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WROD 1 "Write to RO location has been detected";
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RWOD 1 "Read of WO location has been detected";
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WRD 1 "Write to reserved location has been detected";
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RRD 1 "Read to reserved location has been detected";
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};
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register GICD_SETSPI_NSR wo addr(dist, 0x40) "Set Non-secure SPI Pending Register" {
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_ 22 mbz;
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INTID 10 "The INTID of the SPI";
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};
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register GICD_CLRSPI_NSR wo addr(dist, 0x48) "Clear Non-secure SPI Pending Register" {
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_ 22 mbz;
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INTID 10 "The INTID of the SPI";
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};
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register GICD_SETSPI_SR wo addr(dist, 0x50) "Set Secure SPI Pending Register" {
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_ 22 mbz;
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INTID 10 "The INTID of the SPI";
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};
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register GICD_CLRSPI_SR wo addr(dist, 0x58) "Clear Secure SPI Pending Register" {
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_ 22 mbz;
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INTID 10 "The INTID of the SPI";
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};
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regarray GICD_IGROUPR addr(dist, 0x80)[32] "Interrupt Group Registers" type(uint32);
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regarray GICD_ISENABLER addr(dist, 0x100)[32] "Interrupt Set-Enable Registers" type(uint32);
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regarray GICD_ICENABLER addr(dist, 0x180)[32] "Interrupt Clear-Enable Registers" type(uint32);
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regarray GICD_ISPENDR addr(dist, 0x200)[32] "Interrupt Set-Pending Registers" type(uint32);
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regarray GICD_ICPENDR addr(dist, 0x280)[32] "Interrupt Clear-Pending Registers" type(uint32);
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regarray GICD_ISACTIVER addr(dist, 0x300)[32] "Interrupt Set-Active Registers" type(uint32);
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regarray GICD_ICACTIVER addr(dist, 0x380)[32] "Interrupt Clear-Active Registers" type(uint32);
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regarray GICD_IPRIORITYR addr(dist, 0x400)[1020] "Interrupt Priority Registers" type(uint8);
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regarray GICD_ITARGETSR addr(dist, 0x800)[255] "Interrupt Processor Targets Registers" type(uint32);
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regarray GICD_ICFGR addr(dist, 0xC00)[64] "Interrupt Configuration Registers" type(uint32);
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regarray GICD_IGRPMODR addr(dist, 0xD00)[32] "Interrupt Group Modifier Registers" type(uint32);
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regarray GICD_NSACR addr(dist, 0xe00)[64] "Non-secure Access Control Registers" type(uint32);
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constants TargetFilterList width(2) "SGI forwarding" {
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CPUTargetList = 0b00 "Forward the interrupt to the CPU interfaces specified by GICD_SGIR.CPUTargetList.";
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PEAllTarget = 0b01 "Forward the interrupt to all CPU interfaces except that of the PE that requested the interrupt.";
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PEOnlyTarget = 0b10 "Forward the interrupt only to the CPU interface of the PE that requested the interrupt.";
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};
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register GICD_SGIR wo addr(dist, 0xF00) "Software Generated Interrupt Register" {
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_ 6 mbz;
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TargetFilterList 2 type(TargetFilterList);
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CPUTargetList 8 "Forward to CPU interface bit N (only if TargetFilterList==CPUTargetList)";
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NSATT 1 "Required group of the SGI";
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_ 11 mbz;
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INTID 4 "INTID of the SGI to forward to the specified CPU interfaces";
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};
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regarray GICD_CPENDSGIR addr(dist, 0xF10)[4] "SGI Clear-Pending Registers" type(uint32);
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regarray GICD_SPENDSGIR addr(dist, 0xF20)[4] "SGI Set-Pending Registers" type(uint32);
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register ICPIDR2 ro addr(dist, 0x0fe8) "Peripheral ID2 Register" {
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_ 24;
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ArchRev 4 "GIC architecture revision";
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_ 4;
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};
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regarray GICD_IROUTER addr(dist, 0x6100)[1020] "Interrupt Routing Registers" {
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_ 24 mbz;
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Aff3 8 "Affinity level 3, least significant level field";
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Interrupt_Rouing_Mode 1 "Interrupt Routing Mode";
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_ 7 mbz;
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Aff2 8 "Affinity level 2";
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Aff1 8 "Affinity level 1";
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Aff0 8 "Affinity level 0, most significant level field";
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};
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register GICD_PIDR2 ro addr(dist, 0xffe8) "Peripheral ID2 Register" {
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_ 24;
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ArchRev 4 "GIC architecture revision";
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_ 4;
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};
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};
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