86 lines
2.8 KiB
Plaintext
86 lines
2.8 KiB
Plaintext
/*
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* Copyright (c) 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* ixp2800_icp_pic.dev
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*
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* DESCRIPTION: Primary interrupt controller for integrator/cp
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*
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* This is derived from:
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*
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* This is derived from the Intel IXP2400/IXP2800 Network Processor
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* Programmer's Reference Manual (November 2003), p. 541ff
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*
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*/
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device ixp2800_icp_pic0 msbfirst ( addr base ) "IXP2800 Integrator Primary PIC"
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{
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regtype source "Interrupt controller sources" {
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_ 4 "Reserved";
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THD96_127_B 1 "THD_RAW_STATUS_B_3";
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THD64_95_B 1 "THD_RAW_STATUS_B_2";
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THD32_63_B 1 "THD_RAW_STATUS_B_1";
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TH0_31_B 1 "THD_RAW_STATUS_B_0";
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_ 4 "Reserved";
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THD96_127_A 1 "THD_RAW_STATUS_A_3";
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THD64_95_A 1 "THD_RAW_STATUS_A_2";
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THD32_63_A 1 "THD_RAW_STATUS_A_1";
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THD0_31_A 1 "THD_RAW_STATUS_A_0";
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PCI_INT 1 "External PCI interrupt A & B";
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ME_ATTN 1 "Microengine attention register";
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PCI_DOORBELL 1 "A PCI device has set the doorbell interrupt";
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DMA2_DONE 1 "Completion status from the DMA2 engine";
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_ 1 "Reserved";
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DMA0_DONE 1 "Completion status from the DMA0 engine";
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SP_FINT 1 "Slow Port interrupt";
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PMU_INT 1 "PMU interrupt";
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TIMER_UFLW 4 "Timer underflow indicator";
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GPIO_INT 1 "interrupt request from the GPIO unit";
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UART_INT 1 "UART interrupt request";
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ERROR_SUM 1 "OR of all interrupt bits in the ErrorStatus register";
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SOFTINT 1 "Software Interrupt";
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};
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register IRQ_STATUS ro addr (base, 0x08) "IRQ masked interrupt status"
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type(source);
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register IRQ_RAW_STATUS ro addr (base, 0x00) "IRQ un-masked interrupt status"
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type(source);
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register IRQ_ENABLE ro addr (base, 0x10) "Return enabled IRQs"
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type(source);
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register IRQ_ENABLE_SET wo also addr (base, 0x10) "IRQ enable set"
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type(source);
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register IRQ_ENABLE_CLR wo addr (base, 0x18) "IRQ enable clear"
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type(source);
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register SOFT_INT addr (base, 0x54) "Software interrupt set" {
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_ 31 ro "Reserved";
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set 1 rw "Set or read software interrupt";
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};
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register FIQ_STATUS ro addr (base, 0x04) "FIQ masked interrupt status"
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type(source);
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register FIQ_RAW_STATUS ro also addr (base, 0x00) "FIQ un-masked interrupt status"
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type(source);
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register FIQ_ENABLE ro also addr (base, 0x0c) "Return enabled FIQs"
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type(source);
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register FIQ_ENABLE_SET wo also addr (base, 0x0c) "FIQ enable set"
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type(source);
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register FIQ_ENABLE_CLR wo addr (base, 0x14) "FIQ enable clear"
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type(source);
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};
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