92 lines
4.0 KiB
Plaintext
92 lines
4.0 KiB
Plaintext
/*
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* Copyright (c) 2018, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* gic_v3.dev
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*
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* DESCRIPTION: GIC v3 architecture definitions
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*
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* See:
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* GIC v3 Architecture Specification
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*/
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device gic_v3_redist msbfirst (addr redist) "GIC v3 Redistributor" {
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register GICR_CTLR also addr(redist, 0x0000) "Redistributor Control Register" {
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UWP 1 ro "Upstream Write Pending";
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_ 4 mbz;
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DPG1S 1 "Disable Processor selection for Group 1 Secure interrupts";
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DPG1NS 1 "Disable Processor selection for Group 1 Non-secure interrupts";
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DPG0 1 "Disable Processor selection for Group 0 interrupts";
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_ 20 mbz;
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RWP 1 "Register Write Pending";
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_ 2 mbz;
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Enable_LPIs 1 "LPI support is enabled";
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};
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register GICR_IIDR ro addr(redist, 0x0004) "Redistributor Implementer Identification Register" {
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ProductID 8 "Product identifier";
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_ 4 mbz;
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Variant 4 "Variant number";
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Revision 4 "Revision number";
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Implementer 12 "JEP106 code of implementing company";
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};
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register GICR_TYPER ro addr(redist, 0x0008) "Redistributor Type Register" {
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Affinity_Value 32 "The identity of the PE associated with this Redistributor";
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_ 6 mbz;
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CommonLPIAff 2 "The affinity level at which Redistributors share a LPI Configuration table";
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Processor_Number 16 "A unique identifier for the PE";
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_ 2 mbz;
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DPGS 1 "Implementation supports LPIs";
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Last 1 "Implementation supports LPIs";
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DirectLPI 1 "Implementation supports LPIs";
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_ 1 mbz;
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VLPIS 1 "Implementation supports LPIs";
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PLPIS 1 "Implementation supports LPIs";
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};
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register GICR_STATUSR addr(redist, 0x0010) "Error Reporting Status Register" {
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_ 28 mbz;
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WROD 1 "Write to RO location has been detected";
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RWOD 1 "Read of WO location has been detected";
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WRD 1 "Write to reserved location has been detected";
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RRD 1 "Read to reserved location has been detected";
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};
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register GICR_WAKER addr(redist, 0x0014) "Redistributor Wake Register" {
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IMP_DEF2 1 "Implementation Defined";
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_ 28 mbz;
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ChildrenAsleep 1 ro "Indicates whether the connected PE is quiescent";
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ProcessorSleep 1 "Indicates whether the Redistributor can assert the WakeRequest signal";
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IMP_DEF1 1 "Implementation Defined";
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};
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register GICR_IGROUPR0 addr(redist, 0x10080) "Interrupt Group Register 0" type(uint32);
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register GICR_ISENABLER0 addr(redist, 0x10100) "Interrupt Set-Enable Register 0" type(uint32);
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register GICR_ICENABLER0 addr(redist, 0x10180) "Interrupt Clear-Enable Register 0" type(uint32);
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register GICR_ISPENDR0 addr(redist, 0x10200) "Interrupt Set-Pending Register 0" type(uint32);
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register GICR_ICPENDR0 addr(redist, 0x10280) "Interrupt Clear-Pending Register 0" type(uint32);
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register GICR_ISACTIVER0 addr(redist, 0x10300) "Interrupt Set-Active Register 0" type(uint32);
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register GICR_ICACTIVER0 addr(redist, 0x10380) "Interrupt Clear-Active Register 0" type(uint32);
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regarray GICR_IPRIORITYR0 addr(redist, 0x10400)[8] "Interrupt Priority Registers" type(uint32);
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register GICR_ICFGR0 addr(redist, 0x10c00) "SGI Configuration Register" type(uint32);
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register GICR_ICFGR1 addr(redist, 0x10c04) "PPI Configuration Register" type(uint32);
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register GICR_IGRPMODR0 addr(redist, 0x10d00) "Interrupt Group Modifier Register 0" type(uint32);
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register GICR_NSACR0 addr(redist, 0x10e00) "Non-secure Access Control Register" type(uint32);
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};
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