60 lines
1.5 KiB
Plaintext
60 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2013, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* cortex_a9_gt.dev
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*
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* DESCRIPTION: Cortex A9 Global Timer
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*
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* This is derived from:
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*
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* Cortex-A9 MPCore Technical Reference Manual
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* (DDI0407G_cortex_a9_mpcore_r4p1_trm.pdf)
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*
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* This implements private timers and watchdogs
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*/
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device cortex_a9_gt msbfirst ( addr base ) "Cortex A9 Global Timer" {
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register TimerCounterLow addr(base, 0x0)
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"Counter (Lower Word)"
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type(uint32);
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register TimerCounterHigh addr(base, 0x4)
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"Counter (Upper Word)"
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type(uint32);
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register TimerControl addr(base, 0x8) "Control" {
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_ 16 rsvd;
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prescale 8 rw "Prescale factor";
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_ 4 rsvd;
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auto_increment 1 rw "Single shot or increment mode";
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int_enable 1 rw "Interrupt enable bit";
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comp_enable 1 rw "Enable comparision between counter and comparator";
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timer_enable 1 rw "Timer enable bit";
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};
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register TimerIntStat addr(base, 0xc) "Interrupt Status" {
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_ 31 rsvd;
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event_flag 1 rw;
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};
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register TimerComparatorLow addr(base, 0x10)
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"Comparator (Lower Word)"
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type(uint32);
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register TimerComparatorHigh addr(base, 0x14)
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"Comparator (Upper Word)"
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type(uint32);
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register TimerAutoIncrement addr(base, 0x18)
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"Comparator Auto-Increment"
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type(uint32);
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};
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