141 lines
4.4 KiB
Plaintext
141 lines
4.4 KiB
Plaintext
/*
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* Memory mapped GIC v2 CPU Interface. sysreg mapped (GICv3) CPU interfaces
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* should use definitions in armv8.dev.
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* Source: ARM IHI 0069B, page 8-560
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*/
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device gic_v2_cpu msbfirst (addr cpuif) "MMIO mapped GIC CPU interface" {
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register CTLR rw addr(cpuif, 0x0) "CPU Interface Control Register - secure" {
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_ 21 mbz;
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EOImodeNS 1;
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EOImodeS 1;
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IRQBypDisGrp1 1;
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FIQBypDisGrp1 1;
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IRQBypDisGrp0 1;
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FIQBypDisGrp0 1;
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CBPR 1;
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FIQEn 1;
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_ 1 mbz;
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EnableGrp1 1;
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EnableGrp0 1;
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};
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register CTLR_NS rw also addr(cpuif, 0x0) "CPU Interface Control Register - Non-secure" {
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_ 22 mbz;
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EOImodeNS 1;
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RES0 2;
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IRQBypDisGrp1 1;
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FIQBypDisGrp1 1;
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_ 4 mbz;
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EnableGrp1 1;
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};
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register PMR rw addr(cpuif, 0x0004) "Interrupt Controller Interrupt Priority Mask Register" {
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_ 24;
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priority 8 "Priority mask level";
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};
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register BPR rw addr(cpuif, 0x0008) "Interrupt Controller Binray Point Register" {
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_ 29;
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binary_point 3;
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};
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register IAR rw addr(cpuif, 0x000C) "Interrupt Controller Interrupt Acknowledge Register" {
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_ 8;
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intid 24 "INTID of the signaled interrupt";
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};
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register EOIR wo addr(cpuif, 0x0010) "Interrupt Controller End Of Interrupt Register" {
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_ 8;
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intid 24 "INTID from the corresponding ICC_IAR0_EL1 access";
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};
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register RPR ro addr(cpuif, 0x0014) "Running Priority Register" {
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_ 24;
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priority 8 "Running priority";
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};
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register HPPIR ro addr(cpuif, 0x0018) "Highest Priority Pending Interrupt Register" {
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_ 8;
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intid 24 "INTID of the highest priority pending interrupt";
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};
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register ABPR rw addr(cpuif, 0x001c) "Aliased Binary Point Register" {
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_ 29;
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binary_point 3;
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};
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register AIAR ro addr(cpuif, 0x0020) "Aliased Interrupt Acknowledge Register" {
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_ 8;
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intid 24 "INTID of the signaled interrupt";
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};
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register AEOIR wo addr(cpuif, 0x0024) "Aliased End of Interrupt Register" {
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_ 8;
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intid 24 "INTID from the corresponding ICC_IAR0_EL1 access";
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};
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register AHPPIR ro addr(cpuif, 0x0028) "Aliased Highest Priority Pending Interrupt Register" {
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_ 8;
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intid 24 "INTID of the highest priority pending interrupt";
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};
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register STATUSR rw addr(cpuif, 0x002C) "Error Reporting Status Register" {
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_ 27;
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asv 1 "Attempted security violation";
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wrod 1 "Write to an RO location";
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rwod 1 "Read of a WO location";
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wrd 1 "Write to a reserved location";
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rrd 1 "Read of a reserved location";
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};
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register APR1 rw addr(cpuif, 0x00D0) "CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register APR2 rw addr(cpuif, 0x00D4) "CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register APR3 rw addr(cpuif, 0x00D8) "CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register APR4 rw addr(cpuif, 0x00DC) "CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register NSAPR1 rw addr(cpuif, 0x00E0) "Non-secure CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register NSAPR2 rw addr(cpuif, 0x00E4) "Non-secure CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register NSAPR3 rw addr(cpuif, 0x00E8) "Non-secure CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register NSAPR4 rw addr(cpuif, 0x00EC) "Non-secure CPU Interface Active Priorities Registers" {
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impl 32;
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};
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register IIDR ro addr(cpuif, 0x00FC) "CPU Interface Identification Register" {
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ProductID 8 "Product identifier";
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_ 4 mbz;
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Variant 4 "Variant number";
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Revision 4 "Revision number";
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Implementer 12 "JEP106 code of implementing company";
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};
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register DIR wo addr(cpuif, 0x1000) "Deactivate Interrupt Register" {
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_ 8;
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intid 24 "INTID of the highest priority pending interrupt";
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};
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};
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