70 lines
2.1 KiB
Plaintext
70 lines
2.1 KiB
Plaintext
/*
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* Copyright (c) 2008, 2009, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* ht_config.dev
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*
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* DESCRIPTION: HyperTransport Configuration
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*
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* This is derived from the "BIOS and Kernel Developer's Guide (BKDG)
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* for AMD Family 10h Processors", Chapter 3, "Registers".
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*/
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device ht_config lsbfirst ( pci base ) "HyperTransport Configuration" {
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//
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// Section 3.3: Function 0 HyperTransport Technology Configuration
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// Registers
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//
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constants rtdest "Routing Destination" {
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self = 0b1 "Route to this node";
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link0_0 = 0b10 "Route to link 0, sublink 0";
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link1_0 = 0b100 "Route to link 1, sublink 0";
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link2_0 = 0b1000 "Route to link 2, sublink 0";
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link3_0 = 0b10000 "Route to link 3, sublink 0";
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link0_1 = 0b100000 "Route to link 0, sublink 1";
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link1_1 = 0b1000000 "Route to link 1, sublink 1";
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link2_1 = 0b10000000 "Route to link 2, sublink 1";
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link3_1 = 0b100000000 "Route to link 3, sublink 1";
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};
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regtype rtnode "Routing Table" {
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rqrte 9 type(rtdest) "Request Route";
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rprte 9 type(rtdest) "Response Route";
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bcrte 9 type(rtdest) "Broadcast Route";
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_ 5;
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};
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regarray rtnodes rw pci( base, 0x40 ) [8] "Routing Table Nodes" type(rtnode);
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register nodeid rw pci( base, 0x60 ) "Node ID" {
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nodeid 3 "This Node ID";
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_ 1;
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nodecnt 3 "Node Count";
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_ 1;
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sbnode 3 "HyperTransport I/O Hub Node ID";
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_ 1;
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lknode 3 "Lock Controller Node ID";
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_ 1;
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cpucnt 5 "CPU Count";
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_ 3 mbz;
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_ 8;
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};
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register unitid rw pci( base, 0x64 ) "Unit ID" {
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cpuunit 2 "CPU Unit ID";
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_ 2;
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mctunit 2 "Memory Controller Unit ID";
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hbunit 2 "Host Bridge Unit ID";
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sblink 3 "Southbridge I/O Hub Link ID";
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_ 21;
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};
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// ...
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};
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