87 lines
3.1 KiB
Plaintext
87 lines
3.1 KiB
Plaintext
/*
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* Copyright (c) 2016, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/* ARM CPUID register formats */
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device cpuid_arm msbfirst () "ARMv7+ CPUID fields" {
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constants ftr_supp "Feature support" {
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ftr_ni = 0b0000 "Not implemented";
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ftr_i = 0b0001 "Implemented";
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};
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constants jaz_supp "Jazelle extension support" {
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jaz_ni = 0b0000 "Not implemented";
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jaz_it = 0b0001 "Implemented, trivial";
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jaz_i = 0b0010 "Implemented, full";
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};
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constants thm_supp "ThumbEE instruction set support" {
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thm_ni = 0b0000 "Not implemented";
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thm_i1 = 0b0001 "Thumb 1";
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thm_i2 = 0b0011 "Thumb 2";
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};
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datatype id_pfr0 msbfirst(32) "Processor Feature Register 0" {
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_ 16 rsvd "Reserved";
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state3 4 rw type(ftr_supp) "ThumbEE instruction set support";
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state2 4 rw type(jaz_supp) "Jazelle extension support";
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state1 4 rw type(thm_supp) "Thumb instruction set support";
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state0 4 rw type(ftr_supp) "ARM instruction set support";
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};
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constants mpr_supp "M profile" {
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mpr_ni = 0b0000 "Not supported";
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mpr_i = 0b0010 "Supported";
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};
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constants sec_supp "M profile" {
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sec_ni = 0b0000 "Not implemented";
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sec_i = 0b0001 "Implemented";
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sec_ir = 0b0010 "Implemented, with NSACR.RFR";
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};
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datatype id_pfr1 msbfirst(32) "Processor Feature Register 1" {
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_ 12 rsvd "Reserved";
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generic_timer 4 rw type(ftr_supp) "Generic timer extension";
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virtualisation 4 rw type(ftr_supp) "Virtualisation extensions";
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m_profile 4 rw type(mpr_supp) "M profile";
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security 4 rw type(sec_supp) "Security extensions";
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prog_model 4 rw type(ftr_supp) "Programmers' model";
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};
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constants midr_impl "Implementer code" {
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impl_arm = 0x41 "ARM";
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impl_dec = 0x44 "DEC";
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impl_motorola = 0x4d "Motorola/Freescale";
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impl_qualcomm = 0x51 "Qualcomm";
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impl_marvell = 0x56 "Marvell";
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impl_intel = 0x69 "Intel";
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};
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constants arm_part "ARM part number" {
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part_a5 = 0xc05 "Cortex-A5";
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part_a7 = 0xc07 "Cortex-A7";
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part_a8 = 0xc08 "Cortex-A8";
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part_a9 = 0xc09 "Cortex-A9";
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part_a15 = 0xc0f "Cortex-A15";
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part_a17 = 0xc0e "Cortex-A17";
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part_a53 = 0xd03 "Cortex-A53";
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part_a57 = 0xd07 "Cortex-A57";
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part_a72 = 0xd08 "Cortex-A72";
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part_a73 = 0xd09 "Cortex-A73";
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};
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datatype midr msbfirst(32) "Main ID Register" {
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implementer 8 rw type(midr_impl) "Implementer";
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variant 4 rw "Variant";
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architecture 4 rw "Architecture";
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part 12 rw "Primary part number";
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revision 4 rw "Revision";
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};
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};
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