69 lines
1.7 KiB
Plaintext
69 lines
1.7 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* a9scu.dev
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*
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* DESCRIPTION: Cortex A9 Snoop Control Unit
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*
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* This is derived from:
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*
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* ARM Cortex-A9 MPCore Technical Reference Manual
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*
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*/
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device cortex_a9_scu msbfirst ( addr base ) "Cortex A9 SCU" {
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register control addr(base, 0x0) "SCU Control" {
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_ 25 rsvd;
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ic_standby 1 rw "IC standby enable";
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scu_standby 1 rw "SCU standby enable";
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all_device_to_port0 1 rw "Force all Device to port 0 enable";
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spec_linefill 1 rw "SCU speculative linefills enable";
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ram_parity 1 rw "SCU RAMs parity enable";
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address_filtering 1 rw "Address Filtering enable";
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enable 1 rw "SCU enable";
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};
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register config ro addr(base, 0x4) "SCU Configuration" {
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_ 16;
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tag_ram_sizes 8 ro "Tag RAM sizes";
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cpu_smp 4 ro "CPUs SMP bits";
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_ 2;
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numcpus 2 ro "Number of CPUs present";
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};
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constants cpu_status "CPU Status" {
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normal = 0b00 "Normal mode";
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dormant = 0b10 "Dormant mode";
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off = 0b11 "Powered-off mode";
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};
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register powerstatus addr(base, 0x8) "SCU CPU Power Status" {
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_ 6;
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cpu3 2 rw "Status CPU3";
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_ 6;
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cpu2 2 rw "Status CPU2";
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_ 6;
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cpu1 2 rw "Status CPU1";
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_ 6;
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cpu0 2 rw "Status CPU0";
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};
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register filterstart addr(base, 0x40) "Filtering Start Address" {
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addr 12 rw "Filtering Start address";
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_ 20;
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};
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register filterend addr(base, 0x44) "Filtering End Address" {
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addr 12 rw "Filtering Start address";
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_ 20;
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};
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};
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