114 lines
2.7 KiB
Plaintext
114 lines
2.7 KiB
Plaintext
/*
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* Copyright (c) 2007, 2008, 2011 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* amd64.dev
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*
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* DESCRIPTION: amd64 and Intel64 architecture definitions.
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*
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* This is derived from the "Intel 64 and IA-32 Architectures Software
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* Developer's Manual", volumes 3A and 3B, "System Programming Guide,
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* Parts 1 and 2"
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*/
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device amd64 msbfirst ( ) "Intel64 and AMD 64-bit architecture definitions" {
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//
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// Section 2.5: Control registers
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//
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register cr0 noaddr "Control register 0" {
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pg 1 "Paging";
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cd 1 "Cache disable";
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nw 1 "Not write-through";
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_ 10;
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am 1 "Alignment mask";
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_ 1;
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wp 1 "Write protect";
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_ 10;
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ne 1 "Numeric error";
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et 1 "Extension type";
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ts 1 "Task switched";
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em 1 "Emulation";
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mp 1 "Monitor coprocessor";
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pe 1 "Protection enable";
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};
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// Control register 1 is reserved.
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register cr2 noaddr "Page-fault linear address" type(uint64);
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register cr3 noaddr "Control register 3 (PDBR)" {
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pdb 52 "Page-directory base";
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_ 7;
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pcd 1 "Page-level cache disable";
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pwt 1 "Page-level writes transparent";
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_ 3;
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};
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register cr4 noaddr "Control register 4" {
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_ 49 mbz;
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smxe 1 "SMX enable";
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vmxe 1 "VMX enable";
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_ 2 mbz;
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osxmmexcpt 1 "OS support for unmasked SIMD FP exceptions";
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osfxsr 1 "OS support for FXSAVE and FXRSTOR instructions";
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pce 1 "Performance-monitoring counter enable";
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pge 1 "Page global enable";
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mce 1 "Machine-check enable";
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pae 1 "Physical address extensions";
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pse 1 "Page size extensions";
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de 1 "Debugging extensions";
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tsd 1 "Time stamp disable";
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pvi 1 "Protected-mode virtual interrupts";
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vme 1 "Virtual 8086 mode extensions";
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};
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regtype cr8 "Control register 8" {
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_ 60;
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tpl 4 "Task priority level";
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};
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//
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// Section 3.10: PAE-Enabled Paging in IA-32e Mode
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//
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regtype pdir_entry "Page-Directory Entry" {
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exb 1 "Execute-Disable";
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avail 11 "Available";
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_ 12 mbz;
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base 28 "Base address";
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avail2 3 "Available";
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_ 2 mbz;
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avail3 1 "Available";
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accessed 1 "Accessed";
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pcd 1 "Cache disabled";
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pwt 1 "Write-through";
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us 1 "User/Supervisor";
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rw 1 "Read/Write";
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present 1 "Present";
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};
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regtype ptable_entry "Page-Table Entry" {
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exb 1 "Execute-Disable";
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avail 11 "Available";
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_ 12 mbz;
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base 28 "Base address";
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avail2 3 "Available";
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global 1 "Global";
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pat 1 "Page-Attribute index";
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dirty 1 "Dirty";
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accessed 1 "Accessed";
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pcd 1 "Cache disabled";
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pwt 1 "Write-through";
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us 1 "User/Supervisor";
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rw 1 "Read/Write";
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present 1 "Present";
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};
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};
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