138 lines
3.6 KiB
Plaintext
138 lines
3.6 KiB
Plaintext
/*
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* Copyright (c) 2008, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* arm.dev
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*
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* DESCRIPTION: ARM architecture definitions
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*
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* See:
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* ARM Architecture Reference Manual
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*/
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device arm msbfirst () "ARM architecture" {
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// A.2.5
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regtype status "Status register" {
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n 1 "Negative result";
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z 1 "Zero result";
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c 1 "Carry";
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v 1 "Overflow";
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q 1 "DSP overflow";
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_ 19;
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i 1 "IRQ disable";
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f 1 "FIQ disable";
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t 1 "Thumb mode";
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m 5 type(cpu_mode) "Mode";
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};
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constants cpu_mode "CPU mode bits" {
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user = 0b10000 "User";
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fiq = 0b10001 "FIQ";
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irq = 0b10010 "IRQ";
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super = 0b10011 "Supervisor";
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abort = 0b10111 "Abort";
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undef = 0b11011 "Undefined";
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system = 0b11111 "System";
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};
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// A.2.6
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constants exc_vector "Exception vector addresses" {
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vec_reset = 0x00000000 "Reset";
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vec_undef = 0x00000004 "Undefined instruction";
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vec_swi = 0x00000008 "Software interrupt";
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vec_pref_abort = 0x0000000C "Prefetch abort";
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vec_data_abort = 0x00000010 "Data abort";
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vec_irq = 0x00000018 "Interrupt";
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vec_fiq = 0x0000001C "Fast interrupt";
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};
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space cp15(reg, opcode) valuewise "Coprocessor 15";
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// B.2.4
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register control rw cp15(0x01) "CP15 control register" {
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_ 16 mbz;
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l4 1 "Backwards compatible loads";
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rr 1 "Predictable cache replacement strategy";
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v 1 "High exception vectors enable";
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i 1 "Instruction cache enable";
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z 1 "Branch prediction enable";
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f 1 "Implementation defined";
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r 1 "ROM protection bit";
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s 1 "System protection bit";
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b 1 "Big endian";
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l 1 "Late abort model";
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d 1 "26-bit address exception checking";
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p 1 "26/32-bit exception handler mode";
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w 1 "Write buffer enable";
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c 1 "Data or unified cache enable";
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a 1 "Alignment fault checking enable";
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m 1 "MMU enable";
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};
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//
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// Memory Management Unit functions
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//
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// B.3.6.1
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constants fault_type "Faulting access type" {
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terminal = 0b0010 "Terminal exception";
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vector = 0b0000 "Vector exception";
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alignment = 0b0001 "Alignment";
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alignment_2 = 0b0011 "Alternate alignment";
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l1extabort = 0b1100 "Level 1 external abort on translation";
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l2extabort = 0b1110 "Level 2 external abort on translation";
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sec_trans = 0b0101 "Section translation";
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page_trans = 0b0111 "Page transation";
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sec_dom = 0b1001 "Section domain";
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page_dom = 0b1011 "Page domain";
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sec_perm = 0b1101 "Section permissions";
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page_perm = 0b1111 "Page permissions";
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sec_linef = 0b0100 "Section external abort on linefetch";
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page_linef = 0b0110 "Page external abort on linefetch";
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sec_nlinef = 0b1000 "Section external abort on non-linefetch";
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page_nlinef = 0b1010 "Page external abort on non-linefetch";
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};
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// B.3.7.2
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register ttbase rw cp15(0x02) "Translation table base" {
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base 18 "Base address high bits";
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_ 14 mbz;
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};
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// B.3.7.3
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register domacc rw cp15(0x03) "Domain access control" type(uint32);
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// B.3.7.5
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register faultstat rw cp15(0x05) "Fault status" {
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_ 23 mbz;
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_ 1 mbz;
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domain 4 "Faulting domain";
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status 4 type(fault_type) "Access type";
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};
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// 3.7.6
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register faultaddr rw cp15(6) "Fault address" type(uint32);
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// 3.7.7 XXX opcode2, and CRm dependent
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register tlbfunc wo cp15(8) "TLB functions" type(uint32);
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// 3.7.8 XXX opcode2, and CRm dependent
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register tlblock rw cp15(10) "TLB lockdown" {
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entry 31 "Base and victim (variable width)";
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p 1 "Protected from CP8 invalidates";
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};
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};
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