63 lines
2.1 KiB
Plaintext
63 lines
2.1 KiB
Plaintext
/*
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* Copyright (c) 2016, 2017 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* armv8.dev
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*
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* DESCRIPTION: ARMv8 architecture definitions
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*
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* See:
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* ARM Architecture Reference Manual
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*/
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device armv8_cache_ctrl msbfirst () "ARMv8 Cache Control registers" {
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space cache_ctrl(name) registerwise "Cache control register";
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register DC_CSIW wo cache_ctrl(cisw) "Data or unified Cache line Clean and Invalidate by Set/Way" {
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_ 32 mbz;
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SetWay 28 "Set and ways. depends on the cache settings";
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Level 3 "Cache level to operate on, minus 1.";
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_ 1 mbz;
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};
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register DC_CIVAC wo cache_ctrl(civac) "Data or unified Cache line Clean and Invalidate by VA to PoC" {
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addr 64 "Virtual address to use.";
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};
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register DC_CSW wo cache_ctrl(csw) "Data or unified Cache line Clean by Set/Way" {
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_ 32 mbz;
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SetWay 28 "Set and ways. depends on the cache settings";
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Level 3 "Cache level to operate on, minus 1.";
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_ 1 mbz;
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};
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register DC_CVAC wo cache_ctrl(cvac) "Data or unified Cache line Clean by VA to PoC" {
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addr 64 "Virtual address to use.";
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};
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register DC_CVAU wo cache_ctrl(cvau) "Data or unified Cache line Clean by VA to PoU" {
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addr 64 "Virtual address to use.";
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};
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register DC_ISW wo cache_ctrl(isw) "Data or unified Cache line Invalidate by Set/Way" {
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_ 32 mbz;
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SetWay 28 "Set and ways. depends on the cache settings";
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Level 3 "Cache level to operate on, minus 1.";
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_ 1 mbz;
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};
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register DC_IVAC wo cache_ctrl(ivac) "Data or unified Cache line Invalidate by VA to PoC" {
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addr 64 "Virtual address to use.";
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};
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register DC_ZVA wo cache_ctrl(zva) "Data or unified Cache line Invalidate by VA to PoC" {
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addr 64 "Virtual address to use.";
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};
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};
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