54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* Copyright (c) 2020, ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstr 6, CH-8092 Zurich.
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*/
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#ifndef GIC_DIST_H_
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#define GIC_DIST_H_
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#include <stdint.h>
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#include <aos/aos.h>
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//#define GIC_DIST_DEBUG_ON
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#if defined(GIC_DIST_DEBUG_ON)
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#define GIC_DIST_DEBUG(x...) debug_printf("gic_dist:" x)
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#else
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#define GIC_DIST_DEBUG(x...) ((void)0)
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#endif
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struct gic_dist_s;
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/**
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* Allocate and initizalize gic dist driver.
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*
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* \param gds Returns the initialized driver struct
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* \param base The gic dist registers mapped rw and nocache
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*/
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errval_t gic_dist_init(struct gic_dist_s** gds, void* base);
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/**
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* \brief Enable an interrupt
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*
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* \see ARM Generic Interrupt Controller Architecture Specification v1.0
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*
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* \param int_id
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* \param cpu_targets 8 Bit mask. One bit for each core in the system.
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* (chapter 4.3.11)
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* \param prio Priority of the interrupt (lower is higher). We allow 0..15.
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* The number of priority bits is implementation specific, but at least 16
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* (using bits [7:4] of the priority field, chapter 3.3)
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*/
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errval_t gic_dist_enable_interrupt(struct gic_dist_s *gds, int int_id,
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uint8_t cpu_targets, uint16_t prio);
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void gic_dist_raise_softirq(struct gic_dist_s * gds, uint8_t cpumask,
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uint8_t irq);
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#endif
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