59 lines
1.3 KiB
Plaintext
59 lines
1.3 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_i2c_oc.dev
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*
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* description: register definitions for the I2C Bus Overclocking Interface
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*
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* Protection Level: Ring0
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* Visibility: Host / Coprocessor
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* Reset Domain: CSR_RESET, HOT_RESET
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* Register Access: TRM, I2C
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*/
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device xeon_phi_i2c_oc lsbfirst ( addr base ) "Intel Xeon Phi I2C Bus Overclocking Unit" {
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/*
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*
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*/
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register icr rw addr(base, 0x1000) "I2C Control Register for LRB Over-clocking Unit" {
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value 32 "Value";
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};
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/*
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*
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*/
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register isr rw addr(base, 0x1004) "I2C Status Register for LRB Over-clocking Unit" {
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value 32 "Value";
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};
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/*
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*
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*/
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register isar rw addr(base, 0x1008) "I2C Slave Address Register for LRB Over-clocking Unit" {
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value 32 "Value";
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};
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/*
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*
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*/
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register idbr rw addr(base, 0x100C) "I2C Data Buffer Register for LRB Over-clocking Unit" {
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value 32 "Value";
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};
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/*
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*
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*/
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register idmr rw addr(base, 0x1010) "2C Bus Monitor Register for LRB Over-clocking Unit" {
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value 32 "Value";
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};
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};
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