330 lines
11 KiB
Plaintext
330 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_emif.dev
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*
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* DESCRIPTION: OMAP44xx device identification
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*
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* This is derived from:
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*
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* OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
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* Manual Version Q, in particular Section 15.3.6
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*
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*/
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device omap44xx_emif msbfirst ( addr base ) "OMAP44xx external memory intf." {
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register mod_id_rev ro addr(base, 0x0000) "Revision" type(uint32);
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register status ro addr(base, 0x0004) "SDRAM status"
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{
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be 1 "Big endian select for 8 and 16-bit devices";
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dual_clk 1 "Dual Clock mode";
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fast_init 1 "Fast initialization mode";
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_ 26 mbz;
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phy_dll_ready 1 "DDR Phy ready";
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_ 2 mbz;
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};
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constants sdram_type width(3) "SDRAM type values" {
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sdram_s4 = 0x4 "LPDDR2-S4";
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sdram_s2 = 0x5 "LPDDR2-S2";
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};
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register sdram_config rw addr(base, 0x0008) "SDRAM config"
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{
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sdram_type 3 type(sdram_type) "SDRAM type";
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ibank_pos 2 "Internal bank position";
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_ 11;
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narrow_mode 2 "SDRAM data bus width";
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cl 4 "CAS latency";
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rowsize 3 "Row size (add 9 for # row bits)";
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ibank 3 "Internal bank setup: (1<<x) banks";
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ebank 1 "External chip select setup";
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pagesize 3 "Page size (add 9 for # column bits)";
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};
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register sdram_config2 rw addr(base, 0x000c) "SDRAM config 2"
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{
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_ 1;
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cs1nvmen 1 "CS1 LPDDR2-NVM enable";
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_ 2;
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ebank_pos 1 "External bank position";
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_ 21;
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rdbnum 2 "Row buffer setup (1<<x) row buffers";
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_ 1;
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rdbsize 3 "Row data buffer size 32(1<<x) bytes";
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};
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register sdram_ref_ctrl rw addr(base, 0x0010) "SDRAM refresh control"
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{
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initref_dis 1 "Initialization and refresh disable";
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_ 15;
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refresh_rate 16 "Refresh rate";
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};
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register sdram_ref_ctrl_shdw rw addr(base, 0x0014)
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"SDRAM refresh control shadow" type(sdram_ref_ctrl);
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register sdram_tim1 rw addr(base, 0x0018) "SDRAM timing 1"
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{
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_ 3;
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rp 4 "Minimum #DDR clocks precharge to act. or ref.";
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rcd 4 "Minimum #DDR clocks activate to r or w";
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wr 4 "Minimum #DDR clocks write to precharge";
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ras 5 "Minimum #DDR clocks activate to precharge";
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rc 6 "Minimum #DDR clocks activate to activate";
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rrd 3 "Minimum #DDR clocks act. to act. other bank";
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wtr 3 "Minimum #DDR clocks last write to read";
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};
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register sdram_tim1_shdw rw addr(base, 0x001c) "SDRAM timing 1 shadow"
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type(sdram_tim1);
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register sdram_tim2 rw addr(base, 0x0020) "SDRAM timing 2"
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{
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_ 1;
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xp 3 "Minimum #DDR clocks powerdown to non-read";
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_ 3;
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xsnr 9 "Minimum #DDR clocks self-refresh to non-read";
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xsrd 10 "Minimum #DDR clocks self-refresh to read";
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rtp 3 "Minimum #DDR clocks last read to precharge";
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cke 3 "Minimum #DDR clocks between pad_cke_o changes";
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};
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register sdram_tim2_shdw rw addr(base, 0x0024) "SDRAM timing 2 shadow"
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type(sdram_tim2);
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register sdram_tim3 rw addr(base, 0x0028) "SDRAM timing 3"
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{
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_ 8;
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ckesr 3 "Minimum #DDR clocks LPDDR2 in self-refresh";
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zqcs 6 "#DDR clocks a ZQCS command";
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tdqsckmax 2 "#DDR clocks that satisfies tDQSCKmax";
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rfc 9 "Minimum #DDR clocks from ref/ld to ref/act.";
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ras_max 4 "Maximum #interfaces from act. to precharge";
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};
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register sdram_tim3_shdw rw addr(base, 0x002c) "SDRAM timing 3 shadow"
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type(sdram_tim3);
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register lpddr2_nvm_tim rw addr(base, 0x0030) "LPDDR2-NVM timing"
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{
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_ 1;
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xp 3 "Minimum #DDR clocks from powerdown";
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_ 1;
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wtr 3 "Minimum #DDR clocks last write to read";
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rp 4 "Minimum #DDR clocks preactive to activate";
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wra 4 "Minimum #DDR clocks last write to activate";
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rrd 8 "Minimum #DDR clocks act. to act. other bank.";
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rcdmin 8 "Minimum #DDR clocks activate to r/w";
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};
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register lpddr2_nvm_tim_shdw rw addr(base, 0x0034)
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"LPDDR2-NVM timing shadow" type(lpddr2_nvm_tim);
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constants apm_mode width(3) "Auto power management mode" {
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apm_cs = 1 "Clock stop";
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apm_sr = 2 "Self-refresh";
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apm_pd = 4 "Power down";
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};
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register pwr_mgmt_ctrl rw addr(base, 0x0038) "Power management control"
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{
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_ 16;
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pd_tim 4 "Power mangement timer for power-down";
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dpd_en 1 "Deep power down enable";
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lp_mode 3 type(apm_mode) "Automatic power management enable";
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sr_tim 4 "Power mangement timer for self refresh";
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cs_tim 4 "Power mangement timer for clock stop";
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};
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register pwr_mgmt_ctrl_shdw rw addr(base, 0x003c)
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"Power management control shadow" type(pwr_mgmt_ctrl);
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register lpddr2_mode_reg_data rw addr(base, 0x0040)
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"LPDDR2 mode register data" type(uint32);
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register lpddr2_mode_reg_cfg rw addr(base, 0x0050)
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"LPDDR2 mode register config"
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{
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cs 1 "Chip select to issue mode register command";
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refresh_en 1 "Refresh Enable after MRW write";
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_ 22;
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address 8 "Mode register address";
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};
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register l3_config rw addr(base, 0x0054) "L3 configuration"
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{
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_ 4;
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sys_thresh_max 4 "System L3 threshold maximum";
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_ 4;
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ll_thresh_max 4 "Low-latency L3 threshold maximum";
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_ 8;
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pr_old_count 8 "Priority raise old counter";
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};
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register l3_cfg_val1 ro addr(base, 0x0058) "L3 config value 1"
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{
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sys_bus_width 2 "System L3 data bus width 32*(1<<x) bits";
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ll_bus_width 2 "Low-latency L3 data bus width 32*(1<<x)";
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_ 12 mbz;
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wr_fifo_depth 8 "Write data FIFO depth";
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cmd_fifo_depth 8 "Command FIFO depth";
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};
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register l3_cfg_val2 ro addr(base, 0x005c) "L3 config value 2"
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{
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_ 8 mbz;
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rreg_fifo_depth 8 "Register Read Data FIFO depth";
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rsd_fifo_depth 8 "SDRAM read data FIFO depth";
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rcmd_fifo_depth 8 "Read command FIFO depth";
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};
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register perf_cnt_1 ro addr(base, 0x0080) "Perf. counter 1" type(uint32);
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register perf_cnt_2 ro addr(base, 0x0084) "Perf. counter 2" type(uint32);
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constants pcfilter width(4) "Performance counter filter" {
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pcf_sdr_acc = 0x0 "Total SDRAM accesses";
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pcf_sdr_act = 0x1 "Total SDRAM activates";
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pcf_tot_rds = 0x2 "Total reads";
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pcf_tot_wrs = 0x3 "Total writes";
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pcf_cf_full = 0x4 "Cycles L3 command FIFO is full";
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pcf_wf_full = 0x5 "Cycles L3 Write Data FIFO is full";
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pcf_rf_full = 0x6 "Cycles L3 Read Data FIFO is full";
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pcf_tf_full = 0x7 "Cycles L3 Return Command FIFO is full";
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pcf_pri_elv = 0x8 "Priority elevations";
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pcf_cmd_pnd = 0x9 "Cycles that a command was pending";
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pcf_mem_xfr = 0xa "Cycles for which mem. data bus xferd data";
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};
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register perf_cnt_cfg rw addr(base, 0x0088) "Perf. cntr. config"
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{
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cntr2_mconnid_en 1 "MConnID filter enable for perf. cntr. 2";
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cntr2_region_en 1 "Chip Select filter enable for Perf. cntr 2";
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_ 10;
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cntr2_cfg 4 type(pcfilter) "Filter config. for perf. cntr. 2";
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cntr1_mconnid_en 1 "MConnID filter enable for perf. cntr. 1";
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cntr1_region_en 1 "Chip Select filter enable for Perf. cntr 1";
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_ 10;
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cntr1_cfg 4 type(pcfilter) "Filter config. for perf. cntr. 1";
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};
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register perf_cnt_sel rw addr(base, 0x008c) "Perf. cntr. master reg. sel."
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{
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mconnid2 8 "MConnID for perf. counter 2";
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_ 6;
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region_sel2 2 "MAddrSpace for perf. counter 2";
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mconnid1 8 "MConnID for perf. counter 1";
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_ 6;
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region_sel1 2 "MAddrSpace for perf. counter 1";
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};
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register perf_cnt_tim ro addr(base, 0x0090) "Perf. counter time"
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type(uint32);
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register read_idle_ctrl rw addr(base, 0x0098) "Read idle control"
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{
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_ 12;
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read_idle_len 4 "Min size of read idle window";
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_ 7;
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read_idle_interval 9 "Read idle interval";
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};
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register read_idle_ctrl_shdw rw addr(base, 0x009C)
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"Read idle control shadow" type(read_idle_ctrl);
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regtype irq_l3 "L3 interrupt" {
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_ 30;
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ta_sys 1 "SDRAM temperature alert.";
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err_sys 1 "Command or address error.";
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};
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register irqstatus_raw_sys rw addr(base, 0x00a4)
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"System L3 interrupt raw status" type(irq_l3);
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register irqstatus_raw_ll rw addr(base, 0x00a8)
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"Low-latency L3 interrupt raw status" type(irq_l3);
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register irqstatus_sys rw addr(base, 0x00ac)
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"System L3 interrupt status" type(irq_l3);
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register irqstatus_ll rw addr(base, 0x00b0)
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"Low-latency L3 interrupt status" type(irq_l3);
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register irqenable_set_sys rw addr(base, 0x00b4)
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"System L3 interrupt enable set" type(irq_l3);
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register irqenable_set_ll rw addr(base, 0x00b8)
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"Low-latency L3 interrupt enable set" type(irq_l3);
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register irqenable_clr_sys rw addr(base, 0x00bc)
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"System L3 interrupt enable clear" type(irq_l3);
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register irqenable_clr_ll rw addr(base, 0x00c0)
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"Low-latency L3 interrupt enable clear" type(irq_l3);
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register zq_config rw addr(base, 0x00c8)
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"SDRAM output impedance calibration config"
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{
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cs1en 1 "Enable ZQ calibration for CS1";
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cs0en 1 "Enable ZQ calibration for CS0";
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dualcalen 1 "ZQ Dual Calibration enable";
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sfexiten 1 "ZQCL on self-rfr., act. pwrdn, prchrge pwrdwn";
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_ 8;
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zqinit_mult 2 "Num ZQCL intervals in a ZQINIT interval -1";
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zqcl_mult 2 "Num ZQCS intervals in a ZQCL interval -1";
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refinterval 16 "Num rfrsh periods between ZQCS commands";
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};
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register temp_alert_config rw addr(base, 0x00cc) "Temperature Alert Config"
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{
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cs1en 1 "Enables temperature alert polling for CS1";
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cs0en 1 "Enables temperature alert polling for CS0";
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_ 1;
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sfexiten 1 "Poll on self-rfr., act. pwrdn, prchrge pwrdwn";
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devwdt 2 "Physical device width";
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devcnt 2 "#lanes w/ temp. monitoring device";
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_ 2;
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refinterval 22 "Num. refresh periods btw alert polls";
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};
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constants err_spc width(2) "Address space of errored transaction" {
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es_sdram = 0x0 "SDRAM";
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es_ddr2 = 0x1 "LPDDR2-NVM";
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es_int = 0x3 "Internal registers";
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};
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register l3_err_log ro addr(base, 0x00d0) "Error log"
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{
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_ 16;
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maddrspace 2 type(err_spc) "Addr spc of 1st errored transaction";
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mburstseq 3 "Addr mode of 1st errored transaction";
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mcmd 3 "Cmd type of 1st errored transaction";
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mconnid 8 "Connection ID of 1st errored transaction";
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};
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register ddr_phy_ctrl_1 rw addr(base, 0x00e4) "DDR PHY control 1"
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{
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_ 2;
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freeze_delay_code_postamble 4
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"Postamble time respected by the DATA PHY";
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freeze_delay_code_preamble 4
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"Preamble time respected by the DATA PHY";
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dll_master_sw_code_ctrl 10
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"DLL delay code when in software override mode";
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dll_slave_dly_ctrl 8
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"DLL slave delay ratio control";
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read_latency 4
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"Read latency for the read data from SDRAM in DDR clock cycles";
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};
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register ddr_phy_ctrl_1_shdw rw addr(base, 0x00e8)
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"DDR PHY control 1 shadow" type(ddr_phy_ctrl_1);
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register ddr_phy_ctrl_2 rw addr(base, 0x00ec) "DDR PHY control 2"
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type(uint32);
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};
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