128 lines
3.2 KiB
Plaintext
128 lines
3.2 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* virtio_pci.dev
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*
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* 4.1 Virtio Over PCI Bus
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*/
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device virtio_pci lsbfirst ( addr base, addr common ) "Virtio PCI Device Specification" {
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constants vendor_id width(4) "VirtIO PCI vendor" {
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virtio_vendor = 0x1AF4;
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};
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/*
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* cap_vndr 0x09;
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*/
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register vendor addr(base, 0x0) "Identifies a vendor-specific capability." {
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vndr 8 "Vendor ID";
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};
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register next addr(base, 0x1) "Next Pointer" {
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next 8 "Link to next capability in the capability list." ;
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};
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register length addr(base, 0x2) "Length of this capability structure" {
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len 8 "Length";
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};
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constants config_type width(8) "Configuration types" {
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common = 1 "Common configuration";
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notify = 2 "Notifications";
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isr = 3 "ISR Status";
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devspec = 4 "Device specific configuration";
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pci_cfg = 5 "PCI configuration access";
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};
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register config addr(base, 0x3) "identifies the structure" {
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cfg_type 8 "configuration type";
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};
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register bar addr(base, 0x4) "Base Address register (BAR) belonging to the function located beginning" {
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bar 8 "Base Address register (BAR)";
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};
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register offset addr(base, 0x8) "beginning of the structure relative to the base address" {
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off 32 "Offset";
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};
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register length2 addr(base, 0xC) "indicates the length of the structure." {
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len 32 "Length";
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};
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register device_feature_select addr(common, 0x0) "" {
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reg 32 "todo";
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};
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register device_feature addr(common, 0x4) "" {
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reg 32 "todo";
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};
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register driver_feature_select addr(common, 0x8) "" {
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reg 32 "todo";
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};
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register driver addr(common, 0xC) "" {
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reg 32 "todo";
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};
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register msix_config addr(common, 0x10) {
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reg 16 "todo";
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};
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register num_queues addr(common, 0x12) {
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reg 16 "todo";
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};
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register device_status addr(common, 0x14) {
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reg 8 "todo";
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};
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register config_generation addr(common, 0x15) {
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reg 8 "todo";
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};
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register queue_select addr(common, 0x16) {
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val 16 "";
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};
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register queue_size addr(common, 0x18){
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val 16 "";
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};
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register queue_msix_vector addr(common, 0x1A){
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val 16 "";
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};
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register queue_enable addr(common, 0x1C){
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val 16 "";
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};
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register queue_notify_off addr(common, 0x1E){
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val 16 "";
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};
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register queue_desc addr(common, 0x20){
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val 64 "";
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};
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register queue_avail addr(common, 0x28){
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val 64 "";
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};
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register queue_used addr(common, 0x30){
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val 64 "";
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};
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};
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