121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/**
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* \file
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* \brief Platform interface for ARM boards.
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*
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* This file defines the hardware abstraction layer for ARM targets. Each
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* board is expected to have an implementation that corresponds to this
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* interface.
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*
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* This interface is expected to change as new boards are added.
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*/
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/*
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* Copyright (c) 2016 ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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#ifndef __ARM_PLATFORM_H__
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#define __ARM_PLATFORM_H__
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#include <barrelfish_kpi/types.h>
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#include <barrelfish_kpi/platform.h>
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/*
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* Do any extra initialisation for this particular CPU (e.g. A9/A15).
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*/
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void platform_revision_init(void);
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/*
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* Return the core count
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*/
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size_t platform_get_core_count(void);
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/*
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* Print system identification. MMU is NOT yet enabled.
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*/
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void platform_print_id(void);
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/*
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* Return the base address of the private peripheral region.
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*/
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lpaddr_t platform_get_private_region(void);
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/*
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* Fill out provided `struct platform_info`
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*/
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void platform_get_info(struct platform_info *pi);
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void armv7_get_info(struct arch_info_armv7 *ai);
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void armv8_get_info(struct arch_info_armv8 *ai);
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/*
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* Figure out how much RAM we have
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*/
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size_t platform_get_ram_size(void);
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/*
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* Boot secondary processors
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*/
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errval_t platform_boot_core(hwid_t target, genpaddr_t gen_entry, genpaddr_t context);
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void platform_notify_bsp(lpaddr_t *mailbox);
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/*
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* UART locations
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*/
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extern lpaddr_t platform_uart_base[];
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extern size_t platform_uart_size[];
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// Helpers for enabling interrupts
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#define IRQ_PRIO_LOWEST (0xF)
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#define IRQ_CPU_TRG_ALL (0x3) // For two cores on the PandaBoard
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#define IRQ_CPU_TRG_BSP (0x1)
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#define IRQ_EDGE_TRIGGERED (0x1)
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#define IRQ_LEVEL_SENSITIVE (0x0)
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#define IRQ_1_TO_N (0x1)
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#define IRQ_N_TO_N (0x0)
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/*
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* Interrupt controller interface
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*/
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errval_t platform_init_ic_bsp(void);
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errval_t platform_init_ic_app(void);
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uint32_t platform_get_active_irq(void);
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void platform_acknowledge_irq(uint32_t irq);
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errval_t platform_enable_interrupt(uint32_t int_id, uint16_t prio,
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bool edge_triggered, bool one_to_n);
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/*
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* Timers
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*/
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/**
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* @brief initialize the timer
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*/
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void platform_timer_init(int timeslice);
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/**
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* @brief check if the interrupt is a timer interrupt
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*
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* @param interrupt number
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* @return TRUE if it's the timer interrupt
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*/
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bool platform_is_timer_interrupt(uint32_t irq);
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/**
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* @brief Return the IRQ to be used for the cpu driver timer
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* @return The IRQ number of the timer interrupt.
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*/
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uint32_t platform_get_timer_interrupt(void);
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/**
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* @brief Get memory range in which devices are present
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* Should be normally a single range
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*/
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void platform_get_dev_range(lpaddr_t* start, size_t* size);
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#endif // __ARM_PLATFORM_H__
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