342 lines
8.5 KiB
Plaintext
342 lines
8.5 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_dma.dev
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*
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* description: register definitions for the Xeon Phi DMA
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*/
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device xeon_phi_dma lsbfirst(addr base) "Intel Xeon Phi DMA System" {
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regarray dcar rw addr(base, 0xA000) [8; 0x40] "DMA Channel Attribute Register" {
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_ 23 "";
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apic_irq 1 "APIC Interrupt mask bit";
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msix_irq 1 "MSI-X Interrupt mask bit";
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irq_status 1 "Interrupt status";
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_ 6 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dhpr rw addr(base, 0xA004) [8; 0x40] "DMA Descriptor Head Pointer Register" {
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index 16 "Index of the head pointer";
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_ 16 "Reserved";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dtpr rw addr(base, 0xA008) [8; 0x40] "DMA Descriptor Tail Pointer Register" {
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index 16 "Index of the head pointer";
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_ 16 "Reserved";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray aux_lo rw addr(base, 0xA00C) [8; 0x40] "DMA Auxiliary Register 0 Lo" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray aux_hi rw addr(base, 0xA010) [8; 0x40] "DMA Auxiliary Register 0 Hi" {
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r 32 "";
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};
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constants drar_shifts "Shift amounts for the field values" {
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drar_size_shift=2;
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drar_base_shift=6;
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray drar_hi rw addr(base, 0xA018) [8; 0x40] "DMA Descriptor Ring Attributes Register Lo" {
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base 4 "base address hi part";
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_ 2 "";
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size 15 "size of the descriptor ring";
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page 5 "";
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sysbit 1 "";
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_ 5 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray drar_lo rw addr(base, 0xA014) [8; 0x40] "DMA Descriptor Ring Attributes Register Lo" {
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_ 6 "";
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base 26 "base address lo part";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray ditr rw addr(base, 0xA01C) [8; 0x40] "DMA Interrupt Timer Register" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dstat rw addr(base, 0xA020) [8; 0x40] "DMA Status Channel Register" {
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completions 16 "Completition count";
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_ 16 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dstatwb_lo rw addr(base, 0xA024) [8; 0x40] "DMA Tail Pointer Write Back Register Lo" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dstatwb_hi rw addr(base, 0xA028) [8; 0x40] "DMA Tail Pointer Write Back Register Hi" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dcherr rw addr(base, 0xA02C) [8; 0x40] "DMA Channel Error Register" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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* Number: 8
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*/
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regarray dcherrmsk rw addr(base, 0xA030) [8; 0x40] "DMA Channel Error Register Mask" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register dcr rw addr(base, 0xA280) "DMA Configuration Register" {
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co0 1 "DMA Channel 0 Owner";
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ce0 1 "DMA Channel 0 Enable";
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co1 1 "DMA Channel 1 Owner";
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ce1 1 "DMA Channel 1 Enable";
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co2 1 "DMA Channel 2 Owner";
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ce2 1 "DMA Channel 2 Enable";
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co3 1 "DMA Channel 3 Owner";
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ce3 1 "DMA Channel 3 Enable";
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co4 1 "DMA Channel 4 Owner";
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ce4 1 "DMA Channel 4 Enable";
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co5 1 "DMA Channel 5 Owner";
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ce5 1 "DMA Channel 5 Enable";
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co6 1 "DMA Channel 6 Owner";
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ce6 1 "DMA Channel 6 Enable";
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co7 1 "DMA Channel 7 Owner";
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ce7 1 "DMA Channel 7 Enable";
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arb_h 8 "Arb H";
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arb_l 7 "Arb L";
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p 1 "Priority EN";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register dqar rw addr(base, 0xA284) "Descriptor Queue Access Register" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register dqdr_tl rw addr(base, 0xA288) "Descriptor Queue Data Register Top Left" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register dqdr_tr rw addr(base, 0xA28C) "Descriptor Queue Data Register Top Right" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register dqdr_bl rw addr(base, 0xA290) "Descriptor Queue Data Register Bottom Left" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register dqdr_br rw addr(base, 0xA294) "Descriptor Queue Data Register Bottom Right" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register misc rw addr(base, 0xA2A4) "Misc DMA Bits" {
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r 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_REset
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* Register Access: CRU
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*/
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register lock rw addr(base, 0xA400) "Master Lock Register" {
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r 32 "";
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};
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/*
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* Xeon Phi Descriptors
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* 16 bytes in length
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*
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*/
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constants descriptor_type width(4) "" {
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desc_nop=0;
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desc_memcpy=1;
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desc_status = 2;
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desc_general = 3;
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desc_keynoncecent = 4;
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desc_key = 5;
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};
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datatype desc_nop "No-Op descriptor type" {
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_ 124 "";
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dtype 4 "Descriptor type";
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};
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datatype desc_memcpy "Memory Copy descriptor type" {
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src 40 "Source address";
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index 3 "";
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_ 3 "";
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length 14 "";
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_ 4 "";
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dst 40 "Destination address";
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resd 15 "";
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twb 1 "";
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intr 1 "";
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c 1 "";
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co 1 "";
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ecy 1 "";
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dtype 4 "";
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};
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datatype desc_status "Status request descritpor type" {
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data 64 "";
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dst 40 "";
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resvdr 19 "";
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intr 1 "";
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dtype 4 "";
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};
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datatype desc_general "General descriptor type" {
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data 32 "";
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_ 32 "";
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dst 40 "";
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_ 20 "";
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dtype 4 "";
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};
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datatype desc_keynoncecent "" {
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data 64 "";
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_ 53 "";
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cs 1 "";
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index 3 "";
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h 1 "";
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sel 2 "";
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dtype 4 "";
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};
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datatype desc_key "" {
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skap 40 "";
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ski 3 "";
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_ 72 "";
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di 3 "";
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_ 6 "";
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dtype 4 "";
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};
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}; |