175 lines
8.8 KiB
Plaintext
175 lines
8.8 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_dsp_prm.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_dsp_prm msbfirst ( addr base ) "" {
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constants dsp_edma_onstate_status width(2) "" {
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DSP_EDMA_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON.";
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};
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constants dsp_edma_retstate_status width(1) "" {
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DSP_EDMA_RETSTATE_1_r = 1 "Memory bank is retained when domain is in RETENTION state.";
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};
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constants dsp_l2_retstate_status width(1) "" {
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DSP_L2_RETSTATE_0 = 0 "Memory bank is off when the domain is in the RETENTION state.";
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DSP_L2_RETSTATE_1 = 1 "Memory bank is retained when domain is in RETENTION state.";
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};
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constants lowpowerstatechange_status width(1) "" {
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LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change.";
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LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON.";
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};
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constants powerstate_status width(2) "" {
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POWERSTATE_0 = 0 "OFF state";
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POWERSTATE_1 = 1 "RETENTION state";
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POWERSTATE_2 = 2 "INACTIVE state";
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POWERSTATE_3 = 3 "ON State";
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};
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register pm_dsp_pwrstctrl addr(base, 0x0) "This register controls the DSP power state to reach upon a domain sleep transition" {
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_ 10 mbz;
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dsp_edma_onstate 2 ro type(dsp_edma_onstate_status) "DSP_EDMA state when domain is ON.";
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dsp_l2_onstate 2 ro type(dsp_edma_onstate_status) "DSP_L2 state when domain is ON.";
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dsp_l1_onstate 2 ro type(dsp_edma_onstate_status) "DSP_L1 state when domain is ON.";
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_ 5 mbz;
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dsp_edma_retstate 1 ro type(dsp_edma_retstate_status) "DSP_EDMA state when domain is RETENTION.";
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dsp_l2_retstate 1 rw type(dsp_l2_retstate_status) "DSP_L2 state when domain is RETENTION.";
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dsp_l1_retstate 1 rw type(dsp_l2_retstate_status) "DSP_L2 state when domain is RETENTION.";
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_ 3 mbz;
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lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain.";
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_ 1 mbz;
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logicretstate 1 rw type(dsp_l2_retstate_status) "Logic state when power domain is RETENTION";
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powerstate 2 rw type(powerstate_status) "Power state control";
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};
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constants lastpowerstateentered_status width(2) "" {
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LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE";
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LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE";
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LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION";
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LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF";
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};
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constants intransition_status width(1) "" {
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INTRANSITION_0_r = 0 "No ongoing transition on power domain";
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INTRANSITION_1_r = 1 "Power domain transition is in progress.";
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};
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constants dsp_edma_statest_status width(2) "" {
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DSP_EDMA_STATEST_0_r = 0 "Memory is OFF";
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DSP_EDMA_STATEST_1_r = 1 "Memory is RETENTION";
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DSP_EDMA_STATEST_2_r = 2 "Reserved";
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DSP_EDMA_STATEST_3_r = 3 "Memory is ON";
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};
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constants logicstatest_status width(1) "" {
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LOGICSTATEST_0_r = 0 "Logic in domain is OFF";
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LOGICSTATEST_1_r = 1 "Logic in domain is ON";
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};
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constants powerstatest_status width(2) "" {
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POWERSTATEST_0_r = 0 "Power domain is OFF";
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POWERSTATEST_1_r = 1 "Power domain is in RETENTION";
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POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE";
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POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE";
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};
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register pm_dsp_pwrstst addr(base, 0x4) "This register provides a status on the DSP domain current power state. [warm reset insensitive]" {
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_ 6 mbz;
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lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only.";
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_ 3 mbz;
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intransition 1 ro type(intransition_status) "Domain transition status";
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_ 10 mbz;
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dsp_edma_statest 2 ro type(dsp_edma_statest_status) "DSP_EDMA memory state status";
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dsp_l2_statest 2 ro type(dsp_edma_statest_status) "DSP_L2 memory state status";
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dsp_l1_statest 2 ro type(dsp_edma_statest_status) "DSP_L1 memory state status";
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_ 1 mbz;
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logicstatest 1 ro type(logicstatest_status) "Logic state status";
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powerstatest 2 ro type(powerstatest_status) "Current power state status";
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};
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constants rst2_status width(1) "" {
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RST2_0 = 0 "Reset is cleared for the MMU, cache and slave interface";
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RST2_1 = 1 "Reset is asserted for the MMU, cache and slave interface";
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};
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constants rst1_status width(1) "" {
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RST1_0 = 0 "Reset is cleared for the DSP - DSP";
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RST1_1 = 1 "Reset is asserted for the DSP - DSP";
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};
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register rm_dsp_rstctrl addr(base, 0x10) "This register controls the release of the DSP sub-system resets." {
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_ 30 mbz;
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rst2 1 rw type(rst2_status) "DSP - MMU, cache and slave interface reset control";
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rst1 1 rw type(rst1_status) "DSP - DSP reset control";
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};
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constants dsp_dsp_emu_req_rstst_status width(1) "" {
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DSP_DSP_EMU_REQ_RSTST_0 = 0 "No emulation reset";
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DSP_DSP_EMU_REQ_RSTST_1 = 1 "DSP DSP has been reset upon emulation reset request";
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};
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constants dspss_emu_rstst_status width(1) "" {
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DSPSS_EMU_RSTST_0 = 0 "No emulation reset";
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DSPSS_EMU_RSTST_1 = 1 "DSP has been reset upon emulation reset";
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};
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constants rst2st_status width(1) "" {
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RST2ST_0 = 0 "No software reset occured";
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RST2ST_1 = 1 "MMU, cache and slave interface has been reset upon software reset";
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};
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constants rst1st_status width(1) "" {
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RST1ST_0 = 0 "No software reset occured";
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RST1ST_1 = 1 "DSP has been reset upon software reset";
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};
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register rm_dsp_rstst addr(base, 0x14) "This register logs the different reset sources of the DSP domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" {
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_ 28 mbz;
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dsp_dsp_emu_req_rstst 1 rw1c type(dsp_dsp_emu_req_rstst_status) "DSP DSP processor has been reset due to DSP emulation reset request driven from DSPSS";
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dspss_emu_rstst 1 rw1c type(dspss_emu_rstst_status) "DSP domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module";
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rst2st 1 rw1c type(rst2st_status) "DSP MMU, cache and slave interface software reset status";
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rst1st 1 rw1c type(rst1st_status) "DSP DSP software reset";
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};
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constants lostmem_dsp_edma_status width(1) "" {
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LOSTMEM_DSP_EDMA_0 = 0 "Context has been maintained";
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LOSTMEM_DSP_EDMA_1 = 1 "Context has been lost";
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};
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register rm_dsp_dsp_context addr(base, 0x24) "This register contains dedicated DSP context statuses. [warm reset insensitive]" {
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_ 21 mbz;
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lostmem_dsp_edma 1 rw1c type(lostmem_dsp_edma_status) "Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source.";
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lostmem_dsp_l2 1 rw1c type(lostmem_dsp_edma_status) "Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source.";
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lostmem_dsp_l1 1 rw1c type(lostmem_dsp_edma_status) "Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source.";
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_ 6 mbz;
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lostcontext_rff 1 rw1c type(lostmem_dsp_edma_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSP_RET_RST signal)";
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lostcontext_dff 1 rw1c type(lostmem_dsp_edma_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSP_SYS_RST signal)";
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};
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}; |