135 lines
4.5 KiB
Plaintext
135 lines
4.5 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* omap44xx_id.dev
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*
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* DESCRIPTION: OMAP44xx device identification
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*
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* This is derived from:
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*
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* OMAP4430 Multimedia Device Silicon Revision 2.x Technical Reference
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* Manual Version O
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* OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
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* Manual Version Q
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*
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* Section numbers are from the latter.
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*
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*/
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device omap44xx_usbconf msbfirst ( addr base ) "OMAP44xx USB host subsystem" {
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// 23.11.6.2.2
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register revision ro addr(base, 0x0000) "Revision"
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type(uint32);
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register hwinfo ro addr(base, 0x0004) "Hardware info" {
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_ 24;
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sar_cntx_size 8 "Save-and-Restore context size";
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};
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constants idle_mode width(2) "Slave interface power mode" {
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idle_force = 0b00 "Force-Idle mode";
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idle_no = 0b01 "No idle mode";
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idle_smart = 0b10 "Smart-idle mode";
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};
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register config rw addr(base, 0x0010) "Module configuration" {
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_ 23;
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clock_act 1 "Enable autogating OCP-derived int. clks.";
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_ 3;
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s_idle_mode 2 type(idle_mode) "Slave intf. power mgmt. ctrl";
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ena_wakeup 1 "Asynchronous wake-up generation control";
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soft_reset 1 wo "Module software reset";
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auto_idle 1 "Internal autogating control";
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};
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register status ro addr(base, 0x0014) "Module status" {
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_ 31;
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reset_done 1 "Module has entirely come out of reset";
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};
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register irqstat rw1c addr(base, 0x0018) "IRQ status" {
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_ 29 rsvd;
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access_error 1 "Access error to ULPI register over OCP";
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fclk_end 1 "Functional clock no longer requested";
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fclk_start 1 "Functional clock requested for USB clocking";
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};
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register irqenable rw addr(base, 0x001c) "IRQ enable" {
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_ 29 rsvd;
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access_error 1 "Access error to ULPI register over OCP";
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fclk_end 1 "Functional clock no longer requested";
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fclk_start 1 "Functional clock requested for USB clocking";
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};
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register shared_conf rw addr(base, 0x0030) "Shared configuration" {
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_ 30 rsvd;
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fclk_req 1 "Functional clock request";
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fclk_is_on 1 "Status of the functional clock input";
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};
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constants line_state width(2) "Line state" {
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se0 = 0b00 "Single-ended 0";
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fsj = 0b01 "Full-Speed J = differential 1";
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fsk = 0b10 "Full-Speed K = differential 0";
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se1 = 0b11 "Single-ended 1 (illegal in USB)";
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};
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constants si_mode width(4) "Serial interface mode" {
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si_u6ps = 0x0 "6-pin unidirectional PHY i/f. Tx encoding Dat/Se0";
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si_u6pd = 0x1 "6-pin unidirectional PHY i/f. Tx encoding is Dp/Dm";
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si_b3p = 0x2 "3-pin bidirectional PHY i/f";
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si_b4p = 0x3 "4-pin bidirectional PHY i/f";
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si_u6ts = 0x4 "6-pin unidirectional TLL. Tx encoding is Dat/Se0";
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si_u6td = 0x5 "6-pin unidirectional TLL. Tx encoding is Dp/Dm";
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si_b3t = 0x6 "3-pin bidirectional TLL";
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si_b4t = 0x7 "4-pin bidirectional TLL";
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si_b2ts = 0xa "2-pin bidirectional TLL. Encoding is Dat/Se0";
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si_b2td = 0xb "2-pin bidirectional TLL. Encoding is Dp/Dm";
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};
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constants ch_mode width(2) "Main channel mode" {
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ch_u2u = 0b00 "UTMI-to-ULPI TLL mode (HS capable)";
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ch_u2s = 0b01 "UTMI-to-serial (FS/LS)";
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ch_trans= 0b10 "Transparent UTMI mode: to UTMI PHY";
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ch_none = 0b11 "No mode selected";
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};
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regarray channel_conf rw addr(base, 0x0040)[2] "Channel configuration" {
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_ 2 rsvd;
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fslslinestate 2 type(line_state) "Line state for serial modes";
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fslsmode 4 type(si_mode) "Serial interface mode select";
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_ 3 rsvd;
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testtxse0 1 "Force-Se0 tx override for mode test";
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testtxdat 1 "Differential data tx override for mode test";
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testtxen 1 "Differential data tx override for mode test";
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testen 1 "Enable manual test override for Tx path";
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drvvbus 1 "VBUS-drive for ChanMode = serial";
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chrgvbus 1 "VBUS-charge for ChanMode = serial";
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_ 3 rsvd;
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ulpinobitstuff 1 "Disable bitstuff emulation in ULPI TLL";
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ulpiautoidle 1 "Allow ULPI output clock to idle";
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utmiautoidle 1 "Allow UTMI clock to idle";
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_ 1 rsvd;
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ulpioutclkmode 1 ro "ULPI clocking mode select";
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tllfullspeed 1 "PHY speed emul. in TLL (full/slow)";
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tllconnect 1 "Emulate Full/Low-Speed connect";
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tllattach 1 "Emulate cable attach/detach";
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utmiisadev 1 "Select cable end seen by UTMI side of TLL";
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chanmode 2 "Main channel mode selection";
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chanen 1 "Active-high channel enable";
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};
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regarray sar_cntx rw addr(base, 0x0400)[7]
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"Save and restore context array"
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type(uint32);
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};
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