207 lines
8.7 KiB
Plaintext
207 lines
8.7 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_irq.dev
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*
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* description: register definitions for the Xeon Phi interrupts
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*/
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device xeon_phi_irq lsbfirst ( addr base ) "Intel Xeon Phi Interrupts" {
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GPRB_RESET
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* Register Access: CRU
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* Number: 4
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*/
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regarray doorbel rw addr(base, 0xCC90) [4] "System Doorbell Interrupt Command Registe 0-3" {
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value 32 "Value";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GPRB_RESET
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* Register Access: CRU
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*/
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register marker_message_disable rw addr(base, 0xCCA0) "32 Bits to Disable Interrupts" {
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value 32 "Value";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GPRB_RESET
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* Register Access: CRU
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*/
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register marker_message_assert rw addr(base, 0xCCA4) "32 Bits to Assert Interrupts" {
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value 32 "Value";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GPRB_RESET
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* Register Access: CRU
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*/
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register marker_message_send rw addr(base, 0xCCA8) "32 Bits to log INTSCR field of Marker Message" {
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value 32 "Value";
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};
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register msix_ram rw addr(base, 0x7000) "MSI-X RAM" {
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reg 32 "register";
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};
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register sysint_debug rw addr(base, 0x9000) "SYSINT Debug Register" {
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reg 32 "register";
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};
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/*
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* Note: This register contains the status for all of the System Interrupt
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* sources. When an Interrupt event occurs, the bit corresponding to the
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* source shall be set in this register. If SW clears an System Interrupt
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* Status Register bit in the same clock as a HW event wants to set it,
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* the clear shall have precedence over the set.
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* NOTE: While this behavior may seem counter-intuitive and that the HW may
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* risk losing Interrupts, it is actually the preferred implementation
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* because the SW flow must already prevent a race condition. Otherwise, the
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* same problem could occur if the HW event came one clock before the SW clear.
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* Therefore, SW always services Interrupts after clearing the status. If the
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* SW clear did not have precedence, an additional Interrupt would be
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* generated for this condition even though SW had already handled the
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* Interrupt event, which would lead to an additional call of the ISR to
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* clear the status.
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* NOTE: Clear on Read functionality is not supported on this register at
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* the request of SW and HW debug support teams. This results in a slight
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* performance degradation in legacy INTx mode due to the additional UC Write
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* required to clear any status bits that were set.
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*/
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register int_status rw addr(base, 0x9004) "System Interrupt Status Register" {
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reg 32 "registr3";
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};
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/*
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* Note: This register is used for SW testing and HW debug only. The intent
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* of this register is for SW to create the appearance of a HW interrupt
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* event for testing and debug. Writing a '1' to a bit in this register shall
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* result in the corresponding bit in the System Interrupt Status register
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* to be set along with the same behavior as if that HW interrupt event had
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* occurred. Writing a '0' to a bit in this register shall have no effect.
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*/
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register int_status_set rw addr(base, 0x9008) "System Interrupt Status Set Register" {
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reg 32 "register";
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};
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/*
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* This register is used to enable individual Interrupt sources. An Interrupt
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* source, captured in the System Interrupt Status register, shall be enabled
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* to generate Interrupt messages when the value of the corresponding bit in
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* this register is '1', and disabled when '0'. SW enables a particular
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* Interrupt source by writing a '1' to the corresponding bit this register.
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* Writing a '0' to any bit has no effect.
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* NOTE: If SW wants to disable any previously enabled Interrupt sources from
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* generating Interrupt messages, it should use the System Interrupt Disable
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* register instead.
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* NOTE: The value of the bits in this register does not affect the System
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* interrupt Status register. They only affect the generation of the Interrupt
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* messages.
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* WARNING: The following should be true to avoid a hang condition:
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* 1. SW will always acknowledge an Interrupt Vector (clear status bit)
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* before re-enabling it.
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* 2. SW will not blindly re-enable Vectors for which it did not receive
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* an Interrupt.
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* For the unlikely event that these rules need to be violated, you will need
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* to defeature ordering checks to avoid the hang condition.
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*/
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register int_enable rw addr(base, 0x900C) "System Interrupt Enable Register" {
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dbr 4 "";
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_ 4;
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dma 8 "";
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_ 16;
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};
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constants int_en "" {
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dbr_enable_all = 0xF;
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dma_enable_all = 0xFF;
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};
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/*
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* This register is used to disable individual Interrupt sources. Writing a
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* '1' to a bit of this register clears the corresponding bit in the INTENB
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* register. Writing a '0' to any bit has no effect.
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* NOTE: The reason that the Interrupt enables are split into two separate HW
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* register interfaces is to prevent the need for a Read-Modify-Write
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* operation (and potential locks) when different pieces of SW are handling
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* separate Interrupt sources.
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*/
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register int_disable rw addr(base, 0x9010) "System Interrupt Disable" {
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dbr 4 "";
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_ 4;
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dma 8 "";
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_ 16;
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};
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/*
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* In systems that support MSI-X, the interrupt vector allows the ISR to know
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* which interrupt without reading the System Interrupt Status register when
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* a vector is uniquely assigned to an interrupt. In this case, the software
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* overhead of a read or write transaction can be avoided by setting the
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* auto-clear bits in this register. When auto-clear is enabled for an
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* interrupt, the corresponding bit in the System Interrupt Status register
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* will be set when an event occurs, and the MSI-X message will be sent on
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* PCI- Express. Then the corresponding bit in the System Interrupt Status
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* register is cleared and can be asserted on a new event. The vector in the
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* MSI-X message indicates which interrupt caused the event ad defined by
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* the MSI Vector Assignment Regsiter.
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* NOTE: To clarify the definition of SENT, the correspsonding bit will be
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* cleared once the Endpoint accepts the messages which either means it was
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* sent or the vector was masked.
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* NOTE: If interrupts are not uniquely defined to a vector, those interrupts
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* should not use auto-clear. If auto-clear is enabled on an interrupt once
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* the vector is sent, all interrupts assocated to that vector will be cleared.
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*/
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register int_status_auto_clear rw addr(base, 0x9014) "System Interrupt Status Auto-Clear" {
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reg 32 "ff";
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};
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register itp_doorbell rw addr(base, 0x9030) "System Interrupt ITP Doorbell" {
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reg 32 "ff";
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};
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/*
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* Each of these registers assigns Interrupt sources from the System Interrupt
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* Status register to one of the 16 possible MSI(-X) Vectors. The bits set
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* in a given register shall define the collection of Interrupt sources (from
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* System Interrupt Status register) that are assigned to a particular Interrupt
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* Vector. Register 0 shall assign Interrupt sources to Vector 0, Register 1
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* shall assign Interrupt sources to Vector 1, and so on.
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* NOTE: SW must ensure that no interrupts are enabled (in System Interrupt
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* Disable) before modifying the value of any MSI(-X) Vector Assignment
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* register, otherwise the behavior is undefined.
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* NOTE: SW shall be responsible for assigning each interrupt source to an
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* unique Vector, or otherwise must handle multiple interrupts for a given
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* source.
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* NOTE: SW must ensure that interrupts sharing the same vector have the
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* correpsonding bits disabled System Interrupt Status Auto-clear register,
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* otherwise the behavior is undefined.
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*/
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regarray msi_vector rw addr(base, 0x9044) [16] "MSI(-X) Vector Assignment Register 0-15" {
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dbr 4 "";
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_ 4;
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dma 8 "";
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_ 16;
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};
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}; |