42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
/**
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* \file
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* \brief aarch64 cache maintenance functions
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* */
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/*
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* Copyright (c) 2020, ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
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*/
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#ifndef LIBBARRELFISH_CACHE_H
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#define LIBBARRELFISH_CACHE_H
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#define cpu_nullop() arm64_nullop()
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#define cpufunc_nullop() arm64_nullop()
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#define cpu_setttb(a) arm64_setttb(a)
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#define cpu_tlb_flushID() arm64_tlb_flushID()
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#define cpu_tlb_flushID_SE(e) arm64_tlb_flushID_SE(e)
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#define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s))
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#define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
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#define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))
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#define cpu_idcache_wbinv_range(a, s) arm64_idcache_wbinv_range((a), (s))
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#define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
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void arm64_nullop(void);
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void arm64_setttb(vm_offset_t);
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void arm64_tlb_flushID(void);
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void arm64_tlb_flushID_SE(vm_offset_t);
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void arm64_icache_sync_range(vm_offset_t, vm_size_t);
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void arm64_idcache_wbinv_range(vm_offset_t, vm_size_t);
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void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
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void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
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void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
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#endif
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