218 lines
7.9 KiB
Plaintext
218 lines
7.9 KiB
Plaintext
/*
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* omap44xx_mmu.dev
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*
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* The OMAP4460 has three Memory management units (MMU):
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* a) Cortex A9 MMU: For the two ARMV7 cores
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* b) Cortex M3 MMU: For the two multimedia processors
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* c) DSP device MMU: Don't know what that is
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*
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* This is derived from:
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*
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* OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
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* Manual Version X, in particular Section 20.5
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*
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*/
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device omap44xx_mmu msbfirst ( addr base ) "OMAP44xx Memory Management Unit (MMU)" {
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register revision ro addr(base, 0x0000) "This register contains the IP revision code" type(uint32);
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constants idle_mode width(2) "Idle mode" {
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im_force = 0x0 "Force idle";
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im_none = 0x1 "No idle";
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im_smart = 0x2 "Smart idle";
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};
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constants auto_idle_mode width(1) "Idle mode" {
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aim_free = 0x0 "Interconnect clock is free-running";
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aim_auto = 0x1 "Automatic interconnect clock gating strategy";
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};
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register sysconfig rw addr(base, 0x0010) "Controls the various parameters of the L3 interconnect interface" {
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_ 22;
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clockactivity 2 "Clock activity during wake-up mode";
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_ 3;
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idlemode 2 type(idle_mode) "Wake-up enable";
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_ 1;
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softreset 1 "Software reset";
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autoidle 1 type(auto_idle_mode) "Internal interconnect clock gating strategy";
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};
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constants reset_state width(1) "Reset monitoring" {
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ongoing = 0x0 "Internal module reset in on-going";
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done = 0x1 "Reset completed";
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};
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register sysstatus ro addr(base, 0x0014) "Status information about the Module" {
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_ 31;
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reset_state 1 type(reset_state) "Reset state";
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};
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constants irq_fault width(1) "IRQ Fault" {
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false = 0x0 "No fault.";
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pending = 0x1 "Fault is pending";
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};
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register irqstatus rw addr(base, 0x0018) "Interrupt Status" {
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_ 27;
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multihitfault 1 type(irq_fault) "Error due to multiple matched in TLB";
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tablewalkfault 1 type(irq_fault) "Error response received during table walk";
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emumiss 1 type(irq_fault) "Unrecoverable TLB miss during debug";
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translation_fault 1 type(irq_fault) "Invalid descriptor in translation tables";
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tlbmiss 1 type(irq_fault) "Unrecoverable TLB miss";
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};
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constants irq_toggle width(1) "IRQ Toggle" {
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masked = 0x0 "Interrupt is Masked";
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irq_enabled = 0x1 "Interrupt is enabled";
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};
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register irqenable rw addr(base, 0x001C) "Allows to mask/unmask the module internal sources of interrupt" {
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_ 27;
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multihitfault 1 type(irq_toggle) "Error due to multiple matched in TLB";
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tablewalkfault 1 type(irq_toggle) "Error response received during table walk";
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emumiss 1 type(irq_toggle) "Unrecoverable TLB miss during debug";
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translation_fault 1 type(irq_toggle) "Invalid descriptor in translation tables";
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tlbmiss 1 type(irq_toggle) "Unrecoverable TLB miss";
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};
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constants twl_state width(1) "Table walk status" {
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completed = 0x0 "Table walk done";
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running = 0x1 "Table walk is running";
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};
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register walking_st rw addr(base, 0x0040) "Status information about the table walking logic" {
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_ 31;
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status 1 type(twl_state) "Table walk status";
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};
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constants mmu_feature_status width(1) "MMU Feature Status" {
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disabled = 0x0 "Disabled";
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enabled = 0x1 "Enabled";
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};
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register cntl rw addr(base, 0x0044) "Programs MMU Features" {
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_ 28;
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emu_tlb_update 1 type(mmu_feature_status) "TLB Update on emulated table walk";
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tlw 1 type(mmu_feature_status) "Table walk logic";
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mmu 1 type(mmu_feature_status) "Memory management unit";
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_ 1;
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};
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register fault_ad ro addr(base, 0x0048) "MMU Fault Address (virtual)" type(uint32);
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register ttb rw addr(base, 0x004C) "Translation Table Base address" type(uint32);
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register lock rw addr(base, 0x0050) "Lock some TLB entries" {
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_ 17;
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basevalue 5;
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_ 1;
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current_victim 5;
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_ 4;
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};
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constants tlb_load_signal width(1) "TLB Load signal" {
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start = 0x1 "Start TLB load";
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};
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register ld_tlb wo addr(base, 0x0054) "Load TLB entries" {
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_ 31;
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load_table_item 1 type(tlb_load_signal) "Load data in the TLB";
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};
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constants page_size width(2) "Page sizes" {
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section = 0x0 "1 MB";
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large = 0x1 "64 KB";
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small = 0x2 "4 KB";
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super = 0x3 "16 MB";
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};
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register cam rw addr(base, 0x0058) "Holds a CAM entry" {
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virtual_tag 20 "Virtual address tag";
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_ 8;
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preserved 1 "Preserved bit";
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valid 1 "Valid bit";
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page_size 2 type(page_size) "Page size";
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};
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constants page_endianness width(1) "Little/Big Endian?" {
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little = 0x0 "Little endian";
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big = 0x1 "Big endian";
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};
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constants page_element_size width(2) "Element sizes" {
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eight = 0x0 "8-bits";
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sixteen = 0x1 "16-bits";
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thirty_two = 0x2 "32-bits";
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no_translation = 0x3 "No translation";
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};
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constants page_mixed_attributes width(1) "Page mixed attributes" {
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tlb = 0x0 "Use TLB element size";
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cpu = 0x1 "Use CPU element size";
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};
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register ram rw addr(base, 0x005C) "Holds a RAM entry" {
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physical_address 20 "Physical address";
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_ 2;
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endianness 1 type(page_endianness) "Page endianness";
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element_size 2 type(page_element_size) "Page element size";
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mixed 1 type(page_mixed_attributes) "Mixed page attribute";
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_ 6;
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};
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register gflush wo addr(base, 0x0060) "Flush non-protected TLB entries" {
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_ 31;
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global_flush 1 "Flush all non-protected TLB entries when set";
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};
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register flush_entry rw addr(base, 0x0064) "Flush entry pointed to by CAM virtual address" {
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_ 31;
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flush_entry 1 "Flush TLB entry pointed to by CAM entry.";
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};
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register read_cam ro addr(base, 0x0068) "Read CAM data from CAM entry" {
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virtual_tag 20 "Virtual address tag";
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_ 8;
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preserved 1 "Preserved bit";
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valid 1 "Valid bit";
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page_size 2 type(page_size) "Page size";
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};
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register read_ram ro addr(base, 0x006C) "Read RAM data from RAM entry" {
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physical_address 20 "Physical address";
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_ 2;
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endianness 1 type(page_endianness) "Page endianness";
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element_size 2 type(page_element_size) "Page element size";
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mixed 1 type(page_mixed_attributes) "Mixed page attribute";
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_ 6;
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};
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register emu_fault_ad ro addr(base, 0x0070) "Fault Address caused by debugger" type(uint32);
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register fault_pc ro addr(base, 0x0080) "Fault Address caused by Process Counter" type(uint32);
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register fault_status rw addr(base, 0x0084) "Fault status" {
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_ 24;
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fault_trans_id 4 "Master ID who causes a fault";
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read_write 1 "Indicates read or write";
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fault_type 2 "MMU fault type";
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fault_indication 1 "Indicates a MMU Fault";
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};
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constants bus_error_back_en_status width(1) "Bus error back enable status bit" {
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default = 0x0 "Default behaviour for MMU page faults";
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return_bus_error = 0x1 "All MMU faults return bus error back";
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};
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register gp_reg rw addr(base, 0x0088) "Bus-error back response enable?" {
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_ 31;
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bus_error_back_en 1 type(bus_error_back_en_status) "Bus error back response enable bit";
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};
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/* TODO overlap?
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register dspss_gpr rw addr(base, 0x0088) "MMU Hardware debug multiplexer" type(uint32);*/
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};
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