99 lines
2.4 KiB
Plaintext
99 lines
2.4 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_smpt.dev
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*
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* description: register definitions for the Xeon Phi system memory page tables
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*/
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device xeon_phi_mcheck lsbfirst ( addr base ) "Intel Xeon Phi Machine Check Registers" {
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register ctl_lo rw addr(base, 0x3090) "MCX Control Lo" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register ctl_hi rw addr(base, 0x3094) "MCX Control Hi" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register status_lo rw addr(base, 0x3098) "MCX Status Lo" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register status_hi rw addr(base, 0x309C) "MCX Status Hi" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register addr_lo rw addr(base, 0x30A0) "MCX Address Lo" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register addr_hi rw addr(base, 0x30A4) "MCX Address Hi" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register misc rw addr(base, 0x30A8) "Machine Check Misc" {
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reg 32 "";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPA_PWRGD
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* Register Access: CRU, TRM
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*/
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register misc2 rw addr(base, 0x30AC) "Machine Check Misc 2" {
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reg 32 "";
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};
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}; |