230 lines
7.5 KiB
Plaintext
230 lines
7.5 KiB
Plaintext
/*
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* Copyright (c) 2016, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* zynq_uart.dev
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*
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* DESCRIPTION: Xilinx Zynq UART controller
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*
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* This is derived from:
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*
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* Zynq-7000 All Programmable SoC Technical Reference Manual (UG585)
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*
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*/
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device zynq_uart msbfirst (addr base) "Zynq UART" {
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constants en_hi "Enable high" {
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disabled_hi = 0b0 "disabled";
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enabled_hi = 0b1 "enabled";
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};
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constants en_lo "Enable low" {
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enabled_lo = 0b0 "enabled";
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disabled_lo = 0b1 "disabled";
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};
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register CR addr (base, 0x0) "UART Control" {
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_ 23;
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stopbrk 1 rw "Stop transmitting break";
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startbrk 1 rw "Start transmitting break";
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torst 1 rw "Restart receiver timeout counter";
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tx_dis 1 rw type(en_lo) "Transmit disable";
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tx_en 1 rw type(en_hi) "Transmit enable";
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rx_dis 1 rw type(en_lo) "Receive disable";
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rx_en 1 rw type(en_hi) "Receive enable";
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txrst 1 rw "Software reset for Tx data path";
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rxrst 1 rw "Software reset for Rx data path";
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};
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constants chmode "Channel mode" {
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normal = 0b00 "normal";
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echo = 0b01 "automatic echo";
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local_loop = 0b10 "local loopback";
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remote_loop = 0b11 "remote loopback";
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};
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constants stopbits "Number of stop bits" {
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stop_1 = 0b00 "1 stop bit";
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stop_15 = 0b01 "1.5 stop bits";
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stop_2 = 0b10 "2 stop bits";
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};
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constants parity "Parity type" {
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even = 0b000 "even";
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odd = 0b001 "odd";
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space = 0b010 "space";
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mark = 0b011 "mark";
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none0 = 0b100 "none";
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none1 = 0b101 "none";
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none2 = 0b110 "none";
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none3 = 0b111 "none";
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};
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constants length "Character length" {
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bits_8_0 = 0b00 "8 bits";
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bits_8_1 = 0b01 "8 bits";
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bits_7 = 0b10 "7 bits";
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bits_6 = 0b11 "6 bits";
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};
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register MR addr (base, 0x4) "UART Mode" {
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_ 20;
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_ 1;
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_ 1;
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chmode 2 rw type(chmode) "Channel mode";
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nbstop 2 rw type(stopbits) "Number of stop bits";
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par 3 rw type(parity) "Parity type";
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chrl 2 rw type(length) "Character length";
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clksel 1 rw "Divide uart_ref_clk by 8";
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};
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register IER addr (base, 0x8) "Interrupt Enable" {
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_ 19;
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tovr 1 wo "Transmitter FIFO overflow";
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tnful 1 wo "Transmitter FIFO nearly full";
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ttrig 1 wo "Transmitter FIFO trigger";
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dmsi 1 wo "Delta modem status indicator";
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timeout 1 wo "Receiver timeout error";
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parity 1 wo "Receiver parity error";
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framing 1 wo "Receiver framing error";
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rovr 1 wo "Receiver overflow error";
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tful 1 wo "Transmitter FIFO full";
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tempty 1 wo "Transmitter FIFO empty";
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rful 1 wo "Receiver FIFO full";
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rempty 1 wo "Receiver FIFO empty";
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rtrig 1 wo "Receiver FIFO trigger";
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};
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register IDR addr (base, 0xC) "Interrupt Disable" {
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_ 19;
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tovr 1 wo "Transmitter FIFO overflow";
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tnful 1 wo "Transmitter FIFO nearly full";
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ttrig 1 wo "Transmitter FIFO trigger";
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dmsi 1 wo "Delta modem status indicator";
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timeout 1 wo "Receiver timeout error";
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parity 1 wo "Receiver parity error";
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framing 1 wo "Receiver framing error";
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rovr 1 wo "Receiver overflow error";
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tful 1 wo "Transmitter FIFO full";
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tempty 1 wo "Transmitter FIFO empty";
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rful 1 wo "Receiver FIFO full";
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rempty 1 wo "Receiver FIFO empty";
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rtrig 1 wo "Receiver FIFO trigger";
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};
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register IMR addr (base, 0x10) "Interrupt Mask" {
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_ 19;
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tovr 1 ro "Transmitter FIFO overflow";
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tnful 1 ro "Transmitter FIFO nearly full";
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ttrig 1 ro "Transmitter FIFO trigger";
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dmsi 1 ro "Delta modem status indicator";
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timeout 1 ro "Receiver timeout error";
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parity 1 ro "Receiver parity error";
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framing 1 ro "Receiver framing error";
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rovr 1 ro "Receiver overflow error";
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tful 1 ro "Transmitter FIFO full";
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tempty 1 ro "Transmitter FIFO empty";
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rful 1 ro "Receiver FIFO full";
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rempty 1 ro "Receiver FIFO empty";
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rtrig 1 ro "Receiver FIFO trigger";
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};
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register ISR addr (base, 0x14) "Channel Interrupt Status" {
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_ 19;
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tovr 1 rw1c "Transmitter FIFO overflow";
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tnful 1 rw1c "Transmitter FIFO nearly full";
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ttrig 1 rw1c "Transmitter FIFO trigger";
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dmsi 1 rw1c "Delta modem status indicator";
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timeout 1 rw1c "Receiver timeout error";
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parity 1 rw1c "Receiver parity error";
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framing 1 rw1c "Receiver framing error";
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rovr 1 rw1c "Receiver overflow error";
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tful 1 rw1c "Transmitter FIFO full";
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tempty 1 rw1c "Transmitter FIFO empty";
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rful 1 rw1c "Receiver FIFO full";
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rempty 1 rw1c "Receiver FIFO empty";
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rtrig 1 rw1c "Receiver FIFO trigger";
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};
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register BAUDGEN addr (base, 0x18) "Baud Rate Generator" {
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_ 16;
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CD 16 rw "Baud rate clock divisor value";
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};
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register RXTOUT addr (base, 0x1C) "Receiver Timeout" {
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_ 24;
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RTO 8 rw "Receiver timeout value";
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};
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register RXWM addr (base, 0x20) "Receiver FIFO Trigger Level" {
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_ 26;
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RTRIG 6 rw "Receiver FIFO trigger level";
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};
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register MODEMCR addr (base, 0x24) "Modem Control" {
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_ 26;
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FCM 1 rw type(en_hi) "Automatic flow control";
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_ 3;
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RTS 1 rw type(en_lo) "Request to send software control";
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DTR 1 rw type(en_lo) "Data terminal ready";
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};
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register MODEMSR addr (base, 0x28) "Modem Status" {
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_ 23;
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FCMS 1 rw type(en_hi) "Flow control mode";
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DCD 1 ro type(en_lo) "Data carrier detect";
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RI 1 ro type(en_lo) "Ring indicator";
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DSR 1 ro type(en_lo) "Data set ready";
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CTS 1 ro type(en_lo) "Clear to send";
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DDCD 1 rw1c "Delta data carrier detect status";
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TERI 1 rw1c "Trailing edge ring indicator status";
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DDSR 1 rw1c "Delta data set ready status";
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DCTS 1 rw1c "Delta clear to send status";
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};
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register SR addr (base, 0x2C) "Channel Status" {
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_ 17;
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TNFUL 1 ro "Transmitter FIFO nearly full";
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TTRIG 1 ro "Transmitter FIFO >= TTRIG";
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FDELT 1 ro "Receiver FIFO >= FDEL";
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TACTIVE 1 ro "Transmitter active";
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RACTIVE 1 ro "Recevier active";
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_ 1;
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_ 1;
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_ 1;
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_ 1;
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_ 1;
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TXFULL 1 ro "Transmitter FIFO full";
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TXEMPTY 1 ro "Transmitter FIFO empty";
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RXFULL 1 ro "Receiver FIFO full";
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RXEMPTY 1 ro "Receiver FIFO empty";
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RTRIG 1 ro "Receiver FIFO >= RTRIG";
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};
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register FIFO addr (base, 0x30) "Transmit and Receive FIFO" {
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_ 24;
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FIFO 8 rw;
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};
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register BDIV addr (base, 0x34) "Baud Rate Divider" {
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_ 24;
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BDIV 8 rw "Baud rate divider value";
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};
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register FDEL addr (base, 0x38) "Flow Control Delay" {
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_ 26;
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BDIV 6 rw "RxFIFO trigger level for RTS deassertion";
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};
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register TTRIG addr (base, 0x44) "Transmitter FIFO Trigger Level" {
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_ 26;
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TTRIG 6 rw "Transmitter FIFO Trigger Level";
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};
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};
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