358 lines
13 KiB
Plaintext
358 lines
13 KiB
Plaintext
/*
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* Copyright (c) 2012, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* omap_uart.dev
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*
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* DESCRIPTION: OMAP4430 UART
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*
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* This is derived from:
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*
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* OMAP4430 Multimedia Device Silicon Revision 2.x Technical Reference
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* Manual Version O (OMAP4430_ES2.x_PUBLIC_TRM_vO.pdf)
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*
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* This file only incorporates the parts relevant for UART operation.
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* Registers relevant for IrDA, CIR, and other modes are not yet
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* described.
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*/
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device omap_uart msbfirst ( addr base ) "OMAP4430 UART" {
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register THR wo addr (base, 0x0) "Transmit holding" {
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_ 24;
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thr 8 wo "Transmit holding register";
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};
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register RHR ro also addr (base, 0x0) "Receive holding" {
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_ 24;
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rhr 8 ro "Receive holding register";
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};
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register DLL rw also addr (base, 0x0) "Divisor latch low" {
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_ 24;
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clock_lsb 8 rw "Divisor latch low";
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};
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register IER rw addr (base, 0x4) "Interrupt enable" {
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_ 24;
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cts_it 1 "CTS interrupt enable";
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rts_it 1 "RTS interrupt enable";
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xoff_it 1 "XOFF interrupt enable";
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sleep_mode 1 "Sleep mode (stop baud rate clk when module inactive)";
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modem_sts_it 1 "Modem status register interrupt enable";
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line_sts_it 1 "Receiver line status interrupt enable";
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thr_it 1 "THR interrupt enable";
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rhr_it 1 "RHR interrupt enable";
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};
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constants it_type "Interrupt type" {
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it_modem = 0x0 "Modem interrupt";
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it_thr = 0x1 "THR interrupt";
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it_rhr = 0x2 "RHR interrupt";
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it_rlse = 0x3 "Receiver line status error";
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it_rxtimeout= 0x6 "RX time-out";
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it_xoff = 0x8 "XOFF/special character";
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it_cts = 0x10 "CTS, RTS, DSR change state from active to inactive";
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};
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register IIR ro addr (base, 0x8) "Interrupt identification" {
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_ 24;
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fcr_mirror 2 "Mirror contents of FCR[0]";
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it_type 5 type(it_type) "Interrupt type";
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it_pending 1 "No interrupt pending";
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};
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register DLH rw also addr (base, 0x4) "Divisor latch high" {
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_ 26;
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clock_msb 6 rw "Divisor latch high";
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};
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register FCR wo also addr (base, 0x8) "FIFO control" {
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_ 24;
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rx_fifo_trig 2 "RX FIFO trigger level";
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tx_fifo_trig 2 "TX FIFO trigger level";
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dma_mode 1 "Enable DMA mode";
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tx_fifo_clear 1 "Clear TX FIFO";
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rx_fifo_clear 1 "Clear RX FIFO";
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fifo_en 1 "Enable TX/RX FIFOs";
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};
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constants sw_flow "Software flow control" {
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none = 0b00 "No transmit flow control";
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xon1xoff1 = 0b10 "XON1, XOFF1";
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xon2xoff2 = 0b01 "XON2, XOFF2";
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xon12xoff12 = 0b11 "XON1, XON2: XOFF1, XOFF2";
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};
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register EFR wo also addr (base, 0x8) "Enhanced feature register" {
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_ 24;
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auto_cts_en 1 "Enable auto-CTS flow control";
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auto_rts_en 1 "Enable auto-RTS flow control";
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special_char_detect 1 "Enable special character detect";
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enhanced_en 1 "Enable writing to IER";
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sw_tx_flow_control 2 type(sw_flow) "Software TX flow control";
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sw_rx_flow_control 2 type(sw_flow) "Software RX flow control";
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};
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constants char_length "RX/TX char length" {
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wl_5bits = 0 "5 bits";
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wl_6bits = 1 "6 bits";
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wl_7bits = 2 "7 bits";
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wl_8bits = 3 "8 bits";
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};
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register LCR rw addr (base, 0xc) "Line control" {
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_ 24;
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div_en 1 "Divisor latch enable";
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break_en 1 "Break control enable";
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parity_type2 1 "Parity format";
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parity_type1 1 "Even parity if LCR.parity_en = 1";
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parity_en 1 "Parity enable";
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nb_stop 1 "Number of stop bits";
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char_length 2 type(char_length) "TX/RX char length";
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};
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register XON1 rw addr (base, 0x10) "XON1 character" {
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_ 24;
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xon_word1 8 "XON1 character";
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};
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register MCR rw also addr (base, 0x10) "Modem control" {
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_ 25;
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tcr_tlr 1 "Enable access to TCR and TLR";
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xon_en 1 "Enable XON any function";
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loopback_en 1 "Enable local loopback mode";
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cd_sts_ch 1 "In loopback, force DCD in low, IRQ out inactive";
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ri_sts_ch 1 "In loopback, force RI input low";
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rts 1 "Force RTS output active (low)";
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dtr 1 "Force DTR output active (low)";
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};
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register LSR ro addr (base, 0x14) "Line status" {
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_ 24;
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rx_fifo_sts 1 "RX FIFO error";
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tx_sr_e 1 "THR and TX FIFO empty";
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tx_fifo_e 1 "THR empty";
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rx_bi 1 "RX break detected";
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rx_fe 1 "RX FIFO framing error";
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rx_pe 1 "RX FIFO parity error";
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rx_oe 1 "RX FIFO overflow";
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rx_fifo_e 1 "RX FIFO not empty";
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};
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register XON2 rw also addr (base, 0x14) "XON2 character" {
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_ 24;
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xon_word2 8 "XON2 character";
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};
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register TCR rw addr (base, 0x18) "Transmission control" {
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_ 24;
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rx_fifo_trig_start 4 "RX FIFO trigger level to RESTORE transmission";
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rx_fifo_trig_halt 4 "RX FIFO trigger level to HALT transmission";
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};
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register XOFF1 rw also addr (base, 0x18) "XOFF1 character" {
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_ 24;
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xoff_word1 8 "XOFF1 character";
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};
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register MSR ro also addr (base, 0x18) "Modem status" {
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_ 24;
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ncd_sts 1 "Complement of DCD input";
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nri_sts 1 "Complement of RI input";
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ndsr_sts 1 "Complement of DSR input";
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ncts_sts 1 "Complement of CTS input";
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dcd_sts 1 "DCD input changed. Cleared on read.";
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ri_sts 1 "RI input changed. Cleared on read.";
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dsr_sts 1 "DSR input changed. Cleared on read.";
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cts_sts 1 "CTS input changed. Cleared on read.";
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};
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register SPR rw addr (base, 0x1c) "Scratchpad" {
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_ 24;
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spr_word 8 "Scratchpad";
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};
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register TLR rw also addr (base, 0x1c) "Trigger level" {
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_ 24;
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rx_fifo_trig_dma 4 "RX FIFO trigger level";
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tx_fifo_trig_dma 4 "TX FIFO trigger level";
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};
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register XOFF2 rw also addr (base, 0x1c) "XOFF2 character" {
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_ 24;
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xoff_word2 8 "XOFF2 character";
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};
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constants serial_mode "Serial mode" {
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sm_uart16x = 0x0 "UART 16x mode";
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sm_sir = 0x1 "SIR mode";
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sm_uart16xauto = 0x2 "UART 16x auto-baud";
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sm_uart13x = 0x3 "UART 13x mode";
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sm_mir = 0x4 "MIR mode";
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sm_fir = 0x5 "FIR mode";
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sm_cir = 0x6 "CIR mode";
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sm_disable = 0x7 "Disable";
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};
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register MDR1 rw addr (base, 0x20) "Mode definition 1" {
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_ 24;
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frame_end_mode 1 "0 = Frame length method, 1 = EOT bit method";
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sip_mode 1 "Enable automatic SIP mode";
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sct 1 "Store and control IrDA transmission";
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set_txir 1 "IRTX pin output forced high";
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ir_sleep 1 "Enable IrDA/CIR sleep mode";
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mode_select 3 type(serial_mode) "Serial mode select";
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};
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register MDR2 rw addr (base, 0x24) "Mode definition 2" {
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_ 24;
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set_txir_alt 1 "Enable alternate mode for SET_TXIR";
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irrxinvert 1 "IrDA mode: Invert RX pin";
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cir_pulse_mode 2 "CIR pulse modulation width";
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uart_pulse 1 "UART mode: Enable pulse shaping";
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sts_fifo_trig 2 "IrDA mode: Frame status FIFO threshold";
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irtx_underrun 1 "IrDA transmission underrun";
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};
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constants parity_type width(2) "Parity type" {
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par_none = 0b00 "No parity";
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par_spc = 0b01 "Space parity";
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par_even = 0b10 "Even parity";
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par_odd = 0b11 "Odd parity";
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};
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constants baud_rate width(5) "Baud rate" {
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baud_none = 0x0 "No speed specified";
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baud115200 = 0x1 "115200 baud";
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baud57600 = 0x2 "57600 baud";
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baud38400 = 0x3 "38400 baud";
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baud28800 = 0x4 "28800 baud";
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baud19200 = 0x5 "19200 baud";
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baud14400 = 0x6 "14400 baud";
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baud9600 = 0x7 "9600 baud";
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baud4800 = 0x8 "4800 baud";
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baud2400 = 0x9 "2400 baud";
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baud1200 = 0xA "1200 baud";
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};
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register UASR ro addr(base, 0x38) "Autobauding status" {
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_ 24;
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parity 2 type(parity_type) "Parity";
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bit_by_char 1 "1=8 bits per char";
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speed 5 type(baud_rate) "Baud rate";
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};
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register ACR rw addr(base, 0x3C) "Auxiliary control" {
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_ 24;
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pulse_type 1 "Pulse width (1 = 1.6us, 0 = 3/16 baud";
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sd_mod 1 "SD pin set to low if 1";
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dis_ir_rx 1 "Disable RX input";
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dis_tx_underrun 1 "TX underrun is disabled";
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send_sip 1 "Send serial IR interaction pulse (SIP)";
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sctx_en 1 "Store and controlled TX start";
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abort_en 1 "Frame abort enable";
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eot_en 1 "End-of-transmission bit";
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};
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register SCR rw addr (base, 0x40) "Supplementary control" {
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_ 24;
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rx_trig_granu1 1 "Enable granularity 1 trigger RX level";
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tx_trig_granu1 1 "Enable granularity 1 trigger TX level";
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dsr_it 1 "Enable DSR interrupt";
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rx_cts_dsr_wake_up_enable 1 "Enable wake-up interrupt";
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tx_empty_ctl_it 1 "Enable THR interrupt on TX FIFO empty";
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dma_mode_2 2 "DMA mode select";
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dma_mode_ctl 1 "0 = set DMA mode via 1=FCR[3], 0=SCR[2:1]";
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};
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register SSR rw addr (base, 0x44) "Supplementary status" {
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_ 29;
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dma_counter_rst 1 rw "Reset DMA counter on FIFO reset";
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rx_cts_dsr_wake_up_sts 1 ro "Falling edge detected on RX, CTS, or DSR";
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tx_fifo_full 1 ro "TX FIFO is full";
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};
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register MVR ro addr (base, 0x50) "Module version" type(uint32);
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register SYSC rw addr (base, 0x54) "System configuration" {
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_ 27;
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idlemode 2 "Power management idle mode";
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enawakeup 1 "Enable wake-up capability";
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softreset 1 "Soft-reset the module";
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autoidle 1 "Enable automatic OCP clock gating";
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};
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register SYSS ro addr (base, 0x58) "System status" {
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_ 31;
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resetdone 1 "Reset complete";
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};
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register WER rw addr (base, 0x5C) "Wakeup enable" {
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_ 24;
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tx_wakeup 1 "TX event can wake up system";
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rx_lsi 1 "Receiver line status interrupt can wakeup";
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rhr_int 1 "RHR can wake up system";
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rx_activity 1 "RX activity can wake up system";
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dcd_cd_activity 1 "DCD CD activity can wake up system";
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ri_activity 1 "RI activity can wake up system";
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dsr_activity 1 "DSR activity can wake up system";
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cts_activity 1 "CTS activity can wake up system";
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};
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register CPFS rw addr (base, 0x60) "Carrier frequency prescaler" {
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_ 24;
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scale 8 "System clock freq. prescaler (12x multiple)";
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};
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register RFLVL ro addr (base, 0x64) "RX FIFO level" {
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_ 24;
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lvl 8 ro "Receive FIFO level";
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};
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register TFLVL ro addr (base, 0x68) "TX FIFO level" {
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_ 24;
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lvl 8 ro "Transmit FIFO level";
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};
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register IER2 rw addr (base, 0x6C) "Interrupt enable 2" {
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_ 30;
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tfe 1 rw "Transmit FIFO empty";
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rfe 1 rw "Receive FIFO empty";
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};
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register ISR2 rw addr (base, 0x70) "Interrupt status 2" {
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_ 30;
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tfs 1 rw "Transmit FIFO empty";
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rfs 1 rw "Receive FIFO empty";
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};
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register FSEL rw addr (base, 0x74) "Frequency selection" {
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_ 24;
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f 8 rw "Frequency";
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};
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register MDR3 rw addr (base, 0x80) "Mode definiton register 3" {
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_ 29;
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tx_dma_th 1 "Enable to set different TXDMA threshold";
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ndef_freq 1 "Enable NONDEFAULT fclk frequencies";
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d_cir_rx_demod 1 "Disable CIR RX demodulation";
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};
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register TXDT rw addr (base, 0x84) "Transmit DMA threshold" {
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_ 24;
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tdt 8 rw "Threshold";
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};
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};
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