164 lines
3.5 KiB
C
164 lines
3.5 KiB
C
/**
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* \file plat_arm_vm.c
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* \brief
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*/
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/*
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* Copyright (c) 2016 ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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#include <kernel.h>
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#include <offsets.h>
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#include <arch/arm/platform.h>
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#include <serial.h>
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#include <arch/arm/lpuart.h>
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#include <arch/arm/gic.h>
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#include <getopt/getopt.h>
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#include <sysreg.h>
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#include <dev/armv8_dev.h>
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#include <barrelfish_kpi/arm_core_data.h>
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#include <psci.h>
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#include <arch/armv8/global.h>
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#include <maps/imx8x_map.h>
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/* RAM starts at 0, provided by the MMAP */
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lpaddr_t phys_memory_start= 0;
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/*
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* ----------------------------------------------------------------------------
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* GIC
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* ----------------------------------------------------------------------------
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*/
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lpaddr_t platform_gic_distributor_base = 0x51a00000;
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lpaddr_t platform_gic_redistributor_base = 0x51b00000;
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/*
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* ----------------------------------------------------------------------------
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* UART
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* ----------------------------------------------------------------------------
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*/
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/*
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* ----------------------------------------------------------------------------
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* Timer
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* ----------------------------------------------------------------------------
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*/
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#define GLOBAL_TIMER_INTERRUPT 30
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/* the maximum number of UARTS supported */
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#define MAX_NUM_UARTS 1
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/* the serial console port */
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unsigned int serial_console_port = 0;
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/* the debug console port */
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unsigned int serial_debug_port = 0;
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/* the number of physical ports */
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unsigned serial_num_physical_ports = 1;
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/* uart bases */
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lpaddr_t platform_uart_base[MAX_NUM_UARTS] =
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{
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0x5A090000
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};
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/* uart sizes */
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size_t platform_uart_size[MAX_NUM_UARTS] =
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{
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0x10000
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};
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errval_t serial_init(unsigned port, bool initialize_hw)
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{
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lvaddr_t base = local_phys_to_mem(platform_uart_base[port]);
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lpuart_init(port, base, initialize_hw);
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return SYS_ERR_OK;
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};
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/*
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* Do any extra initialisation for this particular CPU (e.g. A9/A15).
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*/
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void platform_revision_init(void)
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{
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}
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/*
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* Figure out how much RAM we have
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*/
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size_t platform_get_ram_size(void)
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{
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return 0;
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}
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/*
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* Boot secondary processors
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*/
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errval_t platform_boot_core(hwid_t target, genpaddr_t gen_entry, genpaddr_t context)
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{
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printk(LOG_NOTE, "Invoking PSCI on: cpu=0x%lx, entry=0x%lx, context=0x%lx\n", target, gen_entry, context);
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struct armv8_core_data *cd = (struct armv8_core_data *)local_phys_to_mem(context);
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cd->page_table_root = armv8_TTBR1_EL1_rd(NULL);
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cd->cpu_driver_globals_pointer = (uintptr_t)global;
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__asm volatile("dsb sy\n"
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"dmb sy\n"
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"isb \n");
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return psci_cpu_on(target, gen_entry, context);
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}
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void platform_notify_bsp(lpaddr_t *mailbox)
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{
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}
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/*
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* Return the core count
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*/
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size_t platform_get_core_count(void)
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{
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return 4;
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}
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/*
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* Print system identification. MMU is NOT yet enabled.
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*/
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void platform_print_id(void)
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{
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}
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/*
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* Fill out provided `struct platform_info`
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*/
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void platform_get_info(struct platform_info *pi)
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{
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pi->arch = PI_ARCH_ARMV8A;
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pi->platform = PI_PLATFORM_IMX8X;
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}
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uint32_t platform_get_timer_interrupt(void){
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return GLOBAL_TIMER_INTERRUPT;
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}
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void armv8_get_info(struct arch_info_armv8 *ai)
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{
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}
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void platform_get_dev_range(lpaddr_t* start, size_t* size){
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*start = IMX8X_START_DEV_RANGE;
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*size = IMX8X_SIZE_DEV_RANGE;
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}
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