119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
/**
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* \file
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* \brief ARM pl011 UART kernel-level driver.
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*/
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/*
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* Copyright (c) 2007, 2008, ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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#include <arch/arm/rpi3_miniuart.h>
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#include <kernel.h>
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#include <paging_kernel_arch.h>
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#include <arch/arm/arm.h>
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#include <arch/arm/platform.h>
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#include <serial.h>
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#include <dev/rpi3_miniuart_dev.h>
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static rpi3_miniuart_t uart;
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#define MSG(format, ...) printk( LOG_NOTE, "rpi3_miniuart: "format, ## __VA_ARGS__ )
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/*
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* \brief Initialize a serial port. The MMU is turned on.
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*/
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void rpi3_miniuart_init(lvaddr_t base, bool hwinit)
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{
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// assert(paging_mmu_enabled());
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// assert(port < serial_num_physical_ports);
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//
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// pl011_uart_t *u = &uarts[port];
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//
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// // [Re]initialize the Mackerel state for the UART
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rpi3_miniuart_initialize(&uart, (mackerel_addr_t) base);
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//
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// if (hwinit) {
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// // Mask all interrupts: set all bits to zero
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// pl011_uart_IMSC_rawwr(u, INTERRUPTS_MASK);
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//
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// // Disable the UART before reconfiguring it.
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// pl011_uart_CR_uarten_wrf(u, 0);
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//
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// // Clear and enable the receive interrupt.
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// pl011_uart_ICR_rxic_wrf(u, 1);
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// pl011_uart_IMSC_rxim_wrf(u, 1);
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//
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// // Configure port to 38400 baud, 8 data, no parity, 1 stop (8-N-1)
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// //
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// // (This is a mild scam as system is running in QEMU)
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// //
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// // Note baud rate changes not committed in h/w until lcr_h
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// // written.
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// pl011_uart_IBRD_divint_wrf(u, 0xc); // Assuming UARTCLK is 7.3728MHz
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// pl011_uart_FBRD_divfrac_wrf(u, 0);
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//
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// /* Configure the line control register. */
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// pl011_uart_LCR_H_t lcr= (pl011_uart_LCR_H_t)0;
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// /* Disable FIFOs. There's no way to get an interrupt when a single
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// * character arrives with FIFOs, so it's useless as a console. */
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// lcr= pl011_uart_LCR_H_fen_insert(lcr, 0);
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// /* Eight data bits. */
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// lcr= pl011_uart_LCR_H_wlen_insert(lcr, pl011_uart_bits8);
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// /* No parity. */
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// lcr= pl011_uart_LCR_H_pen_insert(lcr, 0);
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// /* One stop bit. */
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// lcr= pl011_uart_LCR_H_stp2_insert(lcr, 0);
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// pl011_uart_LCR_H_wr(u, lcr);
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//
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// /* Configure the main control register. */
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// pl011_uart_CR_t cr = (pl011_uart_CR_t)0;
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// /* No flow control. */
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// cr= pl011_uart_CR_ctsen_insert(cr, 0);
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// cr= pl011_uart_CR_rtsen_insert(cr, 0);
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// /* Enable transmit and receive. */
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// cr= pl011_uart_CR_txe_insert(cr, 1);
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// cr= pl011_uart_CR_rxe_insert(cr, 1);
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// /* Enable UART. */
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// cr= pl011_uart_CR_uarten_insert(cr, 1);
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// pl011_uart_CR_wr(u, cr);
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// }
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}
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/*
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* \brief Put a character to the port
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*/
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void serial_putchar(unsigned port, char c)
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{
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while(rpi3_miniuart_STAT_txff_rdf(&uart) == 1) ;
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rpi3_miniuart_DR_rawwr(&uart, c);
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// assert(port < MAX_PORTS);
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// pl011_uart_t *u = &uarts[port];
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// assert(u->base != 0);
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//
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// while(pl011_uart_FR_txff_rdf(u) == 1) ;
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// pl011_uart_DR_rawwr(u, c);
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}
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/*
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* \brief Read a character from a port
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*/
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char serial_getchar(unsigned port)
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{
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// assert(port < MAX_PORTS);
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// pl011_uart_t *u = &uarts[port];
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// assert(u->base != 0);
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//
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// /* Wait for data. */
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// while(pl011_uart_FR_rxfe_rdf(u) == 1);
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//
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// /* Acknowledge any interrupt. */
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// pl011_uart_ICR_rxic_wrf(u, 1);
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//
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// return (char)pl011_uart_DR_data_rdf(u);
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return 0;
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}
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