53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/**
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* \file
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* \brief
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*/
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/*
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* Copyright (c) 2010, ETH Zurich.
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* Copyright (c) 2015, Hewlett Packard Enterprise Development LP.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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#ifndef ARCH_AARCH64_BARRELFISH_KPI_SPINLOCKS_H
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#define ARCH_AARCH64_BARRELFISH_KPI_SPINLOCKS_H
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#include <barrelfish_kpi/asm_inlines_arch.h>
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typedef volatile uint32_t spinlock_t;
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// Refer to ARM Manual - Load-Acquire Exclusive, Store-Release Exclusive and barriers
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static inline void acquire_spinlock(spinlock_t *spinlock)
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{
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unsigned long tmp;
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__asm volatile(
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" sevl\n"
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" prfm pstl1keep, %1\n"
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"1: wfe\n"
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" ldaxr %w0, %1\n"
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" cbnz %w0, 1b\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 1b\n"
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: "=&r" (tmp), "+Q" (*spinlock)
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: "r" (1)
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: "memory");
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dmb();
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}
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static inline void release_spinlock(spinlock_t *spinlock)
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{
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dmb();
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__asm volatile(
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" stlr %w1, %0\n"
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: "=Q" (*spinlock) : "r" (0) : "memory");
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}
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#endif // ARCH_AARCH64_BARRELFISH_KPI_SPINLOCKS_H
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