271 lines
13 KiB
Plaintext
271 lines
13 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_gptimer2_l4interconnect.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_gptimer2_l4interconnect msbfirst ( addr base ) "" {
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register gpt_tidr ro addr(base, 0x0) "This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." type(uint32);
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constants clockactivity_status width(2) "" {
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CLOCKACTIVITY_0 = 0 "Functional clock can be switched-off ; L4 clock can be switched-off.";
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CLOCKACTIVITY_1 = 1 "Functional clock can be switched-off ; L4 clock is maintained during wake-up period.";
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CLOCKACTIVITY_2 = 2 "Functional clock is maintained during wake-up period; L4 clock can be switched-off.";
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CLOCKACTIVITY_3 = 3 "Functional clock is maintained during wake-up period; L4 clock is maintained during wake-up period.";
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};
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constants emufree_status width(1) "" {
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EMUFREE_0 = 0 "Timer counter frozen in emulation";
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EMUFREE_1 = 1 "Timer counter free-running in emulation";
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};
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constants idlemode_status width(2) "" {
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IDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally.";
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IDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged.";
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IDLEMODE_2 = 2 "Smart-idle. Acknowledgment to an idle request is given based on the internal activity of the module.";
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IDLEMODE_3 = 3 "Reserved, do not use.";
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};
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constants enawakeup_status width(1) "" {
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ENAWAKEUP_0 = 0 "No wake-up line assertion in idle mode";
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ENAWAKEUP_1 = 1 "Wake-up line assertion enabled in smart-idle mode.";
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};
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constants softreset_status width(1) "" {
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SOFTRESET_0 = 0 "Normal mode";
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SOFTRESET_1 = 1 "The module is reset.";
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};
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constants autoidle_status width(1) "" {
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AUTOIDLE_0 = 0 "L4 clock is free-running.";
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AUTOIDLE_1 = 1 "Automatic L4 clock gating strategy is applied, based on the L4 interface activity.";
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};
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register gpt1ms_tiocp_cfg addr(base, 0x10) "This register controls the various parameters of the OCP interface." {
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_ 22 mbz;
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clockactivity 2 rw type(clockactivity_status) "Clock activity";
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_ 2 mbz;
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emufree 1 rw type(emufree_status) "Emulation mode";
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idlemode 2 rw type(idlemode_status) "Power management, req/ack control";
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enawakeup 1 rw type(enawakeup_status) "Wake-up feature global control";
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softreset 1 rw type(softreset_status) "Software reset. This bit is automatically reset by the hardware. During reads, it always returns 0.";
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autoidle 1 rw type(autoidle_status) "Internal L4 clock gating strategy";
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};
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constants resetdone_status width(1) "" {
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RESETDONE_0_r = 0 "Internal module reset in ongoing.";
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RESETDONE_1_r = 1 "Reset complete";
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};
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register gpt_tistat addr(base, 0x14) "This register provides status information about the module, excluding interrupt status information." {
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_ 31 mbz;
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resetdone 1 ro type(resetdone_status) "Internal reset monitoring";
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};
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constants tcar_it_flag_status width(1) "" {
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TCAR_IT_FLAG_0 = 0 "No capture interrupt request";
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TCAR_IT_FLAG_1 = 1 "Capture interrupt request";
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};
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constants ovf_it_flag_status width(1) "" {
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OVF_IT_FLAG_0 = 0 "No overflow interrupt request";
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OVF_IT_FLAG_1 = 1 "Overflow interrupt pending";
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};
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constants mat_it_flag_status width(1) "" {
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MAT_IT_FLAG_0 = 0 "No compare interrupt request";
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MAT_IT_FLAG_1 = 1 "Compare interrupt pending";
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};
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register gpt_tisr addr(base, 0x18) "The timer status register is used to determine which of the timer events requested an interrupt." {
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_ 29 mbz;
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tcar_it_flag 1 rw type(tcar_it_flag_status) "Indicates when an external pulse transition of the correct polarity is detected on external pin GPTi_EVENT_CAPTURE";
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ovf_it_flag 1 rw type(ovf_it_flag_status) "TCRR overflow";
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mat_it_flag 1 rw type(mat_it_flag_status) "The compare result of TCRR and TMAR";
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};
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constants tcar_it_ena_status width(1) "" {
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TCAR_IT_ENA_0 = 0 "Disable capture interrupt.";
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TCAR_IT_ENA_1 = 1 "Enable capture interrupt.";
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};
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constants ovf_it_ena_status width(1) "" {
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OVF_IT_ENA_0 = 0 "Disable overflow interrupt.";
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OVF_IT_ENA_1 = 1 "Enable overflow interrupt.";
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};
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constants mat_it_ena_status width(1) "" {
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MAT_IT_ENA_0 = 0 "Disable match interrupt.";
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MAT_IT_ENA_1 = 1 "Enable match interrupt.";
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};
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register gpt_tier addr(base, 0x1C) "This register controls (enable/disable) the interrupt events." {
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_ 29 mbz;
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tcar_it_ena 1 rw type(tcar_it_ena_status) "Capture interrupt enable";
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ovf_it_ena 1 rw type(ovf_it_ena_status) "Overflow interrupt enable";
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mat_it_ena 1 rw type(mat_it_ena_status) "Match interrupt enable";
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};
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constants tcar_wup_ena_status width(1) "" {
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TCAR_WUP_ENA_0 = 0 "Disable capture wake-up.";
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TCAR_WUP_ENA_1 = 1 "Enable capture wake-up.";
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};
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constants ovf_wup_ena_status width(1) "" {
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OVF_WUP_ENA_0 = 0 "Disable overflow wake-up.";
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OVF_WUP_ENA_1 = 1 "Enable overflow wake-up.";
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};
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constants mat_wup_ena_status width(1) "" {
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MAT_WUP_ENA_0 = 0 "Disable match wake-up.";
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MAT_WUP_ENA_1 = 1 "Enable match wake-up.";
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};
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register gpt_twer addr(base, 0x20) "This register controls (enable/disable) the wake-up feature on specific interrupt events." {
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_ 29 mbz;
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tcar_wup_ena 1 rw type(tcar_wup_ena_status) "Capture wake-up enable";
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ovf_wup_ena 1 rw type(ovf_wup_ena_status) "Overflow wake-up enable";
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mat_wup_ena 1 rw type(mat_wup_ena_status) "Match wake-up enable";
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};
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constants gpo_cfg_status width(1) "" {
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GPO_CFG_0 = 0 "GPTi_PORGPOCFG drives 0.";
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GPO_CFG_1 = 1 "GPTi_PORGPOCFG drives 1.";
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};
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constants capt_mode_status width(1) "" {
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CAPT_MODE_0 = 0 "Single capture: Capture the first enabled capture event in TCAR1.";
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CAPT_MODE_1 = 1 "Capture on second event: Capture the second enabled capture event in TCAR2.";
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};
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constants pt_status width(1) "" {
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PT_0 = 0 "Pulse modulation";
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PT_1 = 1 "Toggle modulation";
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};
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constants trg_status width(2) "" {
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TRG_0 = 0 "No trigger";
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TRG_1 = 1 "Trigger on overflow.";
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TRG_2 = 2 "Trigger on overflow and match.";
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TRG_3 = 3 "Reserved";
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};
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constants tcm_status width(2) "" {
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TCM_0 = 0 "No capture";
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TCM_1 = 1 "Capture on rising edges of GPTi_EVENT_CAPTURE pin";
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TCM_2 = 2 "Capture on falling edges of GPTi_EVENT_CAPTURE pin";
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TCM_3 = 3 "Capture on both edges of GPTi_EVENT_CAPTURE pin";
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};
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constants ce_status width(1) "" {
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CE_0 = 0 "Compare mode is disable.";
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CE_1 = 1 "Compare mode is enable.";
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};
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constants pre_status width(1) "" {
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PRE_0 = 0 "The TIMER clock input pin clocks the counter.";
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PRE_1 = 1 "The divided input pin clocks the counter.";
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};
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constants ar_status width(1) "" {
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AR_0 = 0 "One shot timer";
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AR_1 = 1 "Autoreload timer";
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};
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constants st_status width(1) "" {
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ST_0 = 0 "Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed.";
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ST_1 = 1 "Start timer";
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};
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register gpt_tclr addr(base, 0x24) "This register controls optional features specific to the timer functionality." {
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_ 17 mbz;
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gpo_cfg 1 rw type(gpo_cfg_status) "General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, .";
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capt_mode 1 rw type(capt_mode_status) "Capture mode select bit (first/second)";
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pt 1 rw type(pt_status) "Pulse or toggle mode on GPTi_PWM_out output pin";
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trg 2 rw type(trg_status) "Trigger output mode on GPTi_PWM_out output pin";
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tcm 2 rw type(tcm_status) "Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)";
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scpwm 1 rw type(idlemode_status) "Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off.";
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ce 1 rw type(ce_status) "Compare enable";
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pre 1 rw type(pre_status) "Prescaler enable";
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ptv 3 rw "Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods.";
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ar 1 rw type(ar_status) "Autoreload mode";
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st 1 rw type(st_status) "Start/stop timer control";
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};
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register gpt_tcrr rw addr(base, 0x28) "This register holds the value of the internal counter." type(uint32);
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register gpt_tldr rw addr(base, 0x2C) "This register holds the timer load value." type(uint32);
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register gpt_ttgr rw addr(base, 0x30) "The read value of this register is always 0xFFFF FFFF." type(uint32);
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register gpt_twps addr(base, 0x34) "This register contains the write posting bits for all writable functional registers." {
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_ 27 mbz;
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w_pend_tmar 1 ro "When equal to 1, a write is pending to theGPT_TMAR register.";
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w_pend_ttgr 1 ro "When equal to 1, a write is pending to theGPT_TTGR register.";
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w_pend_tldr 1 ro "When equal to 1, a write is pending to theGPT_TLDR register.";
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w_pend_tcrr 1 ro "When equal to 1, a write is pending to theGPT_TCRR register.";
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w_pend_tclr 1 ro "When equal to 1, a write is pending to theGPT_TCLR register.";
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};
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register gpt_tmar rw addr(base, 0x38) "The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." type(uint32);
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register gpt_tcar1 ro addr(base, 0x3C) "This register holds the first captured value of the counter register." type(uint32);
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constants posted_status width(1) "" {
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POSTED_0 = 0 "Posted mode inactive: Delay the command accept output signal.";
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POSTED_1 = 1 "Posted mode active";
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};
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constants sft_status width(1) "" {
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SFT_0 = 0 "Software reset is disabled.";
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SFT_1 = 1 "Software reset is enabled.";
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};
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register gpt_tsicr addr(base, 0x40) "Timer synchronous interface control register" {
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_ 29 mbz;
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posted 1 rw type(posted_status) "Posted mode selection";
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sft 1 rw type(sft_status) "This bit resets all the functional part of the module.";
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_ 1 mbz;
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};
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register gpt_tcar2 ro addr(base, 0x44) "This register holds the second captured value of the counter register." type(uint32);
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register gpt_tpir rw addr(base, 0x48) "This register is used for 1-ms tick generation. The TPIR register holds the value of the positive increment. The value of this register is added to the value of TCVR to determine whether next value loaded in TCRR is the subperiod value or the overperiod value." type(uint32);
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register gpt_tnir rw addr(base, 0x4C) "This register is used for 1-ms tick generation. The TNIR register holds the value of the negative increment. The value of this register is added to the value of the TCVR to determine whether next value loaded in TCRR is the subperiod value or the overperiod value." type(uint32);
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register gpt_tcvr rw addr(base, 0x50) "This register is used for 1-ms tick generation. The TCVR register determines whether next value loaded in TCRR is the subperiod value or the overperiod value." type(uint32);
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register gpt_tocr addr(base, 0x54) "This register is used to mask the tick interrupt for a selected number of ticks." {
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_ 8 mbz;
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ovf_counter_value 24 rw "Number of overflow events";
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};
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register gpt_towr addr(base, 0x58) "This register holds the number of masked overflow interrupts." {
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_ 8 mbz;
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ovf_wrapping_value 24 rw "Number of masked interrupts";
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};
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}; |