137 lines
3.6 KiB
Plaintext
137 lines
3.6 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* xeon_phi_apic.dev
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*
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* description: register definitions for the Xeon Phi APIC register
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*
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* Note: this is for raising interrupts to the other parts.
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*/
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device xeon_phi_apic lsbfirst ( addr base ) "Intel Xeon Phi APIC register" {
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constants irq_vec width(32) "Interupt Vectors" {
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vec_bsp = 229;
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};
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constants irq_idx width(3) "Interrupt Register Index" {
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vnet = 0;
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sht = 1;
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hvc = 2;
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virtio = 3;
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pm = 4;
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unused = 5;
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unused2 = 6;
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bootstrap = 7;
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};
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constants dst_shorthand "Destination shorthand" {
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none = 0b00 "No shorthand";
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self = 0b01 "Self";
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all_inc = 0b10 "All including self";
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all_exc = 0b11 "All excluding self";
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};
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constants dst_mode "Destination mode" {
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dst_phys = 0b00 "Physical";
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dst_log = 0b01 "Logical";
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};
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constants int_level "Interrupt level" {
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lvl_clr = 0b00 "Clear";
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lvl_set = 0b01 "Set";
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};
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constants vdm "Vector delivery mode" {
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fixed = 0b000 "Fixed";
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lowest = 0b001 "Lowest priority";
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smi = 0b010 "SMI";
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nmi = 0b100 "NMI";
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init = 0b101 "INIT";
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startup = 0b110 "Start Up";
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extint = 0b111 "ExtINT";
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};
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constants trigm "Trigger mode" {
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edge = 0 "Edge";
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level = 1 "Level";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_RESET
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* Register Access: CRU
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*/
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register id rw addr(base, 0xA800) "APIC Identification Register" {
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_ 23;
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id 9 "apic id";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_RESET
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* Register Access: CRU
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*/
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register version rw addr(base, 0xA804) "APIC Version Register" {
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ver 8 "version";
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_ 8;
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max_lvt 8 "max LVT entry";
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_ 8;
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_RESET
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* Register Access: CRU
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*/
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register pr rw addr(base, 0xA808) "APIC Priority Register" {
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value 32 "Value";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_RESET
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* Register Access: CRU
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* Number: 26
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*/
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regarray rt rw addr(base, 0xA840) [26] "APIC Redirection Table" {
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value 64 "Value";
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};
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/*
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* Protection Level: Ring 0
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* Visibility: Host / Coprocessor
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* Reset Dmain: GRPB_RESET
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* Register Access: CRU
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* Number: 8
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*/
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regarray icr_lo rw addr(base, 0xA9D0) [8; 0x8] "APIC Interrupt Command Register 0 to 7" {
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vector 8 "Vector";
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dlv_mode 3 type(vdm) "Delivery mode";
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dst_mode 1 type(dst_mode) "Destination mode";
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dlv_stat 1 ro "Delivery status";
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boot_notify 1 "Boot notify bit";
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level 1 type(int_level) "Level";
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trig_mode 1 type(trigm) "Trigger mode";
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_ 2;
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dst_short 2 type(dst_shorthand) "Destination shorthand";
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_ 12;
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};
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regarray icr_hi rw addr(base, 0xA9D4) [8; 0x8] "APIC Interrupt Command Register 0 to 7" {
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dest 32 "Destination field";
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};
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}; |