170 lines
5.6 KiB
C
170 lines
5.6 KiB
C
/*
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* Copyright (c) 2007,2008,2009,2015, ETH Zurich.
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* Copyright (c) 2015, Hewlett Packard Enterprise Development LP.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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#ifndef KERNEL_ARMV8_EXCEPTIONS_H
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#define KERNEL_ARMV8_EXCEPTIONS_H
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#define AARCH64_EVECTOR_UNDEF 0x00
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#define AARCH64_EVECTOR_EL0_SYNC 0x01
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#define AARCH64_EVECTOR_EL0_IRQ 0x02
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#define AARCH64_EVECTOR_EL0_FIQ 0x03
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#define AARCH64_EVECTOR_EL0_SERROR 0x04
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#define AARCH64_EVECTOR_EL1_SYNC 0x05
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#define AARCH64_EVECTOR_EL1_IRQ 0x06
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#define AARCH64_EVECTOR_EL1_FIQ 0x07
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#define AARCH64_EVECTOR_EL1_SERROR 0x08
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#define AARCH64_EVECTOR_EL2_SYNC 0x09
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#define AARCH64_EVECTOR_EL2_IRQ 0x0a
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#define AARCH64_EVECTOR_EL2_FIQ 0x0b
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#define AARCH64_EVECTOR_EL2_SERROR 0x0c
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#define AARCH32_EVECTOR_EL0_SYNC 0x10
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#define AARCH32_EVECTOR_EL0_IRQ 0x11
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#define AARCH32_EVECTOR_EL0_FIQ 0x12
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#define AARCH32_EVECTOR_EL0_SERROR 0x13
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#define WAIT_FOR_INTERRUPT_MAGIC 0x1234
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#if !defined(__ASSEMBLER__)
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enum aarch64_exception_class {
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aarch64_ec_unknown = 0x0,
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aarch64_ec_wfi = 0x1,
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aarch64_ec_mcr_cp15 = 0x3,
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aarch64_ec_mcrr_cp15 = 0x4,
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aarch64_ec_mcr_cp14 = 0x5,
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aarch64_ec_ldc_cp14 = 0x6,
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aarch64_ec_fpen = 0x7,
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aarch64_ec_mcr_cp10 = 0x8,
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aarch64_ec_mcrr_cp14 = 0xc,
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aarch64_ec_il = 0xe,
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aarch64_ec_svc_aa32 = 0x11,
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aarch64_ec_hvc_aa32 = 0x12,
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aarch64_ec_smc_aa32 = 0x13,
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aarch64_ec_svc_aa64 = 0x15,
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aarch64_ec_hvc_aa64 = 0x16,
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aarch64_ec_smc_aa64 = 0x17,
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aarch64_ec_mrs = 0x18,
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aarch64_ec_impl = 0x1f,
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aarch64_ec_iabt_low = 0x20,
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aarch64_ec_iabt_high = 0x21,
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aarch64_ec_pc_align = 0x22,
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aarch64_ec_dabt_low = 0x24,
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aarch64_ec_dabt_high = 0x25,
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aarch64_ec_sp_align = 0x26,
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aarch64_ec_fpu_aa32 = 0x28,
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aarch64_ec_fpu_aa64 = 0x2c,
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aarch64_ec_serror = 0x2f,
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aarch64_ec_bkpt_low = 0x30,
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aarch64_ec_bkpt_high = 0x31,
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aarch64_ec_step_low = 0x32,
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aarch64_ec_step_high = 0x33,
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aarch64_ec_wpt_low = 0x34,
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aarch64_ec_wpt_high = 0x35,
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aarch64_ec_bkpt_soft = 0x38,
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aarch64_ec_bkpt_el2 = 0x3a,
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aarch64_ec_brk = 0x3c,
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};
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enum aarch64_dsfc {
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aarch64_dsfc_size_l0 = 0x00,
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aarch64_dsfc_size_l1 = 0x01,
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aarch64_dsfc_size_l2 = 0x02,
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aarch64_dsfc_size_l3 = 0x03,
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aarch64_dsfc_trans_l0 = 0x04,
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aarch64_dsfc_trans_l1 = 0x05,
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aarch64_dsfc_trans_l2 = 0x06,
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aarch64_dsfc_trans_l3 = 0x07,
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aarch64_dsfc_flag_l1 = 0x09,
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aarch64_dsfc_flag_l2 = 0x0a,
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aarch64_dsfc_flag_l3 = 0x0b,
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aarch64_dsfc_perm_l1 = 0x0d,
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aarch64_dsfc_perm_l2 = 0x0e,
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aarch64_dsfc_perm_l3 = 0x0f,
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aarch64_dsfc_external = 0x10,
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aarch64_dsfc_external_l0 = 0x14,
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aarch64_dsfc_external_l1 = 0x15,
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aarch64_dsfc_external_l2 = 0x16,
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aarch64_dsfc_external_l3 = 0x17,
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aarch64_dsfc_parity = 0x18,
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aarch64_dsfc_parity_l0 = 0x1c,
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aarch64_dsfc_parity_l1 = 0x1d,
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aarch64_dsfc_parity_l2 = 0x1e,
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aarch64_dsfc_parity_l3 = 0x1f,
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aarch64_dsfc_alighment = 0x21,
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aarch64_dsfc_tlb_confl = 0x30,
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aarch64_dsfc_impl1 = 0x34,
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aarch64_dsfc_impl2 = 0x35,
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aarch64_dsfc_sect_dom = 0x3d,
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aarch64_dsfc_page_dom = 0x3e,
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};
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#define CACHE_LINE_BYTES 64
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#define ETABLE_ADDR 0xffffffffffff0000
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#define ETABLE_SECTION_OFFSET 0xf000
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#define JUMP_TABLE_OFFSET 0x100
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#define ETABLE_PHYS_BASE 0x800f0000
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/* The exception vector table. */
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extern int vectors;
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/**
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* Handle page fault in user-mode process.
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*
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* This function should be called in SVC mode with interrupts disabled.
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*/
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void handle_user_page_fault(lvaddr_t fault_address,
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arch_registers_state_t* save_area,
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union registers_aarch64 *resume_area);
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/**
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* Handle undefined instruction fault in user-mode process.
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*
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* This function should be called in SVC mode with interrupts disabled.
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*/
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void handle_user_undef(lvaddr_t fault_address, enum aarch64_exception_class cause,
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arch_registers_state_t* save_area,
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union registers_aarch64 *resume_area);
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void handle_user_fault(lvaddr_t fault_address, uintptr_t cause,
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arch_registers_state_t* save_area)__attribute__((noreturn));
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/**
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* Handle faults in occuring in a priviledged mode.
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*
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* This function should be called with interrupts disabled.
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*/
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void fatal_kernel_fault(lvaddr_t epc, uint64_t spsr, uint64_t esr,
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uint64_t vector, arch_registers_state_t* save_area)
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__attribute__((noreturn));
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/**
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* Handle IRQs without saving any state, hence it should be called when
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* the state is properly saved and an interrupt occurs. Can happen
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* from EL0 interrupt after we saved the state and EL1 (kernel) interrupt.
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*
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* This function should be called with interrupts disabled.
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*/
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void nosave_handle_irq(void) __attribute__((noreturn));
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/**
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* Handle IRQs occuring in EL0. Expects a partially saved register
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* state. Stores the arguments and FPU state in the save_area.
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*
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* This function should be called with interrupts disabled.
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*/
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void save_handle_irq(arch_registers_state_t* save_area, uintptr_t fault_pc,
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uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3)
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__attribute__((noreturn));
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#endif // !defined(__ASSEMBLER__)
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#endif // __KERNEL_ARMV8_EXCEPTIONS_H__
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