60 lines
2.6 KiB
Plaintext
60 lines
2.6 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_intrconn_socket_cm2.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_intrconn_socket_cm2 msbfirst ( addr base ) "" {
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register revision_cm2 ro addr(base, 0x0) "This register contains the IP revision code for the CM2 part of the PRCM" type(uint32);
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constants idlest_status width(2) "" {
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IDLEST_0_r = 0 "Module is fully functional";
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IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
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IDLEST_2_r = 2 "Module is in Idle";
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IDLEST_3_r = 3 "Module is disabled";
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};
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constants modulemode_status width(2) "" {
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MODULEMODE_0 = 0 "Module is disabled by software. INTRCONN configuration port is not accessible.";
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MODULEMODE_1 = 1 "Module is managed automatically by hardware along with L3INSTR domain.";
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MODULEMODE_2_r = 2 "Reserved";
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MODULEMODE_3_r = 3 "Reserved";
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};
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register cm_cm2_profiling_clkctrl addr(base, 0x40) "This register manages the CM2_PROFILING clocks. [warm reset insensitive]" {
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_ 14 mbz;
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idlest 2 ro type(idlest_status) "Module idle status";
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_ 14 mbz;
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modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
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};
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register cm2_debug_cfg addr(base, 0xF0) "This register is used to configure the CM2's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. [warm reset insensitive]" {
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sel3 8 rw "Internal signal block select for debug word byte-3";
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sel2 8 rw "Internal signal block select for debug word byte-2";
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sel1 8 rw "Internal signal block select for debug word byte-1";
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sel0 8 rw "Internal signal block select for debug word byte-0";
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};
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}; |