207 lines
7.9 KiB
Plaintext
207 lines
7.9 KiB
Plaintext
/*
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* Copyright (c) 2016, ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* zynq_slcr.dev
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*
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* DESCRIPTION: Xilinx Zynq System-Level Control Registers
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*
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* This is derived from:
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*
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* Zynq-7000 All Programmable SoC Technical Reference Manual (UG585)
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*
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*/
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/* There are a lot of control registers packed into this block, and we've only
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* included those which we need so far. */
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device zynq_slcr msbfirst (addr base) "Zynq System-Level Control Registers" {
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regtype pll_ctrl "PLL Control" {
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_ 13;
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PLL_FDIV 7 rw "Feedback divisor for the PLL";
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_ 7;
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PLL_BYPASS_FORCE 1 rw "Force PLL bypass, regardless of pinstrap";
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PLL_BYPASS_QUAL 1 rw "Use bypass pinstrap value";
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_ 1;
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PLL_PWRDWN 1 rw "PLL power down";
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PLL_RESET 1 rw;
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};
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register ARM_PLL_CTRL addr(base, 0x100) "ARM PLL Control" type(pll_ctrl);
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register DDR_PLL_CTRL addr(base, 0x104) "DDR PLL Control" type(pll_ctrl);
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register IO_PLL_CTRL addr(base, 0x108) "IO PLL Control" type(pll_ctrl);
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constants clksrc "Clock source" {
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iopll0 = 0b00 "IO PLL";
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iopll1 = 0b01 "IO PLL";
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armpll = 0b10 "ARM PLL";
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ddrpll = 0b11 "DDR PLL";
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};
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register ARM_CLK_CTRL addr(base, 0x120) "CPU Clock Control" {
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_ 3;
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CPU_PERI_CLKACT 1 rw "Clock active";
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CPU_1XCLKACT 1 rw "CPU_1x clock control";
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CPU_2XCLKACT 1 rw "CPU_2x clock control";
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CPU_3OR2XCLKACT 1 rw "CPU_3X2x clock control";
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CPU_6OR4XCLKACT 1 rw "CPU_6X4x clock control";
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_ 10;
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DIVISOR 6 rw "Frequency divisor for the CPU clock source";
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_ 2;
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SRCSEL 2 rw type(clksrc) "PLL whence the clock is sourced";
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_ 4;
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};
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register UART_CLK_CTRL addr(base, 0x154) "UART Reference Clock Control" {
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_ 18;
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DIVISOR 6 rw "Divisor for UART controller source clock";
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_ 2;
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SRCSEL 2 rw type(clksrc) "PLL whence the clock is sourced";
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_ 2;
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CLKACT1 1 rw "UART1 reference clock control";
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CLKACT0 1 rw "UART0 reference clock control";
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};
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constants clk_621_mode "CPU Clock Ratios" {
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ratio_421 = 0b0 "4:2:1";
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ratio_631 = 0b1 "6:3:1";
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};
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register CLK_621_TRUE addr(base, 0x1c4) "CPU Clock Ratio Mode Select" {
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_ 31;
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CLK_621_TRUE 1 rw type(clk_621_mode) "CPU clock ratio";
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};
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register UART_RST_CTRL addr(base, 0x228) "UART Software Reset Control" {
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_ 28;
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UART1_REF_RST 1 rw "UART1 soft reset";
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UART0_REF_RST 1 rw "UART0 soft reset";
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UART1_CPU1X_RST 1 rw "UART1 AMBA reset";
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UART0_CPU1X_RST 1 rw "UART0 AMBA reset";
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};
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register BOOT_MODE addr(base, 0x25c) "Boot Mode Strapping Pins" {
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_ 27;
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PLL_BYPASS 1 ro "Bypass PLLs";
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BOOT_MODE 4 ro "Boot mode pins";
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};
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constants en_lo "Enable low" {
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enabled_lo = 0b0 "enabled";
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disabled_lo = 0b1 "disabled";
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};
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constants devcode "Device code" {
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dev_7z010 = 0x02 "7z010";
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dev_7z015 = 0x1b "7z015";
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dev_7z020 = 0x07 "7z020";
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dev_7z030 = 0x0c "7z030";
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dev_7z045 = 0x11 "7z045";
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};
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register PSS_IDCODE addr(base, 0x530) "SoC Identification" {
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REVISION 4 ro "Revision code";
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FAMILY 7 ro "Family code";
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SUBFAMILY 4 ro "Subfamily code";
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DEVICE_CODE 5 ro "Device code";
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MANUFACTURER_ID 11 ro "Manufacturer ID";
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_ 1;
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};
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constants mio_iotype "MIO Pin IO Standard" {
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mio_lvcmos18 = 0b001 "1.8V LVCMOS";
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mio_lvcmos25 = 0b010 "2.5V LVCMOS";
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mio_lvcmos33 = 0b011 "3.3V LVCMOS";
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mio_hstl = 0b100 "HSTL";
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};
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/* These registers control multiplexing on the MIO pins, which are not
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* routed via the FPGA. */
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regarray MIO_PIN addr(base, 0x700) [ 54 ] "MIO Pin Control" {
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_ 18;
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DisableRcvr 1 rw type(en_lo) "Disable HSTL input buffer when output-only";
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PULLUP 1 rw "Enable pullup";
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IO_Type 3 rw type(mio_iotype) "IO buffer type";
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Speed 1 rw "Fast CMOS edge";
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L3_SEL 3 rw "Level 3 multiplexer selector";
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L2_SEL 2 rw "Level 2 multiplexer selector";
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L1_SEL 1 rw "Level 1 multiplexer selector";
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L0_SEL 1 rw "Level 0 multiplexer selector";
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TRI_ENABLE 1 rw "Tri-state pin";
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};
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register MIO_LOOPBACK addr(base, 0x804) "MIO Pin Loopback" {
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_ 28;
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I2C0_LOOP_I2C1 1 rw "Loop I2C0 to I2C1";
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CAN0_LOOP_CAN1 1 rw "Loop CAN0 to CAN1";
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UA0_LOOP_UA1 1 rw "Loop UART0 to UART1";
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SPI0_LOOP_SPI1 1 rw "Loop SPI0 to SPI1";
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};
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register MIO_MST_TRI0 addr(base, 0x80C) "MIO pin tri-state enables, 31:0" {
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PIN_31_TRI 1 rw "Master tri-state for pin 31";
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PIN_30_TRI 1 rw "Master tri-state for pin 30";
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PIN_29_TRI 1 rw "Master tri-state for pin 29";
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PIN_28_TRI 1 rw "Master tri-state for pin 28";
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PIN_27_TRI 1 rw "Master tri-state for pin 27";
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PIN_26_TRI 1 rw "Master tri-state for pin 26";
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PIN_25_TRI 1 rw "Master tri-state for pin 25";
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PIN_24_TRI 1 rw "Master tri-state for pin 24";
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PIN_23_TRI 1 rw "Master tri-state for pin 23";
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PIN_22_TRI 1 rw "Master tri-state for pin 22";
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PIN_21_TRI 1 rw "Master tri-state for pin 21";
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PIN_20_TRI 1 rw "Master tri-state for pin 20";
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PIN_19_TRI 1 rw "Master tri-state for pin 19";
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PIN_18_TRI 1 rw "Master tri-state for pin 18";
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PIN_17_TRI 1 rw "Master tri-state for pin 17";
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PIN_16_TRI 1 rw "Master tri-state for pin 16";
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PIN_15_TRI 1 rw "Master tri-state for pin 15";
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PIN_14_TRI 1 rw "Master tri-state for pin 14";
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PIN_13_TRI 1 rw "Master tri-state for pin 13";
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PIN_12_TRI 1 rw "Master tri-state for pin 12";
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PIN_11_TRI 1 rw "Master tri-state for pin 11";
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PIN_10_TRI 1 rw "Master tri-state for pin 10";
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PIN_09_TRI 1 rw "Master tri-state for pin 09";
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PIN_08_TRI 1 rw "Master tri-state for pin 08";
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PIN_07_TRI 1 rw "Master tri-state for pin 07";
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PIN_06_TRI 1 rw "Master tri-state for pin 06";
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PIN_05_TRI 1 rw "Master tri-state for pin 05";
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PIN_04_TRI 1 rw "Master tri-state for pin 04";
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PIN_03_TRI 1 rw "Master tri-state for pin 03";
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PIN_02_TRI 1 rw "Master tri-state for pin 02";
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PIN_01_TRI 1 rw "Master tri-state for pin 01";
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PIN_00_TRI 1 rw "Master tri-state for pin 00";
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};
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register MIO_MST_TRI1 addr(base, 0x810) "MIO pin tri-state enables, 53:32" {
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_ 10;
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PIN_53_TRI 1 rw "Master tri-state for pin 53";
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PIN_52_TRI 1 rw "Master tri-state for pin 52";
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PIN_51_TRI 1 rw "Master tri-state for pin 51";
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PIN_50_TRI 1 rw "Master tri-state for pin 50";
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PIN_49_TRI 1 rw "Master tri-state for pin 49";
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PIN_48_TRI 1 rw "Master tri-state for pin 48";
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PIN_47_TRI 1 rw "Master tri-state for pin 47";
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PIN_46_TRI 1 rw "Master tri-state for pin 46";
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PIN_45_TRI 1 rw "Master tri-state for pin 45";
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PIN_44_TRI 1 rw "Master tri-state for pin 44";
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PIN_43_TRI 1 rw "Master tri-state for pin 43";
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PIN_42_TRI 1 rw "Master tri-state for pin 42";
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PIN_41_TRI 1 rw "Master tri-state for pin 41";
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PIN_40_TRI 1 rw "Master tri-state for pin 40";
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PIN_39_TRI 1 rw "Master tri-state for pin 39";
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PIN_38_TRI 1 rw "Master tri-state for pin 38";
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PIN_37_TRI 1 rw "Master tri-state for pin 37";
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PIN_36_TRI 1 rw "Master tri-state for pin 36";
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PIN_35_TRI 1 rw "Master tri-state for pin 35";
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PIN_34_TRI 1 rw "Master tri-state for pin 34";
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PIN_33_TRI 1 rw "Master tri-state for pin 33";
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PIN_32_TRI 1 rw "Master tri-state for pin 32";
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};
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};
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