121 lines
4.8 KiB
Plaintext
121 lines
4.8 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_cortexm3_wkup.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_cortexm3_wkup msbfirst ( addr base ) "" {
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register cortexm3_ctrl_reg addr(base, 0x0) "The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." {
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_ 15 mbz;
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int_cortex_2 1 rw "Interrupt to ARM Cortex-M3 CPU2";
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_ 15 mbz;
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int_cortex_1 1 rw "Interrupt to ARM Cortex-M3 CPU1";
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};
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constants standbymode_status width(2) "" {
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STANDBYMODE_1 = 1 "No-standby mode";
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STANDBYMODE_2 = 2 "Smart-standby mode";
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STANDBYMODE_3 = 3 "Smart-standby wakeup mode - normal mode to be used";
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};
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register standby_core_sysconfig addr(base, 0x4) "Standby protocol" {
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_ 30 mbz;
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standbymode 2 rw type(standbymode_status) "0x0: Force-standby mode";
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};
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constants idlemode_status width(2) "" {
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IDLEMODE_1 = 1 "No-idle mode";
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IDLEMODE_2 = 2 "Smart-idle mode";
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IDLEMODE_3 = 3 "Smart-idle wakeup mode - normal mode to be used";
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};
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register idle_core_sysconfig addr(base, 0x8) "Idle protocol" {
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_ 30 mbz;
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idlemode 2 rw type(idlemode_status) "0x0: Force-idle mode";
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};
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register wugen_mevt0 addr(base, 0xC) "This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." {
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mirq31 1 rw "Interrupt Mask bit 31";
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_ 1 mbz;
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mirq29 1 rw "Interrupt Mask bit 29";
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mirq28 1 rw "Interrupt Mask bit 28";
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mirq27 1 rw "Interrupt Mask bit 27";
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mirq26 1 rw "Interrupt Mask bit 26";
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mirq25 1 rw "Interrupt Mask bit 25";
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mirq24 1 rw "Interrupt Mask bit 24";
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mirq23 1 rw "Interrupt Mask bit 23";
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mirq22 1 rw "Interrupt Mask bit 22";
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mirq21 1 rw "Interrupt Mask bit 21";
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mirq20 1 rw "Interrupt Mask bit 20";
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mirq19 1 rw "Interrupt Mask bit 19";
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mirq18 1 rw "Interrupt Mask bit 18";
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mirq17 1 rw "Interrupt Mask bit 17";
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mirq16 1 rw "Interrupt Mask bit 16";
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mirq15 1 rw "Interrupt Mask bit 15";
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mirq14 1 rw "Interrupt Mask bit 14";
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mirq13 1 rw "Interrupt Mask bit 13";
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mirq12 1 rw "Interrupt Mask bit 12";
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mirq11 1 rw "Interrupt Mask bit 11";
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mirq10 1 rw "Interrupt Mask bit 10";
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mirq9 1 rw "Interrupt Mask bit 9";
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mirq8 1 rw "Interrupt Mask bit 8";
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mirq7 1 rw "Interrupt Mask bit 7";
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_ 7 mbz;
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};
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register wugen_mevt1 addr(base, 0x10) "This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." {
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mirq63 1 rw "Interrupt Mask bit 63";
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mirq62 1 rw "Interrupt Mask bit 62";
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mirq61 1 rw "Interrupt Mask bit 61";
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mirq60 1 rw "Interrupt Mask bit 60";
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mirq59 1 rw "Interrupt Mask bit 59";
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mirq58 1 rw "Interrupt Mask bit 58";
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mirq57 1 rw "Interrupt Mask bit 57";
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mirq56 1 rw "Interrupt Mask bit 56";
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_ 1 mbz;
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mirq54 1 rw "Interrupt Mask bit 54";
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mirq53 1 rw "Interrupt Mask bit 53";
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mirq52 1 rw "Interrupt Mask bit 52";
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mirq51 1 rw "Interrupt Mask bit 51";
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mirq50 1 rw "Interrupt Mask bit 50";
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_ 1 mbz;
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mirq48 1 rw "Interrupt Mask bit 48";
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mirq47 1 rw "Interrupt Mask bit 47";
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mirq46 1 rw "Interrupt Mask bit 46";
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_ 3 mbz;
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mirq42 1 rw "Interrupt Mask bit 42";
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mirq41 1 rw "Interrupt Mask bit 41";
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mirq40 1 rw "Interrupt Mask bit 40";
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mirq39 1 rw "Interrupt Mask bit 39";
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mirq38 1 rw "Interrupt Mask bit 38";
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mirq37 1 rw "Interrupt Mask bit 37";
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mirq36 1 rw "Interrupt Mask bit 36";
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mirq35 1 rw "Interrupt Mask bit 35";
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mirq34 1 rw "Interrupt Mask bit 34";
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mirq33 1 rw "Interrupt Mask bit 33";
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_ 1 mbz;
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};
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}; |