127 lines
6.5 KiB
Plaintext
127 lines
6.5 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_emu_cm.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_emu_cm msbfirst ( addr base ) "" {
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constants clkactivity_core_dpll_emu_clk_status width(1) "" {
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CLKACTIVITY_CORE_DPLL_EMU_CLK_0_r = 0 "Corresponding clock is definitely gated";
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CLKACTIVITY_CORE_DPLL_EMU_CLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
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};
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constants clktrctrl_status width(2) "" {
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CLKTRCTRL_0_r = 0 "Reserved";
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CLKTRCTRL_1_r = 1 "Reserved";
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CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
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CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
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};
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register cm_emu_clkstctrl addr(base, 0x0) "This register enables the EMU domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain. [warm reset insensitive]" {
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_ 22 mbz;
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clkactivity_core_dpll_emu_clk 1 ro type(clkactivity_core_dpll_emu_clk_status) "This field indicates the state of the CORE_DPLL_EMU_CLK clock in the domain.";
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clkactivity_emu_sys_clk 1 ro type(clkactivity_core_dpll_emu_clk_status) "This field indicates the state of the EMU_SYS_CLK clock in the domain.";
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_ 6 mbz;
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clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the EMU clock domain.";
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};
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constants l3_2_dyndep_status width(1) "" {
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L3_2_DYNDEP_1_r = 1 "Dependency is enabled";
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};
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register cm_emu_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from EMU domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." {
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_ 4 mbz;
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windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register.";
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_ 17 mbz;
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l3_2_dyndep 1 ro type(l3_2_dyndep_status) "Dynamic dependency towards L3_2 clock domain";
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_ 6 mbz;
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};
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constants clksel_pmd_stm_clk_status width(3) "" {
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CLKSEL_PMD_STM_CLK_0_r = 0 "Reserved";
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CLKSEL_PMD_STM_CLK_1 = 1 "STM_CLK is the selected STM source clock divided by 1";
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CLKSEL_PMD_STM_CLK_2 = 2 "STM_CLK is the selected STM source clock divided by 2";
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CLKSEL_PMD_STM_CLK_3_r = 3 "Reserved";
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CLKSEL_PMD_STM_CLK_4 = 4 "STM_CLK is the selected STM source clock divided by 4";
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CLKSEL_PMD_STM_CLK_5_r = 5 "Reserved";
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CLKSEL_PMD_STM_CLK_6_r = 6 "Reserved";
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CLKSEL_PMD_STM_CLK_7_r = 7 "Reserved";
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};
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constants clksel_pmd_trace_clk_status width(3) "" {
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CLKSEL_PMD_TRACE_CLK_0_r = 0 "Reserved";
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CLKSEL_PMD_TRACE_CLK_1 = 1 "TRACE_CLK is the selected TRACE source clock divided by 1";
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CLKSEL_PMD_TRACE_CLK_2 = 2 "TRACE_CLK is the selected TRACE source clock divided by 2";
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CLKSEL_PMD_TRACE_CLK_3_r = 3 "Reserved";
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CLKSEL_PMD_TRACE_CLK_4 = 4 "TRACE_CLK is the selected TRACE source clock divided by 4";
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CLKSEL_PMD_TRACE_CLK_5_r = 5 "Reserved";
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CLKSEL_PMD_TRACE_CLK_6_r = 6 "Reserved";
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CLKSEL_PMD_TRACE_CLK_7_r = 7 "Reserved";
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};
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constants pmd_trace_mux_ctrl_status width(2) "" {
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PMD_TRACE_MUX_CTRL_0 = 0 "TRACE source clock is SYS_CLK";
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PMD_TRACE_MUX_CTRL_1 = 1 "TRACE source clock is CORE_DPLL_EMU_CLK";
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PMD_TRACE_MUX_CTRL_2_r = 2 "Reserved";
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PMD_TRACE_MUX_CTRL_3_r = 3 "Reserved";
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};
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constants pmd_stm_mux_ctrl_status width(2) "" {
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PMD_STM_MUX_CTRL_0 = 0 "STM source clock is SYS_CLK";
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PMD_STM_MUX_CTRL_1 = 1 "STM source clock is CORE_DPLL_EMU_CLK";
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PMD_STM_MUX_CTRL_2_r = 2 "Reserved";
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PMD_STM_MUX_CTRL_3_r = 3 "Reserved";
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};
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constants stbyst_status width(1) "" {
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STBYST_0_r = 0 "Module is functional (not in standby)";
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STBYST_1_r = 1 "Module is in standby";
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};
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constants idlest_status width(2) "" {
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IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
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IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
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IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
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IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
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};
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constants modulemode_status width(2) "" {
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MODULEMODE_1_r = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state.";
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};
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register cm_emu_debugss_clkctrl addr(base, 0x20) "This register manages the DEBUGSS clocks. [warm reset insensitive]" {
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_ 2 mbz;
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clksel_pmd_stm_clk 3 rw type(clksel_pmd_stm_clk_status) "Selection of STM clock division";
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clksel_pmd_trace_clk 3 rw type(clksel_pmd_trace_clk_status) "Selection of TRACE clock division";
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pmd_trace_mux_ctrl 2 rw type(pmd_trace_mux_ctrl_status) "Selection of TRACE source clock";
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pmd_stm_mux_ctrl 2 rw type(pmd_stm_mux_ctrl_status) "Selection of STM source clock";
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_ 1 mbz;
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stbyst 1 ro type(stbyst_status) "Module standby status";
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idlest 2 ro type(idlest_status) "Module idle status";
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_ 14 mbz;
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modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed.";
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};
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}; |