104 lines
2.8 KiB
Plaintext
104 lines
2.8 KiB
Plaintext
/*
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* Copyright (c) 2014 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/*
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* knc_sbox.dev
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*
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* description: intel e1000 family gigabit ethernet nics
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*/
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device xeon_phi_gbox_gbox lsbfirst ( addr base ) "Intel Xeon Phi (Knights Corner) GBOX Registers" {
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register pm_state rw addr(base, 0x0060) "Power Management Status for FBOX" {
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statech0 4 "State of channel 0";
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statech1 4 "State of channel 1";
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_ 24 "rsvd";
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};
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register mca_status_lo rw addr(base, 0x0064) "desc" {
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};
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register mca_addr_lo rw addr(base, 0x006C) "desc" {
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};
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register mca_misc rw addr(base, 0x0074) "desc" {
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};
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register pm_configuration rw addr(base, 0x0098) "desc" {
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pm_enable 1 "Powermanagement enabled";
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m1_enable 1 "M1 enabled";
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m2_enable 1 "M2 enabled";
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m3_enable 1 "M3 enabled";
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cke_enable 1 "CKE enabled";
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pm_mod 1 "Behaviour of PM Logic";
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fboxdfxclkgateen 1 "DFX on demand clock gating";
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fboxclkgateen 1 "On demand clock gating enabled";
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m2_timerenable 1 "M2 timer enabled";
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m3_timerenable 1 "M3 timer enabled";
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fboxarbiterlock 1 "Lock FBOX arbiter when idle";
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_ 21 "rsvd";
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};
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register pm_control rw addr(base, 0x009C) "Powemanagement Control for FBOX" {
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enablech0 1 "Channel 0 enabled";
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enablech1 1 "Channel 1 enabled";
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enablech0valid 1 "Channel 0 enable valid";
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enablech1valid 1 "Channel 1 enable valid";
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nextstatech0 4 "Next state for channel 0";
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nextstatech1 4 "Next state for channel 1";
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forcem2 1 "Force M2 state";
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forcem3 1 "Force M3 state";
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exitmemprsv 1 "Signal config done";
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forcewakeup 1 "Wakeup all";
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_ 16 "rsvd";
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};
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register pm_counters rw addr(base, 0x00C0) "Powermanagement control register for FBOX Counters" {
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idlesignaldelay 8 "Idle signal delay (cycles)";
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idlecondition 2 "PM status to idle signal link";
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earlyidlesignaldelay 8 "Early idle signal delay";
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_ 14 "rsvd";
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};
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register pm_config_valid rw addr(base, 0x01B4) "Trigger to latch FBOX power management" {
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_ 32 "Unused";
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};
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register uc_rw_addr rw addr(base, 0x0700) "desc" {
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};
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register uc_start_ip_addr rw addr(base, 0x0720) "desc" {
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};
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register uc_cmd_start rw addr(base, 0x0724) "desc" {
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};
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register afg_master_delay_out rw addr(base, 0x1138) "desc" {
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};
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register afg_master_delay_in rw addr(base, 0x113C) "desc" {
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};
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register afg_master_mclk_range rw addr(base, 0x1140) "desc" {
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};
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};
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