207 lines
10 KiB
Plaintext
207 lines
10 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_dmic_dsp.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_dmic_dsp msbfirst ( addr base ) "" {
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register dmic_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) used by software to track features, bugs, and compatibility" type(uint32);
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constants sidlemode_status width(2) "" {
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SIDLEMODE_0 = 0 "Force-idle. IDLE request is acknowledged unconditionally and immediately.";
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SIDLEMODE_1 = 1 "No-idle. IDLE request is never acknowledged.";
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SIDLEMODE_2 = 2 "Smart-idle. The acknowledgment to an IDLE request is given based on the internal activity.";
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SIDLEMODE_3 = 3 "Smart-idle wakeup capable mode";
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};
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constants freemu_status width(1) "" {
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FREEMU_0 = 0 "IP module is sensitive to emulation suspend.";
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FREEMU_1 = 1 "IP module is not sensitive to emulation suspend.";
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};
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constants softreset_status width(1) "" {
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SOFTRESET_0_w = 0 "No action";
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SOFTRESET_0_r = 0 "Reset done, no pending action";
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SOFTRESET_1_r = 1 "Reset (software or other) ongoing";
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SOFTRESET_1_w = 1 "Initiate software reset.";
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};
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register dmic_sysconfig addr(base, 0x10) "This register allows controlling various parameters of the DMIC interface." {
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_ 28 mbz;
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sidlemode 2 rw type(sidlemode_status) "Configuration of the local target state management (idlereq/idleack control)";
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freemu 1 rw type(freemu_status) "Sensitivity to emulation (debug) suspend input signal";
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softreset 1 rw type(softreset_status) "Module software reset. The bit is automatically reset by the hardware. It has same effect as the main hardware reset.";
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};
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constants dmic_irq_empty_status width(1) "" {
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DMIC_IRQ_EMPTY_0_r = 0 "No event pending";
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DMIC_IRQ_EMPTY_0_w = 0 "No action";
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DMIC_IRQ_EMPTY_1_w = 1 "Set";
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DMIC_IRQ_EMPTY_1_r = 1 "IRQ event pending";
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};
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register dmic_irqstatus_raw addr(base, 0x24) "Component (that is, main) interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." {
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_ 28 mbz;
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dmic_irq_empty 1 rw type(dmic_irq_empty_status) "";
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dmic_irq_alst_full 1 rw type(dmic_irq_empty_status) "";
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dmic_irq_full 1 rw type(dmic_irq_empty_status) "";
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dmic_irq 1 rw type(dmic_irq_empty_status) "";
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};
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constants dmic_irq_empty_status1 width(1) "" {
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DMIC_IRQ_EMPTY_0_r_1 = 0 "No event pending";
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DMIC_IRQ_EMPTY_0_w_1 = 0 "No action";
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DMIC_IRQ_EMPTY_1_w_1 = 1 "Clear pending event, if any";
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DMIC_IRQ_EMPTY_1_r_1 = 1 "IRQ event pending";
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};
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constants dmic_irq_full_status width(1) "" {
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DMIC_IRQ_FULL_0_r_1 = 0 "No event pending";
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DMIC_IRQ_FULL_0_w_1 = 0 "No action";
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DMIC_IRQ_FULL_1_w_1 = 1 "Clear pending event, if any.";
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DMIC_IRQ_FULL_1_r_1 = 1 "IRQ event pending";
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};
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register dmic_irqstatus addr(base, 0x28) "Component (that is, main) interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." {
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_ 28 mbz;
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dmic_irq_empty 1 rw type(dmic_irq_empty_status1) "";
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dmic_irq_alst_full 1 rw1c type(dmic_irq_empty_status1) "This interrupt status is set when only one FIFO space is still available.";
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dmic_irq_full 1 rw1c type(dmic_irq_full_status) "This interrupt status is set when FIFO is full and a new write access has been performed by filter.";
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dmic_irq 1 rw1c type(dmic_irq_full_status) "This interrupt status is set when FIFO threshold value defined inDMIC_FIFO_CTRL is reached.";
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};
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constants dmic_irq_empty_mask_status width(1) "" {
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DMIC_IRQ_EMPTY_MASK_0_r = 0 "Interrupt disabled";
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DMIC_IRQ_EMPTY_MASK_0_w = 0 "No action";
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DMIC_IRQ_EMPTY_MASK_1_w = 1 "Enable interrupt";
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DMIC_IRQ_EMPTY_MASK_1_r = 1 "";
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};
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constants dmic_irq_alst_full_mask_status width(1) "" {
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DMIC_IRQ_ALST_FULL_MASK_0_r = 0 "Interrupt disabled";
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DMIC_IRQ_ALST_FULL_MASK_0_w = 0 "No action";
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DMIC_IRQ_ALST_FULL_MASK_1_w = 1 "Enable interrupt";
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DMIC_IRQ_ALST_FULL_MASK_1_r = 1 "Interrupt enabled";
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};
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register dmic_irqenable_set addr(base, 0x2C) "Component (that is, main) interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." {
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_ 28 mbz;
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dmic_irq_empty_mask 1 rw type(dmic_irq_empty_mask_status) "";
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dmic_irq_alst_full_mask 1 rw type(dmic_irq_alst_full_mask_status) "";
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dmic_irq_full_mask 1 rw type(dmic_irq_alst_full_mask_status) "";
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dmic_irq_mask 1 rw type(dmic_irq_alst_full_mask_status) "";
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};
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constants dmic_irq_empty_mask_status1 width(1) "" {
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DMIC_IRQ_EMPTY_MASK_0_r_1 = 0 "Interrupt disabled";
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DMIC_IRQ_EMPTY_MASK_0_w_1 = 0 "No action";
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DMIC_IRQ_EMPTY_MASK_1_w_1 = 1 "Disable interrupt";
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DMIC_IRQ_EMPTY_MASK_1_r_1 = 1 "Interrupt enabled";
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};
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register dmic_irqenable_clr addr(base, 0x30) "Component (that is, main) interrupt request enable Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." {
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_ 28 mbz;
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dmic_irq_empty_mask 1 rw1c type(dmic_irq_empty_mask_status1) "";
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dmic_irq_alst_full_mask 1 rw1c type(dmic_irq_empty_mask_status1) "";
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dmic_irq_full_mask 1 rw1c type(dmic_irq_empty_mask_status1) "";
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dmic_irq_mask 1 rw1c type(dmic_irq_empty_mask_status1) "";
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};
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register dmic_irqwakeen addr(base, 0x34) "This register allows to enable the wake-up capability on interrupt event." {
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_ 31 mbz;
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irq_wakeup_en 1 rw "Write 1 to allow wake-up by IRQ source (register threshold value reached).";
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};
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register dmic_dmaenable_set addr(base, 0x38) "Component DMA enable (1 bit per DMA-capable channel)/Write 1 to set (enable DMA). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." {
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_ 31 mbz;
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dma_enable 1 rw type(dmic_irq_alst_full_mask_status) "Write 1 to set (enable DMA request)";
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};
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register dmic_dmaenable_clr addr(base, 0x3C) "Component DMA enable (1 bit per DMA-capable channel)/Write 1 to clear (disable DMA). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." {
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_ 31 mbz;
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dma_enable 1 rw1c type(dmic_irq_empty_mask_status1) "Write 1 to clear (disable DMA request)";
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};
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register dmic_dmawakeen addr(base, 0x40) "This register allows to enable the wake-up capability on DMA request event." {
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_ 31 mbz;
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dma_wakeup_en 1 rw "Write 1 to allow wakeup by DMA source (register threshold value reached).";
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};
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constants dmic_polar3_status width(1) "" {
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DMIC_POLAR3_0 = 0 "When 0, the left data is generated in the external microphone 3 on abe_dmic_clk3 low level.";
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DMIC_POLAR3_1 = 1 "When 1, the left data is generated in the external microphone 3 on abe_dmic_clk3 high level.";
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};
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register dmic_ctrl addr(base, 0x44) "This register configures the various parameters of the DMIC module." {
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_ 21 mbz;
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sw_dmic_rst 1 rw "Software reset of the DMIC path. When 1, the DMIC path is reset. Clearing the reset is done by writing 0 to the register.";
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dmic_clk_div 3 rw "Select the DMIC output clock frequency. See for details.";
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dmic_polar3 1 rw type(dmic_polar3_status) "";
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dmic_polar2 1 rw type(dmic_polar3_status) "";
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dmic_polar1 1 rw type(dmic_polar3_status) "";
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dmicoutformat 1 rw "When 0, the data going out from the FIFO are left shifted from 8 bits. When 1, the data going are signed extended on 32 bits";
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dmic_up3_en 1 rw "When 1, uplink path 3 is powered up.";
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dmic_up2_en 1 rw "When 1, uplink path 2 is powered up.";
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dmic_up1_en 1 rw "When 1, uplink path 1 is powered up.";
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};
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register dmic_data_reg ro addr(base, 0x48) "DMIC FIFO data" type(uint32);
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register dmic_fifo_ctrl addr(base, 0x4C) "This register sets the FIFO threshold for the data-ready event." {
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_ 28 mbz;
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dmic_tresh 4 rw "Uplink FIFO threshold";
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};
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register dmic_fifo_dmic1r_data addr(base, 0x50) "Data of the first FIFO DMIC right channel" {
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_ 8 mbz;
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fifo_dmic1r_dat 24 ro "Data of the right FIFO DMIC path 1";
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};
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register dmic_fifo_dmic1l_data addr(base, 0x54) "Data of the first FIFO DMIC left channel" {
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_ 8 mbz;
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fifo_dmic1r_dat 24 ro "Data of the left FIFO DMIC path 1";
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};
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register dmic_fifo_dmic2r_data addr(base, 0x58) "Data of the second FIFO DMIC right channel" {
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_ 8 mbz;
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fifo_dmic2r_dat 24 ro "Data of the right FIFO DMIC path 2";
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};
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register dmic_fifo_dmic2l_data addr(base, 0x5C) "Data of the second FIFO DMIC left channel" {
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_ 8 mbz;
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fifo_dmic2l_dat 24 ro "Data of the left FIFO DMIC path 2";
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};
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register dmic_fifo_dmic3r_data addr(base, 0x60) "Data of the third FIFO DMIC right channel" {
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_ 8 mbz;
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fifo_dmic3r_dat 24 ro "Data of the right FIFO DMIC path 3";
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};
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register dmic_fifo_dmic3l_data addr(base, 0x64) "Data of the third FIFO DMIC left channel" {
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_ 8 mbz;
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fifo_dmic3r_dat 24 ro "Data of the left FIFO DMIC path 3";
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};
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}; |