616 lines
18 KiB
C
616 lines
18 KiB
C
/**
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* \file
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* \brief IMX8x uSDHC Digital Host Controller Driver
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*/
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/*
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* Copyright (c) 2007, 2008, 2010, 2011, 2012,2020 ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* In U-boot drivers/mmc/fsl_esdhc.c is talking to the
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* same controller. This driver follows the i.MX 8DualXPlus/8QuadXPlus
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* Applications Processor Reference Manual register definitions and
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* descriptions, except for the vendor specific register, which is
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* used differently in U-Boot, and that seems the correct way.
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*
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* Card detection on Toradex boards:
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* ===========
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* The Toradex boards dont break out the SDHC card detection pin, instead
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* a GPIO (Bank4, Pin22) has to be checked for card present. Currently,
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* this driver simply assumes a card is present.
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*/
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#include <aos/aos.h>
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#include <drivers/sdhc.h>
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#include <aos/deferred.h>
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#include <dev/imx8x/sdhc_dev.h>
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//#define DEBUG_ON
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#if defined(DEBUG_ON) || defined(GLOBAL_DEBUG)
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# define DEBUG(x...) debug_printf(x)
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#else
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# define DEBUG(x...) ((void)0)
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#endif
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_SEND_TUNING_BLOCK 19
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#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
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#define MMC_CMD_SET_BLOCK_COUNT 23
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_ERASE_GROUP_START 35
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#define MMC_CMD_ERASE_GROUP_END 36
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#define MMC_CMD_ERASE 38
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#define MMC_CMD_APP_CMD 55
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#define MMC_CMD_SPI_READ_OCR 58
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#define MMC_CMD_SPI_CRC_ON_OFF 59
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#define MMC_CMD_RES_MAN 62
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_SWITCH_UHS18V 11
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_APP_SD_STATUS 13
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#define SD_CMD_ERASE_WR_BLK_START 32
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#define SD_CMD_ERASE_WR_BLK_END 33
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
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MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define OCR_BUSY 0x80000000
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#define OCR_HCS 0x40000000
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#define OCR_S18R 0x1000000
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struct sdhc_s {
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sdhc_t dev;
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uintptr_t vbase;
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uint32_t caps;
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// Card properties
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uint8_t cid[16];
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uint32_t csd[4];
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uint16_t rca;
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int high_capacity;
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uint64_t read_bl_len;
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uint64_t write_bl_len ;
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uint64_t capacity_user;
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};
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struct cmd {
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uint16_t cmdidx;
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unsigned int cmdarg;
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unsigned int resp_type;
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unsigned int response[4]; // The response of the command
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genpaddr_t dma_base; // If a data transfer is necessary, use this
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// physical base address for read/write.
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};
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#define dump(sd) do {\
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char buf[1024];\
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sdhc_int_status_pr(buf, 1024, &sd->dev);\
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DEBUG("%s:%d: %s\n", __FUNCTION__, __LINE__, buf);\
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} while(0)
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static errval_t software_reset(struct sdhc_s *sd){
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sdhc_sys_ctrl_rsta_wrf(&sd->dev, 1);
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uint64_t timeout = 1000;
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while(sdhc_sys_ctrl_rsta_rdf(&sd->dev)){
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if(--timeout == 0){
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DEBUG("Reset TIMEOUT!\n");
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return SDHC_ERR_RESET_TIMEOUT;
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}
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barrelfish_usleep(1000);
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}
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// Set sensible defaults
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sdhc_mmc_boot_rawwr(&sd->dev, 0);
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sdhc_mix_ctrl_rawwr(&sd->dev, 0);
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sdhc_clk_tune_ctrl_status_rawwr(&sd->dev, 0);
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sdhc_dll_rawwr(&sd->dev, 0);
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sdhc_vend_spec_t vs = 0;
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vs = sdhc_vend_spec_ipgen_insert(vs, 1);
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vs = sdhc_vend_spec_hcken_insert(vs, 1);
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sdhc_vend_spec_wr(&sd->dev, vs);
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DEBUG("Reset complete!\n");
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sd->caps = sdhc_host_ctrl_cap_rawrd(&sd->dev);
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//Setting clock to initial 40mhz
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sdhc_vend_spec_cken_wrf(&sd->dev, 0);
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sdhc_sys_ctrl_t s = 0;
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s = sdhc_sys_ctrl_dvs_insert(s, 0xf);
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s = sdhc_sys_ctrl_sdclkfs_insert(s, 0x10);
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s = sdhc_sys_ctrl_dtocv_insert(s, 0xc);
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sdhc_sys_ctrl_wr(&sd->dev, s);
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barrelfish_usleep(10000);
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vs = sdhc_vend_spec_rd(&sd->dev);
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vs = sdhc_vend_spec_peren_insert(vs, 1);
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vs = sdhc_vend_spec_cken_insert(vs, 1);
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sdhc_vend_spec_wr(&sd->dev, vs);
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sdhc_prot_ctrl_dtw_wrf(&sd->dev, 0); // Bus width: 1-bit mode
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sdhc_prot_ctrl_emode_wrf(&sd->dev, 0x2); // Little endian mode
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sdhc_sys_ctrl_dtocv_wrf(&sd->dev, 0xe);
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return SYS_ERR_OK;
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}
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static sdhc_cmd_xfr_typ_t xfr_typ_for_cmd(struct cmd *cmd){
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sdhc_cmd_xfr_typ_t c = 0;
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if(cmd->cmdidx == MMC_CMD_READ_SINGLE_BLOCK ||
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cmd->cmdidx == MMC_CMD_WRITE_SINGLE_BLOCK)
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{
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c = sdhc_cmd_xfr_typ_dpsel_insert(c, 1);
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}
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c = sdhc_cmd_xfr_typ_cmdinx_insert(c, cmd->cmdidx);
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if (cmd->resp_type & MMC_RSP_CRC)
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c = sdhc_cmd_xfr_typ_cccen_insert(c, 1);
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if (cmd->resp_type & MMC_RSP_OPCODE)
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c = sdhc_cmd_xfr_typ_cicen_insert(c, 1);
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c = sdhc_cmd_xfr_typ_rsptyp_insert(c, sdhc_rsp_tp_none);
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if (cmd->resp_type & MMC_RSP_136)
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c = sdhc_cmd_xfr_typ_rsptyp_insert(c, sdhc_rsp_tp_136);
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else if (cmd->resp_type & MMC_RSP_BUSY)
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c = sdhc_cmd_xfr_typ_rsptyp_insert(c, sdhc_rsp_tp_48cb);
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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c = sdhc_cmd_xfr_typ_rsptyp_insert(c, sdhc_rsp_tp_48);
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c = sdhc_cmd_xfr_typ_cmdtyp_insert(c, sdhc_cmd_tp_norm);
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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c = sdhc_cmd_xfr_typ_cmdtyp_insert(c, sdhc_cmd_tp_abrt);
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return c;
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}
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static errval_t sdhc_send_cmd(struct sdhc_s * sd, struct cmd * cmd) {
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DEBUG("sdhc_send_cmd: cmdidx=%d,cmdarg=%d\n", cmd->cmdidx, cmd->cmdarg);
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uint32_t mask; // TODO: in some cases we don't need to wait for all
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if(cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) {
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mask = 1;
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} else {
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mask = 3;
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}
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while(sdhc_pres_state_rawrd(&sd->dev) & mask){
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DEBUG("Card busy!\n");
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}
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DEBUG("Card ready (data & cmd inhibit are clear)!\n");
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// NOTE rueegges: This wait does not seem to be necessary
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// barrelfish_usleep(10000);
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// Clear interrupts
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sdhc_int_status_rawwr(&sd->dev, ~0x0);
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// Mask interrupts.
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sdhc_int_signal_en_rawwr(&sd->dev, 0);
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// CMD argument
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sdhc_cmd_arg_wr(&sd->dev, cmd->cmdarg);
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// Mixer controler
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int is_read = cmd->cmdidx == MMC_CMD_READ_SINGLE_BLOCK;
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int is_write = cmd->cmdidx == MMC_CMD_WRITE_SINGLE_BLOCK;
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sdhc_mix_ctrl_wr(&sd->dev, 0);
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sdhc_mix_ctrl_dmaen_wrf(&sd->dev, is_read || is_write);
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sdhc_mix_ctrl_dtdsel_wrf(&sd->dev, is_read);
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if(is_read || is_write){
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// DMA address setup
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assert((cmd->dma_base >> 32) == 0);
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sdhc_vend_spec2_acmd23_argu2_en_wrf(&sd->dev, 0);
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sdhc_ds_addr_wr(&sd->dev, cmd->dma_base);
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//Set watermark
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sdhc_wtmk_lvl_rd_wml_wrf(&sd->dev, 16);
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sdhc_wtmk_lvl_wr_wml_wrf(&sd->dev, 16);
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}
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sdhc_cmd_xfr_typ_t c = xfr_typ_for_cmd(cmd);
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sdhc_cmd_xfr_typ_wr(&sd->dev, c);
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//DEBUG("%s:%d: Wait until irq_stat.tc || irq_stat.cc \n", __FUNCTION__, __LINE__);
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uint32_t tc = 0;
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uint32_t cc = 0;
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size_t i = 0;
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do {
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uint32_t ctoe = sdhc_int_status_ctoe_rdf(&sd->dev);
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uint32_t cce = sdhc_int_status_cce_rdf(&sd->dev);
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tc = sdhc_int_status_tc_rdf(&sd->dev);
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cc = sdhc_int_status_cc_rdf(&sd->dev);
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if (ctoe == 0x1 && cce == 0x1) {
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DEBUG("%s:%d: ctoe = 1 ccrc = 1: Conflict on cmd line.\n",
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__FUNCTION__, __LINE__);
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dump(sd);
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return SDHC_ERR_CMD_CONFLICT;
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}
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if (ctoe == 0x1 && cce == 0x0) {
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DEBUG("%s:%d: cto = 1 ccrc = 0: Abort.\n", __FUNCTION__, __LINE__);
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dump(sd);
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return SDHC_ERR_CMD_TIMEOUT;
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}
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if (i++ > 1000) {
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dump(sd);
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USER_PANIC("Command not Ackd?");
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}
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barrelfish_usleep(10);
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if(tc || cc) break;
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} while (true);
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DEBUG("Command complete!\n");
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if(cmd->resp_type & MMC_RSP_136){
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uint32_t r0 = sdhc_cmd_rsp0_rd(&sd->dev);
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uint32_t r1 = sdhc_cmd_rsp1_rd(&sd->dev);
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uint32_t r2 = sdhc_cmd_rsp2_rd(&sd->dev);
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uint32_t r3 = sdhc_cmd_rsp3_rd(&sd->dev);
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cmd->response[0] = (r3 << 8) | (r2 >> 24);
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cmd->response[1] = (r2 << 8) | (r1 >> 24);
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cmd->response[2] = (r1 << 8) | (r0 >> 24);
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cmd->response[3] = (r0 << 8);
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} else {
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cmd->response[0] = sdhc_cmd_rsp0_rd(&sd->dev);
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}
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return SYS_ERR_OK;
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}
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static errval_t sdhc_go_idle(struct sdhc_s *sd) {
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errval_t err;
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struct cmd init = {
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.cmdidx = MMC_CMD_GO_IDLE_STATE,
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.cmdarg = 0,
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.resp_type = MMC_RSP_NONE
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};
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err = sdhc_send_cmd(sd, &init);
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if(err_is_ok(err)){
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DEBUG("Successfully sent GO_IDLE transaction\n");
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}
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barrelfish_usleep(2000);
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return err;
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}
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static errval_t sdhc_send_if_cond(struct sdhc_s *sd) {
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errval_t err;
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uint32_t pattern = 0xde;
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struct cmd cmd = {
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.cmdidx = SD_CMD_SEND_IF_COND,
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.cmdarg = 0x100 | pattern, // Offer 3V voltage followed by pattern
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.resp_type = MMC_RSP_R7
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};
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err = sdhc_send_cmd(sd, &cmd);
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if(err_is_ok(err)){
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if(cmd.response[0] == (0x100 | pattern)){
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DEBUG("IF_COND: Success! Got (at least) SD Version 2\n");
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return SYS_ERR_OK;
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} else {
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DEBUG("IF_COND: Legacy cards not supported!\n");
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err = SDHC_ERR_CMD_TIMEOUT;
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}
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}
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return err;
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}
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/*
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* This function queries the card to determine operating voltage/standard
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* etc. It does not perform a card initialization.
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*/
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static errval_t sdhc_get_ocr(struct sdhc_s *sd){
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errval_t err;
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uint32_t ocr=0;
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while(1){
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struct cmd app_cmd = {
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.cmdidx = MMC_CMD_APP_CMD,
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.cmdarg = 0,
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.resp_type = MMC_RSP_R1
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};
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err = sdhc_send_cmd(sd, &app_cmd);
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if(err_is_fail(err)){
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DEBUG_ERR(err, "send app_cmd");
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return err;
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}
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struct cmd op_cond_cmd = {
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.cmdidx = SD_CMD_APP_SEND_OP_COND,
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.cmdarg = 0x40300000, // Have OCS and default voltages
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.resp_type = MMC_RSP_R3
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};
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err = sdhc_send_cmd(sd, &op_cond_cmd);
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if(err_is_fail(err)) {
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DEBUG_ERR(err, "send op_cond_cmd");
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return err;
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}
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if(op_cond_cmd.response[0] & OCR_BUSY) {
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ocr = op_cond_cmd.response[0];
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break;
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}
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barrelfish_usleep(10000);
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}
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DEBUG("Received OCR! ocr=0x%"PRIx32"\n", ocr);
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if((ocr & OCR_HCS) == OCR_HCS){
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DEBUG("High capacity card found!\n");
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sd->high_capacity = 1;
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} else {
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DEBUG("Non high capacity card. NOT TESTED\n");
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sd->high_capacity = 0;
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}
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sd->rca = 0;
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return SYS_ERR_OK;
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}
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/**
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* Here we perform the actual card initialization
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*/
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static errval_t sdhc_card_init(struct sdhc_s* sd){
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errval_t err;
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// Put card in identify mode
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struct cmd cid = {
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.cmdidx = MMC_CMD_ALL_SEND_CID,
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.resp_type = MMC_RSP_R2,
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.cmdarg = 0
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};
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err = sdhc_send_cmd(sd, &cid);
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if(err_is_fail(err)){
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DEBUG_ERR(err, "cid command");
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}
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memcpy(sd->cid, cid.response, 16);
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struct cmd send_addr = {
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.cmdidx = SD_CMD_SEND_RELATIVE_ADDR,
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.cmdarg = sd->rca << 16,
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.resp_type = MMC_RSP_R6
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};
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err = sdhc_send_cmd(sd, &send_addr);
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if(err_is_fail(err)){
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DEBUG_ERR(err, "send addr command");
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}
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sd->rca = send_addr.response[0] >> 16 & 0xffff;
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DEBUG("Determined RCA=0x%"PRIx16".\n", sd->rca);
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struct cmd send_csd = {
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.cmdidx = MMC_CMD_SEND_CSD,
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.resp_type = MMC_RSP_R2,
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.cmdarg = sd->rca << 16
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};
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err = sdhc_send_cmd(sd, &send_csd);
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if(err_is_fail(err)){
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DEBUG_ERR(err, "send csd command");
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}
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sd->csd[0] = send_csd.response[0];
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sd->csd[1] = send_csd.response[1];
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sd->csd[2] = send_csd.response[2];
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sd->csd[3] = send_csd.response[3];
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DEBUG("CSD: [0]=%"PRIx32", [1]=%"PRIx32", [2]=%"PRIx32", [3]=%"PRIx32"\n",
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sd->csd[0], sd->csd[1], sd->csd[2], sd->csd[3]);
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sd->read_bl_len = 1 << ((sd->csd[1]>>16) & 0xf);
|
|
DEBUG("SD read_bl_len: %"PRIx64"\n", sd->read_bl_len);
|
|
sd->write_bl_len = sd->read_bl_len;
|
|
|
|
if(sd->high_capacity) {
|
|
unsigned int csize, cmult;
|
|
csize = (sd->csd[1] & 0x3f) << 16 | (sd->csd[2] & 0xffff0000) >> 16;
|
|
cmult = 8;
|
|
sd->capacity_user = ((csize + 1) << (cmult + 2)) * sd->read_bl_len;
|
|
DEBUG("SD capacity: %"PRIx64"\n", sd->capacity_user);
|
|
}
|
|
|
|
// Select the card, this puts it into the "transfer" state
|
|
struct cmd select_card = {
|
|
.cmdidx = MMC_CMD_SELECT_CARD,
|
|
.resp_type = MMC_RSP_R1,
|
|
.cmdarg = sd->rca << 16
|
|
};
|
|
err = sdhc_send_cmd(sd, &select_card);
|
|
if(err_is_fail(err)) {
|
|
DEBUG_ERR(err, "select_card cmd");
|
|
return err;
|
|
}
|
|
|
|
return SYS_ERR_OK;
|
|
}
|
|
|
|
errval_t sdhc_read_block(struct sdhc_s* sd, int index, lpaddr_t dest)
|
|
{
|
|
errval_t err;
|
|
|
|
struct cmd set_blocklen = {
|
|
.cmdidx = MMC_CMD_SET_BLOCKLEN,
|
|
.cmdarg = SDHC_BLOCK_SIZE,
|
|
.resp_type = MMC_RSP_R1
|
|
};
|
|
err = sdhc_send_cmd(sd, &set_blocklen);
|
|
if(err_is_fail(err)){
|
|
DEBUG_ERR(err, "set_blocklen");
|
|
return err;
|
|
}
|
|
|
|
struct cmd read_block = {
|
|
.cmdidx = MMC_CMD_READ_SINGLE_BLOCK,
|
|
.cmdarg = index,
|
|
.resp_type = MMC_RSP_R1,
|
|
.dma_base = dest
|
|
|
|
};
|
|
err = sdhc_send_cmd(sd, &read_block);
|
|
if(err_is_fail(err)){
|
|
DEBUG_ERR(err, "read_block");
|
|
return err;
|
|
}
|
|
|
|
return SYS_ERR_OK;
|
|
}
|
|
|
|
errval_t sdhc_write_block(struct sdhc_s* sd, int index, lpaddr_t source){
|
|
errval_t err;
|
|
|
|
struct cmd set_blocklen = {
|
|
.cmdidx = MMC_CMD_SET_BLOCKLEN,
|
|
.cmdarg = SDHC_BLOCK_SIZE,
|
|
.resp_type = MMC_RSP_R1
|
|
};
|
|
err = sdhc_send_cmd(sd, &set_blocklen);
|
|
if(err_is_fail(err)){
|
|
DEBUG_ERR(err, "set_blocklen");
|
|
return err;
|
|
}
|
|
|
|
struct cmd write_block = {
|
|
.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK,
|
|
.cmdarg = index,
|
|
.resp_type = MMC_RSP_R1,
|
|
.dma_base = source
|
|
|
|
};
|
|
err = sdhc_send_cmd(sd, &write_block);
|
|
if(err_is_fail(err)){
|
|
DEBUG_ERR(err, "read_block");
|
|
return err;
|
|
}
|
|
|
|
return SYS_ERR_OK;
|
|
}
|
|
|
|
static errval_t card_init(struct sdhc_s * sd){
|
|
//Initialize and identify the card. Roughly following SDHC specification,
|
|
//3.6 Card Initialization and Identification.
|
|
errval_t err;
|
|
|
|
DEBUG("Sending go idle transaction...\n"); err = sdhc_go_idle(sd);
|
|
if(err_is_fail(err)) return err;
|
|
|
|
DEBUG("Sending if_cond transaction...\n");
|
|
err = sdhc_send_if_cond(sd);
|
|
if(err_is_fail(err)) return err;
|
|
|
|
DEBUG("Query OCR (CMD 55/41)...\n");
|
|
err = sdhc_get_ocr(sd);
|
|
if(err_is_fail(err)) return err;
|
|
|
|
DEBUG("Card initialization...\n");
|
|
err = sdhc_card_init(sd);
|
|
if(err_is_fail(err)) return err;
|
|
|
|
DEBUG("Card in transfer state!");
|
|
|
|
return SYS_ERR_OK;
|
|
}
|
|
|
|
errval_t sdhc_test(struct sdhc_s *sd, void* scratch, lpaddr_t scratch_p)
|
|
{
|
|
errval_t err;
|
|
|
|
// Write, read and verify some test data
|
|
char test_data[] = {0x01,0x02,0x03,0xff,0x0};
|
|
for(int i=0; test_data[i]; i++){
|
|
((char*)scratch)[i] = test_data[i];
|
|
}
|
|
|
|
err = sdhc_write_block(sd, SDHC_TEST_BLOCK, scratch_p);
|
|
if(err_is_fail(err)){
|
|
DEBUG_ERR(err, "write block");
|
|
return err;
|
|
}
|
|
|
|
memset(scratch, 0, 0x1000);
|
|
|
|
err = sdhc_read_block(sd, SDHC_TEST_BLOCK, scratch_p);
|
|
if(err_is_fail(err)){
|
|
DEBUG_ERR(err, "read block");
|
|
return err;
|
|
}
|
|
|
|
for(int i=0; test_data[i]; i++){
|
|
char c = ((char*)scratch)[i];
|
|
printf("Byte [%d] = %x\n", i, c);
|
|
if(c != test_data[i]) return SDHC_ERR_TEST_FAILED;
|
|
}
|
|
|
|
return SYS_ERR_OK;
|
|
}
|
|
|
|
errval_t sdhc_init(struct sdhc_s** sd_ret, void *base)
|
|
{
|
|
DEBUG("sdhc_init: enter\n");
|
|
errval_t err;
|
|
|
|
struct sdhc_s * sd = calloc(sizeof(struct sdhc_s), 1);
|
|
*sd_ret = sd;
|
|
|
|
sdhc_initialize(&sd->dev, base);
|
|
|
|
err = software_reset(sd);
|
|
if (err_is_fail(err)) {
|
|
DEBUG_ERR(err, "software reset failed");
|
|
return err;
|
|
}
|
|
DEBUG("reset done.\n");
|
|
|
|
err = card_init(sd);
|
|
if (err_is_fail(err)) {
|
|
DEBUG_ERR(err, "card init failed (No card present?)");
|
|
return err;
|
|
}
|
|
|
|
return SYS_ERR_OK;
|
|
}
|
|
|