110 lines
6.2 KiB
Plaintext
110 lines
6.2 KiB
Plaintext
/*
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* Copyright (c) 2013 ETH Zurich. All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
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* Attn: Systems Group.
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*/
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/*
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* omap44xx_dss_cm2.dev
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*
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* DESCRIPTION:
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*
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* NOTE: This file has been automatically generated based on the
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* XML files extracted from the TI RDT v1.0.0.4p Tool.
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* Download from here: http://www.ti.com/product/omap4460
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* This means that the file might not be optimal in terms of naming
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* conventions for constants and registers (duplicated
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* namespaces in register and device name etc.).
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* Also, because of the underlying structure from the original XML
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* it's possible that some constants appear multiple times (if they
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* have slightly different descriptions for example).
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*
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* You want to clean that up before using the files for the first time!
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*/
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device omap44xx_dss_cm2 msbfirst ( addr base ) "" {
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constants clkactivity_hdmi_phy_48m_fclk_status width(1) "" {
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CLKACTIVITY_HDMI_PHY_48M_FCLK_0_r = 0 "Corresponding clock is definitely gated";
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CLKACTIVITY_HDMI_PHY_48M_FCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
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};
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constants clktrctrl_status width(2) "" {
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CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
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CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
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CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
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CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
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};
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register cm_dss_clkstctrl addr(base, 0x0) "This register enables the DSS domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
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_ 20 mbz;
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clkactivity_hdmi_phy_48m_fclk 1 ro type(clkactivity_hdmi_phy_48m_fclk_status) "This field indicates the state of the HDMI_PHY_48MHz_FCLK clock in the domain. [warm reset insensitive]";
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clkactivity_dss_alwon_sys_clk 1 ro type(clkactivity_hdmi_phy_48m_fclk_status) "This field indicates the state of the DSS_ALWON_SYS_CLK clock in the domain. [warm reset insensitive]";
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clkactivity_dss_fclk 1 ro type(clkactivity_hdmi_phy_48m_fclk_status) "This field indicates the state of the DSS_FCLK clock in the domain. [warm reset insensitive]";
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clkactivity_dss_l3_iclk 1 ro type(clkactivity_hdmi_phy_48m_fclk_status) "This field indicates the state of the DSS_L3_ICLK (and DSS_L4_ICLK) clock in the domain. [warm reset insensitive]";
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_ 6 mbz;
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clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the DSS clock domain.";
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};
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constants l3_2_statdep_status width(1) "" {
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L3_2_STATDEP_0 = 0 "Dependency is disabled";
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L3_2_STATDEP_1 = 1 "Dependency is enabled";
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};
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register cm_dss_staticdep addr(base, 0x4) "This register controls the static domain depedencies from DSS domain towards 'target' domains. It is relevant only for domain having system initiator(s)." {
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_ 25 mbz;
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l3_2_statdep 1 rw type(l3_2_statdep_status) "Static dependency towards L3_2 clock domain";
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l3_1_statdep 1 ro type(l3_2_statdep_status) "Static dependency towards L3_1 clock domain";
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memif_statdep 1 rw type(l3_2_statdep_status) "Static dependency towards MEMIF clock domain";
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_ 1 mbz;
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ivahd_statdep 1 rw type(l3_2_statdep_status) "Static dependency towards IVAHD clock domain";
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_ 2 mbz;
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};
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register cm_dss_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from DSS domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." {
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_ 26 mbz;
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l3_1_dyndep 1 ro type(l3_2_statdep_status) "Dynamic dependency towards L3_1 domain";
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_ 5 mbz;
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};
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constants stbyst_status width(1) "" {
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STBYST_0_r = 0 "Module is functional (not in standby)";
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STBYST_1_r = 1 "Module is in standby";
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};
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constants idlest_status width(2) "" {
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IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
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IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
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IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
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IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
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};
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constants optfclken_tv_fclk_status width(1) "" {
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OPTFCLKEN_TV_FCLK_0 = 0 "Optional functional clock is disabled";
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OPTFCLKEN_TV_FCLK_1 = 1 "Optional functional clock is enabled";
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};
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constants modulemode_status width(2) "" {
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MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
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MODULEMODE_1_r = 1 "Reserved";
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MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
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MODULEMODE_3_r = 3 "Reserved";
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};
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register cm_dss_dss_clkctrl addr(base, 0x20) "This register manages the DSS clocks." {
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_ 13 mbz;
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stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
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idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
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_ 4 mbz;
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optfclken_tv_fclk 1 rw type(optfclken_tv_fclk_status) "Optional functional clock control.";
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optfclken_sys_clk 1 rw type(optfclken_tv_fclk_status) "Optional functional clock control.";
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optfclken_48mhz_clk 1 rw type(optfclken_tv_fclk_status) "Optional functional clock control.";
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optfclken_dssclk 1 rw type(optfclken_tv_fclk_status) "Optional functional clock control.";
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_ 6 mbz;
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modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
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};
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}; |