197 lines
6.6 KiB
Python
197 lines
6.6 KiB
Python
# Simple M5 script for use with Barrelfish. This creates a very
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# basic machine with a set of CPUs connected directly to the
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# simulated memory.
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#
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# (See configs/example/* in the M5 distribution for examples of
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# fuller scripts -- caches, etc.).
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# Determine script pathname
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import inspect, os
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import optparse
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import os
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import fatal
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#from O3_ARM_v7a import *
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import CacheConfig
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from Caches import *
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# Try to determine Barrelfish source directory
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# We assume that this script remains in tools/arm_gem5
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bfsrcdir='%s/../..' % os.path.dirname(inspect.getfile(inspect.currentframe()))
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print "Barrelfish source-directory is assume to be %s" % bfsrcdir
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr()
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default = Self.badaddr_responder.pio
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#######################################################################
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#
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# Utility functions
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def setCPUClass(options):
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atomic = False
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if options.cpu_type == "timing":
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class TmpClass(TimingSimpleCPU): pass
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elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
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if not options.caches and not options.ruby:
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print "O3 CPU must be used with caches"
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sys.exit(1)
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if options.cpu_type == "arm_detailed":
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class TmpClass(O3_ARM_v7a_3): pass
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else:
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class TmpClass(DerivO3CPU): pass
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elif options.cpu_type == "inorder":
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if not options.caches:
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print "InOrder CPU must be used with caches"
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sys.exit(1)
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class TmpClass(InOrderCPU): pass
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else:
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class TmpClass(AtomicSimpleCPU): pass
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atomic = True
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CPUClass = None
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test_mem_mode = 'atomic'
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if not atomic:
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test_mem_mode = 'timing'
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return (TmpClass, test_mem_mode, CPUClass)
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#######################################################################
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#
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# Check that we are running on a full-system arm simulator
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if not buildEnv['TARGET_ISA'] == "arm":
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fatal("Expected TARGET_ISA == arm");
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#######################################################################
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#
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# Set up basic configuration options
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parser = optparse.OptionParser()
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parser.add_option("--kernel", action="store", type="string")
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parser.add_option("--ramdisk", action="store", type="string")
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parser.add_option("-n", "--num_cpus", type="int", default=1)
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parser.add_option("--cpu-type", type="choice", default="atomic",
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choices = ["atomic", "arm_detailed"],
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help = "type of cpu to run with")
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parser.add_option("--caches", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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parser.add_option("--l1d_size", type="string", default="64kB")
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parser.add_option("--l1i_size", type="string", default="32kB")
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parser.add_option("--l2_size", type="string", default="2MB")
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parser.add_option("--l3_size", type="string", default="16MB")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=8)
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parser.add_option("--l3_assoc", type="int", default=16)
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parser.add_option("--cacheline_size", type="int", default=64)
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parser.add_option("--loglevel", type="int", default=4)
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parser.add_option("--clock", action="store", type="string", default='1GHz')
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#parser.add_option("--memchecker", action="store_true")
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#parser.add_option("-d", "--detailed", action="store_true")
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parser.add_option("--spec-input", default="ref", type="choice",
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choices=["ref", "test", "train", "smred", "mdred",
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"lgred"],
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help="Input set size for SPEC CPU2000 benchmarks.")
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parser.add_option("--arm-iset", default="arm", type="choice",
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choices=["arm", "thumb", "aarch64"],
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help="ARM instruction set.")
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(options, args) = parser.parse_args()
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#######################################################################
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#
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# Create simulated machine.
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(CPUClass, mem_mode, FutureClass) = setCPUClass(options)
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system = ArmSystem()
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#system = LinuxArmSystem()
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#kernel to boot
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system.kernel = options.kernel
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#memory system
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system.iobus = IOXBar()
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#system.iobus = NoncoherentXBar()
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#system.iobus.forward_latency = 0
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#system.iobus.frontend_latency = 0
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#system.iobus.response_latency = 0
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system.membus = MemBus()
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system.membus.badaddr_responder.warn_access = "warn"
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system.bridge = Bridge(delay='50ns')
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system.bridge.master = system.iobus.slave
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system.bridge.slave = system.membus.master
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system.physmem = SimpleMemory(range = AddrRange('256MB'),conf_table_reported = True)
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system.mem_mode = mem_mode
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#load ramdisk at specific location (256MB = @0x10000000)
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#system.ramdisk = SimpleMemory(range = AddrRange(Addr('256MB'), size = '256MB'), file=options.ramdisk)
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#system.ramdisk.port = system.membus.master
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#CPU(s)
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#CPUClass.clock = "1GHz"
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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#machine type
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system.realview = VExpress_EMM()
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#setup bootloader
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system.realview.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), size = '64MB'), null = True)
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system.realview.nvmem.port = system.membus.master
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# System boot loader is now given relative to source directory
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system.boot_loader = ('%s/tools/aarch64_gem5/boot_emm.aarch64' % bfsrcdir)
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system.highest_el_is_64 = True
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#system.boot_loader_mem = system.realview.nvmem
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#system.realview.setupBootLoader(system.membus, system, '../tools/arm_gem5/boot.arm')
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system.gic_cpu_addr = system.realview.gic.cpu_addr
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system.flags_addr = system.realview.realview_io.pio_addr + 0x30
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boot_flags = 'rw loglevel=%s' % (options.loglevel)
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system.boot_osflags = boot_flags
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system.realview.attachOnChipIO(system.membus, system.bridge)
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system.realview.attachIO(system.iobus)
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system.intrctrl = IntrControl()
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system.terminal = Terminal()
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system.vncserver = VncServer()
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system.physmem.port = system.membus.master
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system.system_port = system.membus.slave
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#Caches
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if options.caches or options.l2cache:
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system.iocache = IOCache(addr_ranges=[system.physmem.range])
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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else:
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system.iobridge = Bridge(delay='50ns',
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ranges = [system.physmem.range])
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system.iobridge.slave = system.iobus.master
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system.iobridge.master = system.membus.slave
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CacheConfig.config_cache(options, system)
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#######################################################################
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#
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# Start simulation
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root = Root(full_system=True, system=system)
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m5.instantiate()
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print '..... STARTING SIMULATION'
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exit_event = m5.simulate()
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exit_cause = exit_event.getCause()
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print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)
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