45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
/**
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* \file
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* \brief Private memory region layout for the Cortex-A57 MPCore
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*/
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/*
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* Copyright (c) 2016 ETH Zurich.
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* All rights reserved.
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*
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* This file is distributed under the terms in the attached LICENSE file.
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* If you do not find this file, copies can be found by writing to:
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* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
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*/
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/* Offsets taken from ARM Cortex A72 MPCore TRM Table 8-1. */
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#ifndef A72MPCORE_MAP_H
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#define A72MPCORE_MAP_H
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/*
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* Offset range from PERIPHBASE[43:18]
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*
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* It lists the address offsets for the GIC blocks relative to the PERIPHBASE
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* base address
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*/
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/* CPU interface */
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#define A72MPCORE_GIC_CPU_OFFSET 0x0000
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#define A72MPCORE_GIC_CPU_SIZE 0x2000
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/* Virtual interface control */
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#define A72MPCORE_GICH_CPU_OFFSET 0x10000
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#define A72MPCORE_GICH_CPU_SIZE 0x1000
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/* Virtual CPU interface (4KB page offset) */
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#define A72MPCORE_GICV_OFFSET 0x20000
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#define A72MPCORE_GICV_SIZE 0x2000
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/* Alias of the Virtual CPU interface (64KB page offset alias) */
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#define A72MPCORE_GICV_OFFSET 0x2F000
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#define A72MPCORE_GICV_SIZE 0x2000
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#endif /* A72MPCORE_MAP_H */
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